first commit
This commit is contained in:
commit
4ca9947ed6
|
|
@ -0,0 +1,68 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 10/13/2023 08:56:30 AM
|
||||
-- Design Name:
|
||||
-- Module Name: blink - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity blink is
|
||||
Port ( clk : in STD_LOGIC; -- CLK_125_N or P (for now no clock, just press button and change led state)?
|
||||
rst : in STD_LOGIC; -- reset, active low, where is this?
|
||||
led7 : out STD_LOGIC); -- TODO: maybe set all others low to turn them off?
|
||||
end blink;
|
||||
|
||||
architecture Behavioral of blink is
|
||||
type state_type is (s00, s01);
|
||||
signal ps, ns : state_type;
|
||||
begin
|
||||
-- GPIO_LED_7 <= GPIO_SW_C;
|
||||
fsm: process (ps)
|
||||
begin
|
||||
case ps is
|
||||
when s00 =>
|
||||
ns <= s01;
|
||||
led7 <= '1';
|
||||
when s01 =>
|
||||
ns <= s00;
|
||||
led7 <= '0';
|
||||
when others =>
|
||||
ns <= s00;
|
||||
led7 <= '0';
|
||||
end case;
|
||||
end process;
|
||||
process (clk, rst)
|
||||
begin
|
||||
if rst = '1' then
|
||||
ps <= s00;
|
||||
else
|
||||
ps <= ns;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 10/14/2023 12:29:16 PM
|
||||
-- Design Name:
|
||||
-- Module Name: blink_tb - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity blink_tb is
|
||||
-- Port ( CLK_125_N : in STD_LOGIC;
|
||||
-- GPIO_SW_C : in STD_LOGIC;
|
||||
-- GPIO_LED_7 : out STD_LOGIC);
|
||||
end blink_tb;
|
||||
|
||||
architecture test of blink_tb is
|
||||
signal CLK_125_N : STD_LOGIC := '0';
|
||||
signal GPIO_SW_C : STD_LOGIC := '0';
|
||||
signal GPIO_LED_7 : STD_LOGIC := '0';
|
||||
begin
|
||||
dut: entity work.blink
|
||||
port map(
|
||||
CLK_125_N => CLK_125_N,
|
||||
GPIO_SW_C => GPIO_SW_C,
|
||||
GPIO_LED_7 => GPIO_LED_7
|
||||
);
|
||||
CLK_125_N <= not CLK_125_N after 1 ps;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
|
||||
GPIO_SW_C <= '1';
|
||||
wait for 10 ps;
|
||||
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
|
||||
GPIO_SW_C <= '0';
|
||||
|
||||
wait for 1 ns;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
-- process
|
||||
-- begin
|
||||
-- GPIO_SW_C <= '0';
|
||||
-- wait for 10 ns;
|
||||
-- GPIO_SW_C <= '1';
|
||||
-- wait for 10 ns;
|
||||
-- end process;
|
||||
|
||||
end test;
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity clock_divider is
|
||||
Port (
|
||||
reset : in STD_LOGIC;
|
||||
clock : in STD_LOGIC;
|
||||
divided_clocks : out STD_LOGIC_VECTOR(31 downto 0)
|
||||
);
|
||||
end entity clock_divider;
|
||||
|
||||
architecture Behavioral of clock_divider is
|
||||
signal div_clks : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
|
||||
begin
|
||||
process (clock)
|
||||
begin
|
||||
if rising_edge(clock) then
|
||||
div_clks <= div_clks + 1;
|
||||
end if;
|
||||
end process;
|
||||
divided_clocks <= div_clks;
|
||||
end architecture Behavioral;
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
--------------------------------------------------------------------------
|
||||
-- File : clkreset.vhd
|
||||
----------------------------------------------------------------------------
|
||||
-- Description : Wrapper for clock PLL and reset logic
|
||||
--
|
||||
-- External 'p_reset' input resets the PLL immediately and sets the 'reset'
|
||||
-- active high to the internal FPGA logic.
|
||||
-- When the reset goes inactive the PLL will try to generate the requested
|
||||
-- output freq clock 'clk_i' for the FPGA internal logic from the 'p_clk' input.
|
||||
-- Once the PLL output clock is stable the PLL sets the 'pll_locked' output high.
|
||||
-- A counter then increments to 255 and then the 'reset' output is set low
|
||||
-- to allow the FPGA logic to run.
|
||||
--
|
||||
-- *** Check p_reset_n polarity, design assumes active low ***
|
||||
--
|
||||
----------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
|
||||
entity clkreset is
|
||||
port(
|
||||
-- Reset and clock from pads
|
||||
p_reset : in std_logic; -- From RESET input pad
|
||||
p_clk_n : in std_logic; -- From CLOCK input pad, N
|
||||
p_clk_p : in std_logic; -- From CLOCK input pad, P
|
||||
|
||||
-- Reset and clock outputs to all internal logic
|
||||
clk : out std_logic;
|
||||
lock : out std_logic;
|
||||
reset : out std_logic
|
||||
);
|
||||
end clkreset;
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Structural architecture instantiates a vendor IP block clock tile.
|
||||
------------------------------------------------------------------------
|
||||
architecture struct of clkreset is
|
||||
|
||||
signal pll_locked : std_logic;
|
||||
signal pll_locked_d1 : std_logic := '0';
|
||||
signal clk_i : std_logic;
|
||||
signal cnt_reset : unsigned(7 downto 0) := X"00";
|
||||
signal reset_pll : std_logic;
|
||||
|
||||
-- Clock generator IP. Use MMCM or PLL
|
||||
-- component clkpll
|
||||
-- port (
|
||||
-- refclk : in std_logic := '0'; -- refclk.clk
|
||||
-- reset : in std_logic := '0'; -- reset.reset
|
||||
-- outclk_0 : out std_logic; -- outclk0.clk
|
||||
-- locked : out std_logic -- locked.export
|
||||
-- );
|
||||
-- end component;
|
||||
component clk_wiz_0
|
||||
port (-- Clock in ports
|
||||
-- Clock out ports
|
||||
outclk_0 : out std_logic;
|
||||
-- Status and control signals
|
||||
reset : in std_logic;
|
||||
locked : out std_logic;
|
||||
clk_in1_p : in std_logic; -- refclk, P
|
||||
clk_in1_n : in std_logic -- refclk, N
|
||||
);
|
||||
end component;
|
||||
begin
|
||||
|
||||
clk <= clk_i;
|
||||
lock <= pll_locked_d1;
|
||||
reset_pll <= p_reset;
|
||||
|
||||
---------------------------------------------------------------------------------
|
||||
-- Clock generator. 100 MHz clock from XX MHz board clock input
|
||||
---------------------------------------------------------------------------------
|
||||
-- u_clkpll : clkpll
|
||||
-- port map(
|
||||
-- refclk => p_clk , -- in std_logic := '0'; -- refclk.clk
|
||||
-- reset => reset_pll , -- in std_logic := '0'; -- reset.reset
|
||||
-- outclk_0 => clk_i , -- out std_logic; -- outclk0.clk
|
||||
-- locked => pll_locked -- out std_logic -- locked.export
|
||||
-- );
|
||||
u_clkpll : clk_wiz_0
|
||||
port map (
|
||||
-- Clock out ports
|
||||
outclk_0 => clk_i, -- out
|
||||
-- Status and control signals
|
||||
reset => reset_pll, -- in
|
||||
locked => pll_locked, -- out
|
||||
-- Clock in ports
|
||||
clk_in1_p => p_clk_p, -- in
|
||||
clk_in1_n => p_clk_n -- in
|
||||
);
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
-- Keep main logic reset until PLL locked for 255 clock cycles
|
||||
-------------------------------------------------------------------------------
|
||||
pr_reset : process (p_reset, pll_locked, clk_i)
|
||||
begin
|
||||
if (p_reset = '1' or pll_locked = '0') then
|
||||
reset <= '1';
|
||||
pll_locked_d1 <= '0';
|
||||
cnt_reset <= X"00";
|
||||
|
||||
elsif rising_edge(clk_i) then
|
||||
|
||||
pll_locked_d1 <= pll_locked;
|
||||
|
||||
if (pll_locked_d1 = '1' and cnt_reset < X"FF") then
|
||||
cnt_reset <= cnt_reset + 1;
|
||||
end if;
|
||||
|
||||
if (cnt_reset < X"FF") then
|
||||
reset <= '1';
|
||||
else
|
||||
reset <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end struct;
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
vlib work
|
||||
vcom *.vhd
|
||||
vsim -voptargs="+acc" -t 1ps -lib work top_tb
|
||||
do wave.do
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
run -all
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 10/13/2023 08:56:30 AM
|
||||
-- Design Name:
|
||||
-- Module Name: blink - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity top is
|
||||
Port ( CLK_125_N : in STD_LOGIC; -- CLK_125_N or P (for now no clock, just press button and change led state)?
|
||||
GPIO_SW_C : in STD_LOGIC; -- reset, active low, where is this?
|
||||
GPIO_LED_7 : out STD_LOGIC; -- TODO: is there ways to concatenate these?
|
||||
GPIO_LED_6 : out STD_LOGIC;
|
||||
GPIO_LED_5 : out STD_LOGIC;
|
||||
GPIO_LED_4 : out STD_LOGIC;
|
||||
GPIO_LED_3 : out STD_LOGIC;
|
||||
GPIO_LED_2 : out STD_LOGIC;
|
||||
GPIO_LED_1 : out STD_LOGIC;
|
||||
GPIO_LED_0 : out STD_LOGIC);
|
||||
end top;
|
||||
|
||||
architecture Behavioral of top is
|
||||
signal div_clks : STD_LOGIC_VECTOR(31 downto 0);
|
||||
-- TODO: set below to an integer value to select which clock you want
|
||||
-- signal whichClock : STD_LOGIC;
|
||||
signal clkSelect : STD_LOGIC; -- Assuming you use this signal as an output
|
||||
signal CLOCK_50 : STD_LOGIC;
|
||||
|
||||
begin
|
||||
-- Connect the instantiated clock divider
|
||||
cdiv : entity work.clock_divider
|
||||
port map (
|
||||
clock => CLK_125_N, -- Connect to your clock source
|
||||
reset => GPIO_SW_C, -- Connect to your reset signal
|
||||
divided_clocks => div_clks
|
||||
);
|
||||
|
||||
-- change the value to a higher one to see a slower blinking
|
||||
GPIO_LED_7 <= GPIO_SW_C;
|
||||
GPIO_LED_6 <= div_clks(27);
|
||||
GPIO_LED_5 <= div_clks(26);
|
||||
GPIO_LED_4 <= div_clks(25);
|
||||
GPIO_LED_3 <= div_clks(24);
|
||||
GPIO_LED_2 <= div_clks(23);
|
||||
GPIO_LED_1 <= div_clks(22);
|
||||
GPIO_LED_0 <= div_clks(21);
|
||||
|
||||
|
||||
-- Other logic for your designs
|
||||
end Behavioral;
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 10/14/2023 12:29:16 PM
|
||||
-- Design Name:
|
||||
-- Module Name: top_tb - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool Versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx leaf cells in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity top_tb is
|
||||
end top_tb;
|
||||
|
||||
architecture test of top_tb is
|
||||
signal CLK_125_N : STD_LOGIC := '0';
|
||||
signal GPIO_SW_C : STD_LOGIC := '0';
|
||||
signal GPIO_LED_7 : STD_LOGIC := '0';
|
||||
signal GPIO_LED_6 : STD_LOGIC := '0';
|
||||
signal GPIO_LED_5 : STD_LOGIC := '0';
|
||||
signal GPIO_LED_4 : STD_LOGIC := '0';
|
||||
signal GPIO_LED_3 : STD_LOGIC := '0';
|
||||
signal GPIO_LED_2 : STD_LOGIC := '0';
|
||||
signal GPIO_LED_1 : STD_LOGIC := '0';
|
||||
signal GPIO_LED_0 : STD_LOGIC := '0';
|
||||
begin
|
||||
dut: entity work.top
|
||||
port map(
|
||||
CLK_125_N => CLK_125_N,
|
||||
GPIO_SW_C => GPIO_SW_C,
|
||||
GPIO_LED_7 => GPIO_LED_7,
|
||||
GPIO_LED_6 => GPIO_LED_6,
|
||||
GPIO_LED_5 => GPIO_LED_5,
|
||||
GPIO_LED_4 => GPIO_LED_4,
|
||||
GPIO_LED_3 => GPIO_LED_3,
|
||||
GPIO_LED_2 => GPIO_LED_2,
|
||||
GPIO_LED_1 => GPIO_LED_1,
|
||||
GPIO_LED_0 => GPIO_LED_0
|
||||
);
|
||||
CLK_125_N <= not CLK_125_N after 1 ps;
|
||||
|
||||
|
||||
-- Stimulus process
|
||||
process
|
||||
begin
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
|
||||
GPIO_SW_C <= '1';
|
||||
wait for 10 ps;
|
||||
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
wait until rising_edge(CLK_125_N);
|
||||
|
||||
GPIO_SW_C <= '0';
|
||||
|
||||
wait for 1 ns;
|
||||
|
||||
wait;
|
||||
end process;
|
||||
|
||||
end test;
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /top_tb/dut/CLK_125_N
|
||||
add wave -noupdate /top_tb/dut/GPIO_SW_C
|
||||
add wave -noupdate /top_tb/dut/GPIO_LED_7
|
||||
add wave -noupdate /top_tb/dut/GPIO_LED_6
|
||||
add wave -noupdate /top_tb/dut/GPIO_LED_5
|
||||
add wave -noupdate /top_tb/dut/GPIO_LED_4
|
||||
add wave -noupdate /top_tb/dut/GPIO_LED_3
|
||||
add wave -noupdate /top_tb/dut/GPIO_LED_2
|
||||
add wave -noupdate /top_tb/dut/GPIO_LED_1
|
||||
add wave -noupdate /top_tb/dut/GPIO_LED_0
|
||||
add wave -noupdate /top_tb/dut/clkSelect
|
||||
add wave -noupdate /top_tb/dut/div_clks
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {0 ps} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ps} {1616433 ps}
|
||||
Loading…
Reference in New Issue