109 lines
3.2 KiB
VHDL
109 lines
3.2 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10/14/2023 12:29:16 PM
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-- Design Name:
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-- Module Name: top_tb - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity top_tb is
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end top_tb;
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architecture test of top_tb is
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signal CLK_125_N : STD_LOGIC := '0';
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signal GPIO_SW_C : STD_LOGIC := '0';
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signal GPIO_LED_7 : STD_LOGIC := '0';
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signal GPIO_LED_6 : STD_LOGIC := '0';
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signal GPIO_LED_5 : STD_LOGIC := '0';
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signal GPIO_LED_4 : STD_LOGIC := '0';
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signal GPIO_LED_3 : STD_LOGIC := '0';
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signal GPIO_LED_2 : STD_LOGIC := '0';
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signal GPIO_LED_1 : STD_LOGIC := '0';
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signal GPIO_LED_0 : STD_LOGIC := '0';
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begin
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dut: entity work.top
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port map(
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CLK_125_N => CLK_125_N,
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GPIO_SW_C => GPIO_SW_C,
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GPIO_LED_7 => GPIO_LED_7,
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GPIO_LED_6 => GPIO_LED_6,
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GPIO_LED_5 => GPIO_LED_5,
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GPIO_LED_4 => GPIO_LED_4,
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GPIO_LED_3 => GPIO_LED_3,
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GPIO_LED_2 => GPIO_LED_2,
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GPIO_LED_1 => GPIO_LED_1,
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GPIO_LED_0 => GPIO_LED_0
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);
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CLK_125_N <= not CLK_125_N after 1 ps;
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-- Stimulus process
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process
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begin
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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GPIO_SW_C <= '1';
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wait for 10 ps;
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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wait until rising_edge(CLK_125_N);
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GPIO_SW_C <= '0';
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wait for 1 ns;
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wait;
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end process;
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end test;
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