77 lines
2.3 KiB
VHDL
77 lines
2.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10/13/2023 08:56:30 AM
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-- Design Name:
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-- Module Name: blink - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity top is
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Port ( CLK_125_N : in STD_LOGIC; -- CLK_125_N or P (for now no clock, just press button and change led state)?
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GPIO_SW_C : in STD_LOGIC; -- reset, active low, where is this?
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GPIO_LED_7 : out STD_LOGIC; -- TODO: is there ways to concatenate these?
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GPIO_LED_6 : out STD_LOGIC;
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GPIO_LED_5 : out STD_LOGIC;
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GPIO_LED_4 : out STD_LOGIC;
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GPIO_LED_3 : out STD_LOGIC;
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GPIO_LED_2 : out STD_LOGIC;
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GPIO_LED_1 : out STD_LOGIC;
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GPIO_LED_0 : out STD_LOGIC);
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end top;
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architecture Behavioral of top is
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signal div_clks : STD_LOGIC_VECTOR(31 downto 0);
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-- TODO: set below to an integer value to select which clock you want
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-- signal whichClock : STD_LOGIC;
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signal clkSelect : STD_LOGIC; -- Assuming you use this signal as an output
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signal CLOCK_50 : STD_LOGIC;
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begin
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-- Connect the instantiated clock divider
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cdiv : entity work.clock_divider
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port map (
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clock => CLK_125_N, -- Connect to your clock source
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reset => GPIO_SW_C, -- Connect to your reset signal
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divided_clocks => div_clks
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);
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-- change the value to a higher one to see a slower blinking
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GPIO_LED_7 <= GPIO_SW_C;
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GPIO_LED_6 <= div_clks(27);
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GPIO_LED_5 <= div_clks(26);
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GPIO_LED_4 <= div_clks(25);
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GPIO_LED_3 <= div_clks(24);
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GPIO_LED_2 <= div_clks(23);
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GPIO_LED_1 <= div_clks(22);
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GPIO_LED_0 <= div_clks(21);
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-- Other logic for your designs
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end Behavioral;
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