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-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/13/2023 08:56:30 AM
-- Design Name: 
-- Module Name: blink - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port ( CLK_125_N : in STD_LOGIC;  -- CLK_125_N or P (for now no clock, just press button and change led state)?
           GPIO_SW_C : in STD_LOGIC;  -- reset, active low, where is this?
           GPIO_LED_7 : out STD_LOGIC;  -- TODO: is there ways to concatenate these?
           GPIO_LED_6 : out STD_LOGIC;
           GPIO_LED_5 : out STD_LOGIC;
           GPIO_LED_4 : out STD_LOGIC;
           GPIO_LED_3 : out STD_LOGIC;
           GPIO_LED_2 : out STD_LOGIC;
           GPIO_LED_1 : out STD_LOGIC;
           GPIO_LED_0 : out STD_LOGIC);
end top;

architecture Behavioral of top is
    signal div_clks : STD_LOGIC_VECTOR(31 downto 0);
    -- TODO: set below to an integer value to select which clock you want
    -- signal whichClock : STD_LOGIC;
    signal clkSelect : STD_LOGIC;  -- Assuming you use this signal as an output
    signal CLOCK_50 : STD_LOGIC;

begin
    -- Connect the instantiated clock divider
    cdiv : entity work.clock_divider
        port map (
            clock => CLK_125_N,  -- Connect to your clock source
            reset => GPIO_SW_C,  -- Connect to your reset signal
            divided_clocks => div_clks
        );

    -- change the value to a higher one to see a slower blinking
    GPIO_LED_7 <= GPIO_SW_C;
    GPIO_LED_6 <= div_clks(27);
    GPIO_LED_5 <= div_clks(26);
    GPIO_LED_4 <= div_clks(25);
    GPIO_LED_3 <= div_clks(24);
    GPIO_LED_2 <= div_clks(23);
    GPIO_LED_1 <= div_clks(22);
    GPIO_LED_0 <= div_clks(21);


    -- Other logic for your designs
end Behavioral;