25 lines
614 B
VHDL
25 lines
614 B
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity clock_divider is
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Port (
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reset : in STD_LOGIC;
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clock : in STD_LOGIC;
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divided_clocks : out STD_LOGIC_VECTOR(31 downto 0)
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);
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end entity clock_divider;
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architecture Behavioral of clock_divider is
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signal div_clks : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
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begin
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process (clock)
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begin
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if rising_edge(clock) then
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div_clks <= div_clks + 1;
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end if;
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end process;
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divided_clocks <= div_clks;
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end architecture Behavioral;
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