library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock_divider is
    Port (
        reset : in STD_LOGIC;
        clock : in STD_LOGIC;
        divided_clocks : out STD_LOGIC_VECTOR(31 downto 0)
    );
end entity clock_divider;

architecture Behavioral of clock_divider is
    signal div_clks : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
    process (clock)
    begin
        if rising_edge(clock) then
            div_clks <= div_clks + 1;
        end if;
    end process;
    divided_clocks <= div_clks;
end architecture Behavioral;