69 lines
1.7 KiB
VHDL
69 lines
1.7 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10/13/2023 08:56:30 AM
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-- Design Name:
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-- Module Name: blink - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity blink is
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Port ( clk : in STD_LOGIC; -- CLK_125_N or P (for now no clock, just press button and change led state)?
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rst : in STD_LOGIC; -- reset, active low, where is this?
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led7 : out STD_LOGIC); -- TODO: maybe set all others low to turn them off?
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end blink;
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architecture Behavioral of blink is
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type state_type is (s00, s01);
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signal ps, ns : state_type;
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begin
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-- GPIO_LED_7 <= GPIO_SW_C;
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fsm: process (ps)
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begin
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case ps is
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when s00 =>
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ns <= s01;
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led7 <= '1';
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when s01 =>
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ns <= s00;
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led7 <= '0';
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when others =>
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ns <= s00;
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led7 <= '0';
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end case;
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end process;
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process (clk, rst)
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begin
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if rst = '1' then
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ps <= s00;
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else
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ps <= ns;
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end if;
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end process;
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end Behavioral;
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