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-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/13/2023 08:56:30 AM
-- Design Name: 
-- Module Name: blink - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity blink is
    Port ( clk : in STD_LOGIC;  -- CLK_125_N or P (for now no clock, just press button and change led state)?
           rst : in STD_LOGIC;  -- reset, active low, where is this?
           led7 : out STD_LOGIC);  -- TODO: maybe set all others low to turn them off?
end blink;

architecture Behavioral of blink is
    type state_type is (s00, s01);
    signal ps, ns : state_type;
begin
    -- GPIO_LED_7 <= GPIO_SW_C;
    fsm: process (ps)
    begin
        case ps is
            when s00 =>
                ns <= s01;
                led7 <= '1';
            when s01 =>
                ns <= s00;
                led7 <= '0';
            when others =>
                ns <= s00;
                led7 <= '0';
        end case;
    end process;
        process (clk, rst)
    begin
        if rst = '1' then
            ps <= s00;
        else
            ps <= ns;
        end if;
    end process;
end Behavioral;