reg results should be signed

src/hdl/CPU_pipelined.sv

@@ -262,11 +262,13 @@ module CPU_pipelined_testbench();
         end
 
         for (i = 0; i < 32; i = i + 1) begin
-            $display("X%0d = %0d", i, dut.u_regfile.dataBus[i]);
+            $display("X%0d = %0d", i, $signed(dut.u_regfile.dataBus[i]));
         end
 
         // Addtional signals to display
-
+        // $display("Mem[0] = %0d", dut.dmem.mem[0]);
+        // $display("Mem[8] = %0d", dut.dmem.mem[8]);
+        // $display("Mem[16] = %0d", dut.dmem.mem[16]);
         // 
 
         $display("PC = %0d", dut.pcIF / 4);

tools/sim/runs/sim.do

@@ -1,5 +1,5 @@
 # Change to path to the benchmark to simulate
-set bench_path ../Benchmarks/test04_LdurStur.arm
+set bench_path ../Benchmarks/test12_Fibonacci.arm
 
 vlib work