From 7b911f354a00c7f0184530295f2e6724f8e283bc Mon Sep 17 00:00:00 2001 From: Eric Yu Date: Sat, 5 Oct 2024 01:03:20 -0700 Subject: [PATCH] reg results should be signed --- src/hdl/CPU_pipelined.sv | 6 ++++-- tools/sim/runs/sim.do | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/hdl/CPU_pipelined.sv b/src/hdl/CPU_pipelined.sv index 624d30e..2291f12 100644 --- a/src/hdl/CPU_pipelined.sv +++ b/src/hdl/CPU_pipelined.sv @@ -262,11 +262,13 @@ module CPU_pipelined_testbench(); end for (i = 0; i < 32; i = i + 1) begin - $display("X%0d = %0d", i, dut.u_regfile.dataBus[i]); + $display("X%0d = %0d", i, $signed(dut.u_regfile.dataBus[i])); end // Addtional signals to display - + // $display("Mem[0] = %0d", dut.dmem.mem[0]); + // $display("Mem[8] = %0d", dut.dmem.mem[8]); + // $display("Mem[16] = %0d", dut.dmem.mem[16]); // $display("PC = %0d", dut.pcIF / 4); diff --git a/tools/sim/runs/sim.do b/tools/sim/runs/sim.do index 46c19e7..36c4de8 100644 --- a/tools/sim/runs/sim.do +++ b/tools/sim/runs/sim.do @@ -1,5 +1,5 @@ # Change to path to the benchmark to simulate -set bench_path ../Benchmarks/test04_LdurStur.arm +set bench_path ../Benchmarks/test12_Fibonacci.arm vlib work