Eric Yu eyhc
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Pipline_Arm_CPU
SystemVerilog 0 0
The simulated 64-bit Arm CPU was written in SystemVerilog.
Updated 2024-10-05 08:03:47 +00:00
rendercv
Python 0 0
Generate CV from YAML file
Updated 2024-08-01 16:02:38 +00:00
Regfile
SystemVerilog 0 0
Regfile design from the 5-stage CPU
Updated 2024-07-09 14:10:55 +00:00
PulseChannelUnVerified
VHDL 0 0
Updated 2024-05-02 06:34:01 +00:00
nanoq_laser_pulse_channel
0 0
Updated 2024-03-07 01:31:50 +00:00
VLSI_II
Python 0 0
Dumpster repo for EE 477 VLSI II course at UW
Updated 2024-03-02 20:59:29 +00:00
sshcec
Python 0 0
Custom TightVNC for UW ECE. Project EOL in favor of existing MobaXterm
Updated 2024-01-12 08:19:39 +00:00
MCMod_HDL_1_10
Java 0 0
Forge 1.10.1 mod that converts basic Verilog code into Minecraft builds, based from https://github.com/itsfrank/MinecraftHDL
Updated 2024-01-06 02:48:03 +00:00
ZCU_Start
VHDL 0 0
A "Hello World" Program for ZCU102 using Vivado and VHDL language
Updated 2024-01-06 02:41:08 +00:00
Read-Sensor-Resistances
Python 0 0
Updated 2023-05-07 21:37:04 +00:00