; Copyright 1991-2009 Mentor Graphics Corporation ; ; All Rights Reserved. ; ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. ; [Library] others = $MODEL_TECH/../modelsim.ini ; Altera Primitive libraries ; ; VHDL Section ; ; ; Verilog Section ; secureip = E:/xilinx_libs/secureip unisim = E:/xilinx_libs/unisim unimacro = E:/xilinx_libs/unimacro unifast = E:/xilinx_libs/unifast unisims_ver = E:/xilinx_libs/unisims_ver unimacro_ver = E:/xilinx_libs/unimacro_ver unifast_ver = E:/xilinx_libs/unifast_ver simprims_ver = E:/xilinx_libs/simprims_ver xpm = E:/xilinx_libs/xpm xilinx_vip = E:/xilinx_libs/xilinx_vip adc_dac_if_phy_v1_0_0 = E:/xilinx_libs/adc_dac_if_phy_v1_0_0 advanced_io_wizard_phy_v1_0_0 = E:/xilinx_libs/advanced_io_wizard_phy_v1_0_0 advanced_io_wizard_v1_0_7 = E:/xilinx_libs/advanced_io_wizard_v1_0_7 ahblite_axi_bridge_v3_0_21 = E:/xilinx_libs/ahblite_axi_bridge_v3_0_21 ai_noc = E:/xilinx_libs/ai_noc ai_pl_trig = E:/xilinx_libs/ai_pl_trig ai_pl = E:/xilinx_libs/ai_pl an_lt_v1_0_6 = E:/xilinx_libs/an_lt_v1_0_6 audio_clock_recovery_unit_v1_0_2 = E:/xilinx_libs/audio_clock_recovery_unit_v1_0_2 audio_tpg_v1_0_0 = E:/xilinx_libs/audio_tpg_v1_0_0 av_pat_gen_v1_0_1 = E:/xilinx_libs/av_pat_gen_v1_0_1 av_pat_gen_v2_0_0 = E:/xilinx_libs/av_pat_gen_v2_0_0 axis_cap_ctrl_v1_0_0 = E:/xilinx_libs/axis_cap_ctrl_v1_0_0 axis_dbg_stub_v1_0_0 = E:/xilinx_libs/axis_dbg_stub_v1_0_0 axis_dbg_sync_v1_0_0 = E:/xilinx_libs/axis_dbg_sync_v1_0_0 axis_ila_adv_trig_v1_0_0 = E:/xilinx_libs/axis_ila_adv_trig_v1_0_0 axis_ila_ct_v1_0_0 = E:/xilinx_libs/axis_ila_ct_v1_0_0 axis_ila_pp_v1_0_0 = E:/xilinx_libs/axis_ila_pp_v1_0_0 axis_ila_txns_cntr_v1_0_0 = E:/xilinx_libs/axis_ila_txns_cntr_v1_0_0 axis_infrastructure_v1_1_0 = E:/xilinx_libs/axis_infrastructure_v1_1_0 axis_itct_v1_0_0 = E:/xilinx_libs/axis_itct_v1_0_0 axis_mem_v1_0_0 = E:/xilinx_libs/axis_mem_v1_0_0 axis_mu_v1_0_0 = E:/xilinx_libs/axis_mu_v1_0_0 axis_protocol_checker_v2_0_10 = E:/xilinx_libs/axis_protocol_checker_v2_0_10 axi_ahblite_bridge_v3_0_23 = E:/xilinx_libs/axi_ahblite_bridge_v3_0_23 axi_amm_bridge_v1_0_16 = E:/xilinx_libs/axi_amm_bridge_v1_0_16 axi_bram_ctrl_v4_1_6 = E:/xilinx_libs/axi_bram_ctrl_v4_1_6 axi_chip2chip_v5_0_15 = E:/xilinx_libs/axi_chip2chip_v5_0_15 axi_dbg_hub = E:/xilinx_libs/axi_dbg_hub axi_infrastructure_v1_1_0 = E:/xilinx_libs/axi_infrastructure_v1_1_0 axi_jtag_v1_0_0 = E:/xilinx_libs/axi_jtag_v1_0_0 axi_lite_ipif_v3_0_4 = E:/xilinx_libs/axi_lite_ipif_v3_0_4 axi_lmb_bridge_v1_0_0 = E:/xilinx_libs/axi_lmb_bridge_v1_0_0 axi_pcie3_v3_0_22 = E:/xilinx_libs/axi_pcie3_v3_0_22 axi_perf_mon_v5_0_28 = E:/xilinx_libs/axi_perf_mon_v5_0_28 axi_pmon_v1_0_0 = E:/xilinx_libs/axi_pmon_v1_0_0 axi_remapper_rx_v1_0_0 = E:/xilinx_libs/axi_remapper_rx_v1_0_0 axi_remapper_tx_v1_0_0 = E:/xilinx_libs/axi_remapper_tx_v1_0_0 blk_mem_gen_v8_3_6 = E:/xilinx_libs/blk_mem_gen_v8_3_6 blk_mem_gen_v8_4_5 = E:/xilinx_libs/blk_mem_gen_v8_4_5 bsip_v1_1_0 = E:/xilinx_libs/bsip_v1_1_0 bs_mux_v1_0_0 = E:/xilinx_libs/bs_mux_v1_0_0 cam_v2_3_0 = E:/xilinx_libs/cam_v2_3_0 clk_gen_sim_v1_0_2 = E:/xilinx_libs/clk_gen_sim_v1_0_2 clk_vip_v1_0_2 = E:/xilinx_libs/clk_vip_v1_0_2 cmac_usplus_v3_1_9 = E:/xilinx_libs/cmac_usplus_v3_1_9 cmac_v2_6_7 = E:/xilinx_libs/cmac_v2_6_7 compact_gt_v1_0_12 = E:/xilinx_libs/compact_gt_v1_0_12 cpm4_v1_0_8 = E:/xilinx_libs/cpm4_v1_0_8 cpm5_v1_0_8 = E:/xilinx_libs/cpm5_v1_0_8 dcmac_v2_0_0 = E:/xilinx_libs/dcmac_v2_0_0 ddr4_pl_phy_v1_0_0 = E:/xilinx_libs/ddr4_pl_phy_v1_0_0 ddr4_pl_v1_0_8 = E:/xilinx_libs/ddr4_pl_v1_0_8 displayport_v8_1_5 = E:/xilinx_libs/displayport_v8_1_5 dist_mem_gen_v8_0_13 = E:/xilinx_libs/dist_mem_gen_v8_0_13 dprx_fec_8b10b_v1_0_1 = E:/xilinx_libs/dprx_fec_8b10b_v1_0_1 dp_videoaxi4s_bridge_v1_0_1 = E:/xilinx_libs/dp_videoaxi4s_bridge_v1_0_1 ecc_v2_0_13 = E:/xilinx_libs/ecc_v2_0_13 emb_fifo_gen_v1_0_2 = E:/xilinx_libs/emb_fifo_gen_v1_0_2 emb_mem_gen_v1_0_6 = E:/xilinx_libs/emb_mem_gen_v1_0_6 emc_common_v3_0_5 = E:/xilinx_libs/emc_common_v3_0_5 ethernet_1_10_25g_v2_7_5 = E:/xilinx_libs/ethernet_1_10_25g_v2_7_5 fast_adapter_v1_0_3 = E:/xilinx_libs/fast_adapter_v1_0_3 fifo_generator_v13_0_6 = E:/xilinx_libs/fifo_generator_v13_0_6 fifo_generator_v13_1_4 = E:/xilinx_libs/fifo_generator_v13_1_4 fifo_generator_v13_2_7 = E:/xilinx_libs/fifo_generator_v13_2_7 fit_timer_v2_0_10 = E:/xilinx_libs/fit_timer_v2_0_10 generic_baseblocks_v2_1_0 = E:/xilinx_libs/generic_baseblocks_v2_1_0 gigantic_mux = E:/xilinx_libs/gigantic_mux gig_ethernet_pcs_pma_v16_2_8 = E:/xilinx_libs/gig_ethernet_pcs_pma_v16_2_8 gmii_to_rgmii_v4_1_4 = E:/xilinx_libs/gmii_to_rgmii_v4_1_4 gtwizard_ultrascale_v1_5_4 = E:/xilinx_libs/gtwizard_ultrascale_v1_5_4 gtwizard_ultrascale_v1_6_13 = E:/xilinx_libs/gtwizard_ultrascale_v1_6_13 gtwizard_ultrascale_v1_7_13 = E:/xilinx_libs/gtwizard_ultrascale_v1_7_13 hbm2e_pl_v1_0_0 = E:/xilinx_libs/hbm2e_pl_v1_0_0 hbm_v1_0_12 = E:/xilinx_libs/hbm_v1_0_12 hdcp22_cipher_dp_v1_0_0 = E:/xilinx_libs/hdcp22_cipher_dp_v1_0_0 hdcp22_cipher_v1_0_3 = E:/xilinx_libs/hdcp22_cipher_v1_0_3 hdcp22_rng_v1_0_1 = E:/xilinx_libs/hdcp22_rng_v1_0_1 hdcp_keymngmt_blk_v1_0_0 = E:/xilinx_libs/hdcp_keymngmt_blk_v1_0_0 hdcp_v1_0_3 = E:/xilinx_libs/hdcp_v1_0_3 hdmi_acr_ctrl_v1_0_0 = E:/xilinx_libs/hdmi_acr_ctrl_v1_0_0 hdmi_gt_controller_v1_0_7 = E:/xilinx_libs/hdmi_gt_controller_v1_0_7 high_speed_selectio_wiz_v3_6_3 = E:/xilinx_libs/high_speed_selectio_wiz_v3_6_3 i2s_receiver_v1_0_5 = E:/xilinx_libs/i2s_receiver_v1_0_5 i2s_transmitter_v1_0_5 = E:/xilinx_libs/i2s_transmitter_v1_0_5 ibert_lib_v1_0_7 = E:/xilinx_libs/ibert_lib_v1_0_7 ieee802d3_clause74_fec_v1_0_13 = E:/xilinx_libs/ieee802d3_clause74_fec_v1_0_13 ilknf_v1_1_0 = E:/xilinx_libs/ilknf_v1_1_0 interlaken_v2_4_11 = E:/xilinx_libs/interlaken_v2_4_11 in_system_ibert_v1_0_16 = E:/xilinx_libs/in_system_ibert_v1_0_16 iomodule_v3_1_8 = E:/xilinx_libs/iomodule_v3_1_8 jesd204c_v4_2_8 = E:/xilinx_libs/jesd204c_v4_2_8 jesd204_v7_2_15 = E:/xilinx_libs/jesd204_v7_2_15 jtag_axi = E:/xilinx_libs/jtag_axi lib_cdc_v1_0_2 = E:/xilinx_libs/lib_cdc_v1_0_2 lib_pkg_v1_0_2 = E:/xilinx_libs/lib_pkg_v1_0_2 ll_compress_v1_0_0 = E:/xilinx_libs/ll_compress_v1_0_0 ll_compress_v1_1_0 = E:/xilinx_libs/ll_compress_v1_1_0 ll_compress_v2_0_1 = E:/xilinx_libs/ll_compress_v2_0_1 ll_compress_v2_1_0 = E:/xilinx_libs/ll_compress_v2_1_0 lmb_bram_if_cntlr_v4_0_21 = E:/xilinx_libs/lmb_bram_if_cntlr_v4_0_21 lmb_v10_v3_0_12 = E:/xilinx_libs/lmb_v10_v3_0_12 ltlib_v1_0_0 = E:/xilinx_libs/ltlib_v1_0_0 lut_buffer_v2_0_0 = E:/xilinx_libs/lut_buffer_v2_0_0 l_ethernet_v3_3_0 = E:/xilinx_libs/l_ethernet_v3_3_0 mammoth_transcode_v1_0_0 = E:/xilinx_libs/mammoth_transcode_v1_0_0 mem_pl_v1_0_0 = E:/xilinx_libs/mem_pl_v1_0_0 microblaze_v11_0_9 = E:/xilinx_libs/microblaze_v11_0_9 microblaze_v9_5_4 = E:/xilinx_libs/microblaze_v9_5_4 mipi_csi2_rx_ctrl_v1_0_8 = E:/xilinx_libs/mipi_csi2_rx_ctrl_v1_0_8 mipi_csi2_tx_ctrl_v1_0_4 = E:/xilinx_libs/mipi_csi2_tx_ctrl_v1_0_4 mipi_dphy_v4_3_4 = E:/xilinx_libs/mipi_dphy_v4_3_4 mipi_dsi_tx_ctrl_v1_0_7 = E:/xilinx_libs/mipi_dsi_tx_ctrl_v1_0_7 mpegtsmux_v1_1_4 = E:/xilinx_libs/mpegtsmux_v1_1_4 mrmac_v1_6_0 = E:/xilinx_libs/mrmac_v1_6_0 multi_channel_25g_rs_fec_v1_0_18 = E:/xilinx_libs/multi_channel_25g_rs_fec_v1_0_18 mutex_v2_1_11 = E:/xilinx_libs/mutex_v2_1_11 axi_tg_lib = E:/xilinx_libs/axi_tg_lib noc_hbm_v1_0_0 = E:/xilinx_libs/noc_hbm_v1_0_0 noc_ncrb_v1_0_0 = E:/xilinx_libs/noc_ncrb_v1_0_0 noc_nidb_v1_0_0 = E:/xilinx_libs/noc_nidb_v1_0_0 noc_nmu_phydir_v1_0_0 = E:/xilinx_libs/noc_nmu_phydir_v1_0_0 noc_npp_rptr_v1_0_0 = E:/xilinx_libs/noc_npp_rptr_v1_0_0 noc_nps4_v1_0_0 = E:/xilinx_libs/noc_nps4_v1_0_0 noc_nps6_v1_0_0 = E:/xilinx_libs/noc_nps6_v1_0_0 noc_nps_v1_0_0 = E:/xilinx_libs/noc_nps_v1_0_0 noc_nsu_v1_0_0 = E:/xilinx_libs/noc_nsu_v1_0_0 nvmeha_v1_0_7 = E:/xilinx_libs/nvmeha_v1_0_7 nvme_tc_v3_0_1 = E:/xilinx_libs/nvme_tc_v3_0_1 oddr_v1_0_2 = E:/xilinx_libs/oddr_v1_0_2 oran_radio_if_v2_2_0 = E:/xilinx_libs/oran_radio_if_v2_2_0 pci32_v5_0_12 = E:/xilinx_libs/pci32_v5_0_12 pci64_v5_0_11 = E:/xilinx_libs/pci64_v5_0_11 pcie_axi4lite_tap_v1_0_1 = E:/xilinx_libs/pcie_axi4lite_tap_v1_0_1 pcie_dma_versal_v2_0_11 = E:/xilinx_libs/pcie_dma_versal_v2_0_11 pcie_jtag_v1_0_0 = E:/xilinx_libs/pcie_jtag_v1_0_0 pcie_qdma_mailbox_v1_0_0 = E:/xilinx_libs/pcie_qdma_mailbox_v1_0_0 pc_cfr_v6_4_2 = E:/xilinx_libs/pc_cfr_v6_4_2 pc_cfr_v7_0_1 = E:/xilinx_libs/pc_cfr_v7_0_1 pc_cfr_v7_1_0 = E:/xilinx_libs/pc_cfr_v7_1_0 picxo = E:/xilinx_libs/picxo ptp_1588_timer_syncer_v1_0_2 = E:/xilinx_libs/ptp_1588_timer_syncer_v1_0_2 ptp_1588_timer_syncer_v2_0_3 = E:/xilinx_libs/ptp_1588_timer_syncer_v2_0_3 qdma_v4_0_13 = E:/xilinx_libs/qdma_v4_0_13 qdriv_pl_v1_0_7 = E:/xilinx_libs/qdriv_pl_v1_0_7 rama_v1_1_12_lib = E:/xilinx_libs/rama_v1_1_12_lib rld3_pl_phy_v1_0_0 = E:/xilinx_libs/rld3_pl_phy_v1_0_0 rld3_pl_v1_0_9 = E:/xilinx_libs/rld3_pl_v1_0_9 roe_framer_v3_0_3 = E:/xilinx_libs/roe_framer_v3_0_3 rst_vip_v1_0_4 = E:/xilinx_libs/rst_vip_v1_0_4 smartconnect_v1_0 = E:/xilinx_libs/smartconnect_v1_0 sem_ultra_v3_1_23 = E:/xilinx_libs/sem_ultra_v3_1_23 sem_v4_1_13 = E:/xilinx_libs/sem_v4_1_13 shell_utils_msp432_bsl_crc_gen_v1_0_0 = E:/xilinx_libs/shell_utils_msp432_bsl_crc_gen_v1_0_0 sim_clk_gen_v1_0_3 = E:/xilinx_libs/sim_clk_gen_v1_0_3 sim_rst_gen_v1_0_2 = E:/xilinx_libs/sim_rst_gen_v1_0_2 sim_trig_v1_0_7 = E:/xilinx_libs/sim_trig_v1_0_7 stm_v1_0 = E:/xilinx_libs/stm_v1_0 stm_v1_0_0 = E:/xilinx_libs/stm_v1_0_0 system_cache_v5_0_8 = E:/xilinx_libs/system_cache_v5_0_8 ta_dma_v1_0_10 = E:/xilinx_libs/ta_dma_v1_0_10 tcc_decoder_3gpplte_v3_0_6 = E:/xilinx_libs/tcc_decoder_3gpplte_v3_0_6 ten_gig_eth_mac_v15_1_10 = E:/xilinx_libs/ten_gig_eth_mac_v15_1_10 ten_gig_eth_pcs_pma_v6_0_22 = E:/xilinx_libs/ten_gig_eth_pcs_pma_v6_0_22 timer_sync_1588_v1_2_4 = E:/xilinx_libs/timer_sync_1588_v1_2_4 tmr_inject_v1_0_4 = E:/xilinx_libs/tmr_inject_v1_0_4 tmr_manager_v1_0_10 = E:/xilinx_libs/tmr_manager_v1_0_10 tmr_voter_v1_0_4 = E:/xilinx_libs/tmr_voter_v1_0_4 trace_s2mm_v1_2_0 = E:/xilinx_libs/trace_s2mm_v1_2_0 tsn_endpoint_ethernet_mac_block_v1_0_11 = E:/xilinx_libs/tsn_endpoint_ethernet_mac_block_v1_0_11 uhdsdi_gt_v2_0_8 = E:/xilinx_libs/uhdsdi_gt_v2_0_8 uram_rd_back_v1_0_2 = E:/xilinx_libs/uram_rd_back_v1_0_2 usxgmii_v1_2_7 = E:/xilinx_libs/usxgmii_v1_2_7 util_ff_v1_0_0 = E:/xilinx_libs/util_ff_v1_0_0 util_idelay_ctrl_v1_0_2 = E:/xilinx_libs/util_idelay_ctrl_v1_0_2 util_reduced_logic_v2_0_4 = E:/xilinx_libs/util_reduced_logic_v2_0_4 util_vector_logic_v2_0_2 = E:/xilinx_libs/util_vector_logic_v2_0_2 versal_cips_v3_2_1 = E:/xilinx_libs/versal_cips_v3_2_1 vfb_v1_0_20 = E:/xilinx_libs/vfb_v1_0_20 video_frame_crc_v1_0_4 = E:/xilinx_libs/video_frame_crc_v1_0_4 vid_edid_v1_0_0 = E:/xilinx_libs/vid_edid_v1_0_0 vid_phy_controller_v2_1_13 = E:/xilinx_libs/vid_phy_controller_v2_1_13 vid_phy_controller_v2_2_13 = E:/xilinx_libs/vid_phy_controller_v2_2_13 vitis_deadlock_detector_v1_0_1 = E:/xilinx_libs/vitis_deadlock_detector_v1_0_1 v_axi4s_remap_v1_0_19 = E:/xilinx_libs/v_axi4s_remap_v1_0_19 v_axi4s_remap_v1_1_5 = E:/xilinx_libs/v_axi4s_remap_v1_1_5 v_csc_v1_1_5 = E:/xilinx_libs/v_csc_v1_1_5 v_deinterlacer_v5_1_0 = E:/xilinx_libs/v_deinterlacer_v5_1_0 v_demosaic_v1_1_5 = E:/xilinx_libs/v_demosaic_v1_1_5 v_frmbuf_rd_v2_2_5 = E:/xilinx_libs/v_frmbuf_rd_v2_2_5 v_frmbuf_wr_v2_2_5 = E:/xilinx_libs/v_frmbuf_wr_v2_2_5 v_gamma_lut_v1_1_5 = E:/xilinx_libs/v_gamma_lut_v1_1_5 v_hcresampler_v1_1_5 = E:/xilinx_libs/v_hcresampler_v1_1_5 v_hdmi_phy1_v1_0_6 = E:/xilinx_libs/v_hdmi_phy1_v1_0_6 v_hdmi_rx_v3_0_0 = E:/xilinx_libs/v_hdmi_rx_v3_0_0 v_hdmi_tx_v3_0_0 = E:/xilinx_libs/v_hdmi_tx_v3_0_0 v_hscaler_v1_1_5 = E:/xilinx_libs/v_hscaler_v1_1_5 v_letterbox_v1_1_5 = E:/xilinx_libs/v_letterbox_v1_1_5 v_mix_v5_1_5 = E:/xilinx_libs/v_mix_v5_1_5 v_scenechange_v1_1_4 = E:/xilinx_libs/v_scenechange_v1_1_4 v_sdi_rx_vid_bridge_v2_0_0 = E:/xilinx_libs/v_sdi_rx_vid_bridge_v2_0_0 v_smpte_sdi_v3_0_9 = E:/xilinx_libs/v_smpte_sdi_v3_0_9 v_smpte_uhdsdi_rx_v1_0_1 = E:/xilinx_libs/v_smpte_uhdsdi_rx_v1_0_1 v_smpte_uhdsdi_tx_v1_0_1 = E:/xilinx_libs/v_smpte_uhdsdi_tx_v1_0_1 v_smpte_uhdsdi_v1_0_9 = E:/xilinx_libs/v_smpte_uhdsdi_v1_0_9 v_tpg_v8_0_9 = E:/xilinx_libs/v_tpg_v8_0_9 v_tpg_v8_1_5 = E:/xilinx_libs/v_tpg_v8_1_5 v_tpg_v8_2_1 = E:/xilinx_libs/v_tpg_v8_2_1 v_uhdsdi_audio_v2_0_6 = E:/xilinx_libs/v_uhdsdi_audio_v2_0_6 v_uhdsdi_vidgen_v1_0_1 = E:/xilinx_libs/v_uhdsdi_vidgen_v1_0_1 v_vcresampler_v1_1_5 = E:/xilinx_libs/v_vcresampler_v1_1_5 v_vid_in_axi4s_v4_0_9 = E:/xilinx_libs/v_vid_in_axi4s_v4_0_9 v_vid_in_axi4s_v5_0_1 = E:/xilinx_libs/v_vid_in_axi4s_v5_0_1 v_vscaler_v1_1_5 = E:/xilinx_libs/v_vscaler_v1_1_5 v_warp_filter_v1_0_2 = E:/xilinx_libs/v_warp_filter_v1_0_2 v_warp_init_v1_0_2 = E:/xilinx_libs/v_warp_init_v1_0_2 xbip_dsp48_wrapper_v3_0_4 = E:/xilinx_libs/xbip_dsp48_wrapper_v3_0_4 xbip_utils_v3_0_10 = E:/xilinx_libs/xbip_utils_v3_0_10 xdfe_nlf_v1_0_1 = E:/xilinx_libs/xdfe_nlf_v1_0_1 xdfe_resampler_v1_0_4 = E:/xilinx_libs/xdfe_resampler_v1_0_4 xdma_v4_1_19 = E:/xilinx_libs/xdma_v4_1_19 xlconcat_v2_1_4 = E:/xilinx_libs/xlconcat_v2_1_4 xlconstant_v1_1_7 = E:/xilinx_libs/xlconstant_v1_1_7 xlslice_v1_0_2 = E:/xilinx_libs/xlslice_v1_0_2 xpm_cdc_gen_v1_0_1 = E:/xilinx_libs/xpm_cdc_gen_v1_0_1 xsdbm_v3_0_0 = E:/xilinx_libs/xsdbm_v3_0_0 xxv_ethernet_v4_1_0 = E:/xilinx_libs/xxv_ethernet_v4_1_0 aurora_8b10b_versal_v1_0_1 = E:/xilinx_libs/aurora_8b10b_versal_v1_0_1 axi_c2c_v1_0_3 = E:/xilinx_libs/axi_c2c_v1_0_3 lib_srl_fifo_v1_0_2 = E:/xilinx_libs/lib_srl_fifo_v1_0_2 lib_fifo_v1_0_16 = E:/xilinx_libs/lib_fifo_v1_0_16 axi_datamover_v5_1_28 = E:/xilinx_libs/axi_datamover_v5_1_28 amm_axi_bridge_v1_0_12 = E:/xilinx_libs/amm_axi_bridge_v1_0_12 axis_register_slice_v1_1_26 = E:/xilinx_libs/axis_register_slice_v1_1_26 axis_switch_v1_1_26 = E:/xilinx_libs/axis_switch_v1_1_26 axis_clock_converter_v1_1_27 = E:/xilinx_libs/axis_clock_converter_v1_1_27 axis_data_fifo_v2_0_8 = E:/xilinx_libs/axis_data_fifo_v2_0_8 ats_switch_v1_0_5 = E:/xilinx_libs/ats_switch_v1_0_5 audio_formatter_v1_0_8 = E:/xilinx_libs/audio_formatter_v1_0_8 axi4stream_vip_v1_1_12 = E:/xilinx_libs/axi4stream_vip_v1_1_12 v_tc_v6_2_4 = E:/xilinx_libs/v_tc_v6_2_4 v_dp_axi4s_vid_out_v1_0_4 = E:/xilinx_libs/v_dp_axi4s_vid_out_v1_0_4 v_tc_v6_1_13 = E:/xilinx_libs/v_tc_v6_1_13 v_axi4s_vid_out_v4_0_14 = E:/xilinx_libs/v_axi4s_vid_out_v4_0_14 axi4svideo_bridge_v1_0_14 = E:/xilinx_libs/axi4svideo_bridge_v1_0_14 axis_accelerator_adapter_v2_1_16 = E:/xilinx_libs/axis_accelerator_adapter_v2_1_16 axis_broadcaster_v1_1_25 = E:/xilinx_libs/axis_broadcaster_v1_1_25 axis_combiner_v1_1_24 = E:/xilinx_libs/axis_combiner_v1_1_24 axis_data_fifo_v1_1_27 = E:/xilinx_libs/axis_data_fifo_v1_1_27 axis_dwidth_converter_v1_1_25 = E:/xilinx_libs/axis_dwidth_converter_v1_1_25 axis_ila_intf_v1_0_0 = E:/xilinx_libs/axis_ila_intf_v1_0_0 axis_interconnect_v1_1_20 = E:/xilinx_libs/axis_interconnect_v1_1_20 axis_subset_converter_v1_1_26 = E:/xilinx_libs/axis_subset_converter_v1_1_26 axis_vio_v1_0_6 = E:/xilinx_libs/axis_vio_v1_0_6 axi_apb_bridge_v3_0_17 = E:/xilinx_libs/axi_apb_bridge_v3_0_17 axi_bram_ctrl_v4_0_14 = E:/xilinx_libs/axi_bram_ctrl_v4_0_14 axi_sg_v4_1_15 = E:/xilinx_libs/axi_sg_v4_1_15 axi_cdma_v4_1_26 = E:/xilinx_libs/axi_cdma_v4_1_26 axi_clock_converter_v2_1_25 = E:/xilinx_libs/axi_clock_converter_v2_1_25 axi_data_fifo_v2_1_25 = E:/xilinx_libs/axi_data_fifo_v2_1_25 axi_register_slice_v2_1_26 = E:/xilinx_libs/axi_register_slice_v2_1_26 axi_crossbar_v2_1_27 = E:/xilinx_libs/axi_crossbar_v2_1_27 axi_dma_v7_1_27 = E:/xilinx_libs/axi_dma_v7_1_27 axi_protocol_converter_v2_1_26 = E:/xilinx_libs/axi_protocol_converter_v2_1_26 axi_dwidth_converter_v2_1_26 = E:/xilinx_libs/axi_dwidth_converter_v2_1_26 axi_emc_v3_0_26 = E:/xilinx_libs/axi_emc_v3_0_26 axi_epc_v2_0_29 = E:/xilinx_libs/axi_epc_v2_0_29 lib_bmg_v1_0_14 = E:/xilinx_libs/lib_bmg_v1_0_14 axi_ethernetlite_v3_0_25 = E:/xilinx_libs/axi_ethernetlite_v3_0_25 axi_ethernet_buffer_v2_0_24 = E:/xilinx_libs/axi_ethernet_buffer_v2_0_24 axi_fifo_mm_s_v4_2_8 = E:/xilinx_libs/axi_fifo_mm_s_v4_2_8 axi_firewall_v1_1_5 = E:/xilinx_libs/axi_firewall_v1_1_5 axi_firewall_v1_2_1 = E:/xilinx_libs/axi_firewall_v1_2_1 interrupt_control_v3_1_4 = E:/xilinx_libs/interrupt_control_v3_1_4 axi_gpio_v2_0_28 = E:/xilinx_libs/axi_gpio_v2_0_28 axi_hbicap_v1_0_4 = E:/xilinx_libs/axi_hbicap_v1_0_4 axi_hwicap_v3_0_30 = E:/xilinx_libs/axi_hwicap_v3_0_30 axi_iic_v2_1_2 = E:/xilinx_libs/axi_iic_v2_1_2 axi_intc_v4_1_17 = E:/xilinx_libs/axi_intc_v4_1_17 axi_interconnect_v1_7_20 = E:/xilinx_libs/axi_interconnect_v1_7_20 axi_master_burst_v2_0_7 = E:/xilinx_libs/axi_master_burst_v2_0_7 axi_msg_v1_0_8 = E:/xilinx_libs/axi_msg_v1_0_8 axi_mcdma_v1_1_7 = E:/xilinx_libs/axi_mcdma_v1_1_7 axi_memory_init_v1_0_7 = E:/xilinx_libs/axi_memory_init_v1_0_7 axi_mm2s_mapper_v1_1_25 = E:/xilinx_libs/axi_mm2s_mapper_v1_1_25 axi_mmu_v2_1_24 = E:/xilinx_libs/axi_mmu_v2_1_24 axi_pcie_v2_9_7 = E:/xilinx_libs/axi_pcie_v2_9_7 axi_protocol_checker_v2_0_12 = E:/xilinx_libs/axi_protocol_checker_v2_0_12 axi_quad_spi_v3_2_25 = E:/xilinx_libs/axi_quad_spi_v3_2_25 axi_sideband_util_v1_0_10 = E:/xilinx_libs/axi_sideband_util_v1_0_10 axi_tft_v2_0_25 = E:/xilinx_libs/axi_tft_v2_0_25 axi_timebase_wdt_v3_0_18 = E:/xilinx_libs/axi_timebase_wdt_v3_0_18 axi_timer_v2_0_28 = E:/xilinx_libs/axi_timer_v2_0_28 axi_traffic_gen_v3_0_12 = E:/xilinx_libs/axi_traffic_gen_v3_0_12 axi_uart16550_v2_0_28 = E:/xilinx_libs/axi_uart16550_v2_0_28 axi_uartlite_v2_0_30 = E:/xilinx_libs/axi_uartlite_v2_0_30 axi_usb2_device_v5_0_27 = E:/xilinx_libs/axi_usb2_device_v5_0_27 axi_utils_v2_0_6 = E:/xilinx_libs/axi_utils_v2_0_6 axi_vdma_v6_3_14 = E:/xilinx_libs/axi_vdma_v6_3_14 xbip_pipe_v3_0_6 = E:/xilinx_libs/xbip_pipe_v3_0_6 xbip_dsp48_addsub_v3_0_6 = E:/xilinx_libs/xbip_dsp48_addsub_v3_0_6 xbip_addsub_v3_0_6 = E:/xilinx_libs/xbip_addsub_v3_0_6 c_reg_fd_v12_0_6 = E:/xilinx_libs/c_reg_fd_v12_0_6 c_addsub_v12_0_14 = E:/xilinx_libs/c_addsub_v12_0_14 axi_vfifo_ctrl_v2_0_28 = E:/xilinx_libs/axi_vfifo_ctrl_v2_0_28 axi_vip_v1_1_12 = E:/xilinx_libs/axi_vip_v1_1_12 bs_switch_v1_0_0 = E:/xilinx_libs/bs_switch_v1_0_0 canfd_v3_0_5 = E:/xilinx_libs/canfd_v3_0_5 can_v5_0_29 = E:/xilinx_libs/can_v5_0_29 cic_compiler_v4_0_16 = E:/xilinx_libs/cic_compiler_v4_0_16 xbip_bram18k_v3_0_6 = E:/xilinx_libs/xbip_bram18k_v3_0_6 mult_gen_v12_0_18 = E:/xilinx_libs/mult_gen_v12_0_18 cmpy_v6_0_21 = E:/xilinx_libs/cmpy_v6_0_21 c_mux_bit_v12_0_6 = E:/xilinx_libs/c_mux_bit_v12_0_6 c_shift_ram_v12_0_14 = E:/xilinx_libs/c_shift_ram_v12_0_14 c_mux_bus_v12_0_6 = E:/xilinx_libs/c_mux_bus_v12_0_6 c_gate_bit_v12_0_6 = E:/xilinx_libs/c_gate_bit_v12_0_6 xbip_counter_v3_0_6 = E:/xilinx_libs/xbip_counter_v3_0_6 c_counter_binary_v12_0_15 = E:/xilinx_libs/c_counter_binary_v12_0_15 c_compare_v12_0_6 = E:/xilinx_libs/c_compare_v12_0_6 convolution_v9_0_16 = E:/xilinx_libs/convolution_v9_0_16 cordic_v6_0_18 = E:/xilinx_libs/cordic_v6_0_18 cpri_v8_11_12 = E:/xilinx_libs/cpri_v8_11_12 xbip_dsp48_acc_v3_0_6 = E:/xilinx_libs/xbip_dsp48_acc_v3_0_6 xbip_accum_v3_0_6 = E:/xilinx_libs/xbip_accum_v3_0_6 c_accum_v12_0_14 = E:/xilinx_libs/c_accum_v12_0_14 dbg_intf = E:/xilinx_libs/dbg_intf xbip_dsp48_multadd_v3_0_6 = E:/xilinx_libs/xbip_dsp48_multadd_v3_0_6 dds_compiler_v6_0_22 = E:/xilinx_libs/dds_compiler_v6_0_22 dft_v4_0_16 = E:/xilinx_libs/dft_v4_0_16 dft_v4_2_3 = E:/xilinx_libs/dft_v4_2_3 dfx_axi_shutdown_manager_v1_0_0 = E:/xilinx_libs/dfx_axi_shutdown_manager_v1_0_0 dfx_bitstream_monitor_v1_0_1 = E:/xilinx_libs/dfx_bitstream_monitor_v1_0_1 dfx_controller_v1_0_3 = E:/xilinx_libs/dfx_controller_v1_0_3 dfx_decoupler_v1_0_4 = E:/xilinx_libs/dfx_decoupler_v1_0_4 displayport_v7_0_0 = E:/xilinx_libs/displayport_v7_0_0 displayport_v9_0_5 = E:/xilinx_libs/displayport_v9_0_5 xbip_dsp48_mult_v3_0_6 = E:/xilinx_libs/xbip_dsp48_mult_v3_0_6 floating_point_v7_0_20 = E:/xilinx_libs/floating_point_v7_0_20 div_gen_v5_1_19 = E:/xilinx_libs/div_gen_v5_1_19 dsp_macro_v1_0_2 = E:/xilinx_libs/dsp_macro_v1_0_2 ernic_v3_1_2 = E:/xilinx_libs/ernic_v3_1_2 etrnic_v1_1_5 = E:/xilinx_libs/etrnic_v1_1_5 fc32_rs_fec_v1_0_21 = E:/xilinx_libs/fc32_rs_fec_v1_0_21 fec_5g_common_v1_1_1 = E:/xilinx_libs/fec_5g_common_v1_1_1 fir_compiler_v5_2_6 = E:/xilinx_libs/fir_compiler_v5_2_6 fir_compiler_v7_2_18 = E:/xilinx_libs/fir_compiler_v7_2_18 flexo_100g_rs_fec_v1_0_22 = E:/xilinx_libs/flexo_100g_rs_fec_v1_0_22 floating_point_v7_1_14 = E:/xilinx_libs/floating_point_v7_1_14 g709_rs_encoder_v2_2_8 = E:/xilinx_libs/g709_rs_encoder_v2_2_8 rs_toolbox_v9_0_9 = E:/xilinx_libs/rs_toolbox_v9_0_9 g709_rs_decoder_v2_2_10 = E:/xilinx_libs/g709_rs_decoder_v2_2_10 g709_fec_v2_4_5 = E:/xilinx_libs/g709_fec_v2_4_5 g975_efec_i4_v1_0_18 = E:/xilinx_libs/g975_efec_i4_v1_0_18 g975_efec_i7_v2_0_18 = E:/xilinx_libs/g975_efec_i7_v2_0_18 hw_trace = E:/xilinx_libs/hw_trace icap_arb_v1_0_1 = E:/xilinx_libs/icap_arb_v1_0_1 ieee802d3_200g_rs_fec_v2_0_5 = E:/xilinx_libs/ieee802d3_200g_rs_fec_v2_0_5 ieee802d3_25g_rs_fec_v1_0_23 = E:/xilinx_libs/ieee802d3_25g_rs_fec_v1_0_23 ieee802d3_400g_rs_fec_v2_0_8 = E:/xilinx_libs/ieee802d3_400g_rs_fec_v2_0_8 ieee802d3_50g_rs_fec_v1_0_19 = E:/xilinx_libs/ieee802d3_50g_rs_fec_v1_0_19 ieee802d3_50g_rs_fec_v2_0_11 = E:/xilinx_libs/ieee802d3_50g_rs_fec_v2_0_11 ieee802d3_rs_fec_v2_0_15 = E:/xilinx_libs/ieee802d3_rs_fec_v2_0_15 ldpc_v2_0_10 = E:/xilinx_libs/ldpc_v2_0_10 xfft_v7_2_13 = E:/xilinx_libs/xfft_v7_2_13 lte_fft_v2_0_22 = E:/xilinx_libs/lte_fft_v2_0_22 xfft_v9_1_8 = E:/xilinx_libs/xfft_v9_1_8 lte_fft_v2_1_6 = E:/xilinx_libs/lte_fft_v2_1_6 mailbox_v2_1_15 = E:/xilinx_libs/mailbox_v2_1_15 mdm_v3_2_23 = E:/xilinx_libs/mdm_v3_2_23 mem_tg_v1_0_8 = E:/xilinx_libs/mem_tg_v1_0_8 iomodule_v3_0 = E:/xilinx_libs/iomodule_v3_0 lmb_bram_if_cntlr_v4_0 = E:/xilinx_libs/lmb_bram_if_cntlr_v4_0 lmb_v10_v3_0 = E:/xilinx_libs/lmb_v10_v3_0 axi_lite_ipif_v3_0 = E:/xilinx_libs/axi_lite_ipif_v3_0 mdm_v3_2 = E:/xilinx_libs/mdm_v3_2 microblaze_mcs_v2_3_6 = E:/xilinx_libs/microblaze_mcs_v2_3_6 perf_axi_tg_v1_0_8 = E:/xilinx_libs/perf_axi_tg_v1_0_8 polar_v1_0_10 = E:/xilinx_libs/polar_v1_0_10 polar_v1_1_0 = E:/xilinx_libs/polar_v1_1_0 processing_system7_vip_v1_0_14 = E:/xilinx_libs/processing_system7_vip_v1_0_14 proc_sys_reset_v5_0_13 = E:/xilinx_libs/proc_sys_reset_v5_0_13 pr_decoupler_v1_0_10 = E:/xilinx_libs/pr_decoupler_v1_0_10 qdriv_pl_phy_v1_0_0 = E:/xilinx_libs/qdriv_pl_phy_v1_0_0 quadsgmii_v3_5_8 = E:/xilinx_libs/quadsgmii_v3_5_8 rs_decoder_v9_0_18 = E:/xilinx_libs/rs_decoder_v9_0_18 rs_encoder_v9_0_17 = E:/xilinx_libs/rs_encoder_v9_0_17 sd_fec_v1_1_9 = E:/xilinx_libs/sd_fec_v1_1_9 shell_utils_addr_remap_v1_0_5 = E:/xilinx_libs/shell_utils_addr_remap_v1_0_5 sid_v8_0_17 = E:/xilinx_libs/sid_v8_0_17 soft_ecc_proxy_v1_0_1 = E:/xilinx_libs/soft_ecc_proxy_v1_0_1 spdif_v2_0_26 = E:/xilinx_libs/spdif_v2_0_26 srio_gen2_v4_1_14 = E:/xilinx_libs/srio_gen2_v4_1_14 switch_core_top_v1_0_11 = E:/xilinx_libs/switch_core_top_v1_0_11 tcc_decoder_3gppmm_v2_0_23 = E:/xilinx_libs/tcc_decoder_3gppmm_v2_0_23 tcc_encoder_3gpplte_v4_0_16 = E:/xilinx_libs/tcc_encoder_3gpplte_v4_0_16 tcc_encoder_3gpp_v5_0_18 = E:/xilinx_libs/tcc_encoder_3gpp_v5_0_18 tmr_comparator_v1_0_5 = E:/xilinx_libs/tmr_comparator_v1_0_5 tmr_sem_v1_0_22 = E:/xilinx_libs/tmr_sem_v1_0_22 tri_mode_ethernet_mac_v9_0_22 = E:/xilinx_libs/tri_mode_ethernet_mac_v9_0_22 tsn_temac_v1_0_7 = E:/xilinx_libs/tsn_temac_v1_0_7 vby1hs_v1_0_2 = E:/xilinx_libs/vby1hs_v1_0_2 versal_cips_ps_vip_v1_0_4 = E:/xilinx_libs/versal_cips_ps_vip_v1_0_4 videoaxi4s_bridge_v1_0_5 = E:/xilinx_libs/videoaxi4s_bridge_v1_0_5 viterbi_v9_1_13 = E:/xilinx_libs/viterbi_v9_1_13 vitis_net_p4_v1_1_0 = E:/xilinx_libs/vitis_net_p4_v1_1_0 v_dual_splitter_v1_0_9 = E:/xilinx_libs/v_dual_splitter_v1_0_9 v_frmbuf_rd_v2_3_1 = E:/xilinx_libs/v_frmbuf_rd_v2_3_1 v_frmbuf_rd_v2_4_0 = E:/xilinx_libs/v_frmbuf_rd_v2_4_0 v_frmbuf_wr_v2_3_1 = E:/xilinx_libs/v_frmbuf_wr_v2_3_1 v_frmbuf_wr_v2_4_0 = E:/xilinx_libs/v_frmbuf_wr_v2_4_0 v_hdmi_rx1_v1_0_3 = E:/xilinx_libs/v_hdmi_rx1_v1_0_3 v_hdmi_tx1_v1_0_3 = E:/xilinx_libs/v_hdmi_tx1_v1_0_3 v_mix_v5_2_3 = E:/xilinx_libs/v_mix_v5_2_3 v_multi_scaler_v1_2_3 = E:/xilinx_libs/v_multi_scaler_v1_2_3 v_vid_gt_bridge_v1_0_5 = E:/xilinx_libs/v_vid_gt_bridge_v1_0_5 v_vid_sdi_tx_bridge_v2_0_0 = E:/xilinx_libs/v_vid_sdi_tx_bridge_v2_0_0 v_warp_filter_v1_1_0 = E:/xilinx_libs/v_warp_filter_v1_1_0 v_warp_init_v1_1_0 = E:/xilinx_libs/v_warp_init_v1_1_0 xbip_dsp48_multacc_v3_0_6 = E:/xilinx_libs/xbip_dsp48_multacc_v3_0_6 xbip_multadd_v3_0_17 = E:/xilinx_libs/xbip_multadd_v3_0_17 xdfe_common_v1_0_0 = E:/xilinx_libs/xdfe_common_v1_0_0 xdfe_cc_filter_v1_0_4 = E:/xilinx_libs/xdfe_cc_filter_v1_0_4 xdfe_cc_mixer_v1_0_4 = E:/xilinx_libs/xdfe_cc_mixer_v1_0_4 xdfe_equalizer_v1_0_4 = E:/xilinx_libs/xdfe_equalizer_v1_0_4 xdfe_fft_v1_0_4 = E:/xilinx_libs/xdfe_fft_v1_0_4 xdfe_nr_prach_v1_0_4 = E:/xilinx_libs/xdfe_nr_prach_v1_0_4 xsdbs_v1_0_2 = E:/xilinx_libs/xsdbs_v1_0_2 zynq_ultra_ps_e_vip_v1_0_12 = E:/xilinx_libs/zynq_ultra_ps_e_vip_v1_0_12 [vcom] ; VHDL93 variable selects language version as the default. ; Default is VHDL-2002. ; Value of 0 or 1987 for VHDL-1987. ; Value of 1 or 1993 for VHDL-1993. ; Default or value of 2 or 2002 for VHDL-2002. ; Default or value of 3 or 2008 for VHDL-2008. VHDL93 = 2002 ; Show source line containing error. Default is off. ; Show_source = 1 ; Turn off unbound-component warnings. Default is on. ; Show_Warning1 = 0 ; Turn off process-without-a-wait-statement warnings. Default is on. ; Show_Warning2 = 0 ; Turn off null-range warnings. Default is on. ; Show_Warning3 = 0 ; Turn off no-space-in-time-literal warnings. Default is on. ; Show_Warning4 = 0 ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. ; Show_Warning5 = 0 ; Turn off optimization for IEEE std_logic_1164 package. Default is on. ; Optimize_1164 = 0 ; Turn on resolving of ambiguous function overloading in favor of the ; "explicit" function declaration (not the one automatically created by ; the compiler for each type declaration). Default is off. ; The .ini file has Explicit enabled so that std_logic_signed/unsigned ; will match the behavior of synthesis tools. Explicit = 1 ; Turn off acceleration of the VITAL packages. Default is to accelerate. ; NoVital = 1 ; Turn off VITAL compliance checking. Default is checking on. ; NoVitalCheck = 1 ; Ignore VITAL compliance checking errors. Default is to not ignore. ; IgnoreVitalErrors = 1 ; Turn off VITAL compliance checking warnings. Default is to show warnings. ; Show_VitalChecksWarnings = 0 ; Keep silent about case statement static warnings. ; Default is to give a warning. ; NoCaseStaticError = 1 ; Keep silent about warnings caused by aggregates that are not locally static. ; Default is to give a warning. ; NoOthersStaticError = 1 ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "Loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on some limited synthesis rule compliance checking. Checks only: ; -- signals used (read) by a process must be in the sensitivity list ; CheckSynthesis = 1 ; Activate optimizations on expressions that do not involve signals, ; waits, or function/procedure/task invocations. Default is off. ; ScalarOpts = 1 ; Require the user to specify a configuration for all bindings, ; and do not generate a compile time default binding for the ; component. This will result in an elaboration error of ; 'component not bound' if the user fails to do so. Avoids the rare ; issue of a false dependency upon the unused default binding. ; RequireConfigForAllDefaultBinding = 1 ; Inhibit range checking on subscripts of arrays. Range checking on ; scalars defined with subtypes is inhibited by default. ; NoIndexCheck = 1 ; Inhibit range checks on all (implicit and explicit) assignments to ; scalar objects defined with subtypes. ; NoRangeCheck = 1 [vlog] ; Turn off inclusion of debugging info within design units. ; Default is to include debugging info. ; NoDebug = 1 ; Turn off "loading..." messages. Default is messages on. ; Quiet = 1 ; Turn on Verilog hazard checking (order-dependent accessing of global vars). ; Default is off. ; Hazard = 1 ; Turn on converting regular Verilog identifiers to uppercase. Allows case ; insensitivity for module names. Default is no conversion. ; UpCase = 1 ; Turn on incremental compilation of modules. Default is off. ; Incremental = 1 ; Turns on lint-style checking. ; Show_Lint = 1 [vsim] ; Simulator resolution ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. Resolution = fs ; User time unit for run commands ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the ; unit specified for Resolution. For example, if Resolution is 100ps, ; then UserTimeUnit defaults to ps. ; Should generally be set to default. UserTimeUnit = default ; Default run length RunLength = 100 ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 ; Directive to license manager: ; vhdl Immediately reserve a VHDL license ; vlog Immediately reserve a Verilog license ; plus Immediately reserve a VHDL and Verilog license ; nomgc Do not look for Mentor Graphics Licenses ; nomti Do not look for Model Technology Licenses ; noqueue Do not wait in the license queue when a license isn't available ; viewsim Try for viewer license but accept simulator license(s) instead ; of queuing for viewer license ; License = plus ; Stop the simulator after a VHDL/Verilog assertion message ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal BreakOnAssertion = 3 ; Assertion Message Format ; %S - Severity Level ; %R - Report Message ; %T - Time of assertion ; %D - Delta ; %I - Instance or Region pathname (if available) ; %% - print '%' character ; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" ; Assertion File - alternate file for storing VHDL/Verilog assertion messages ; AssertFile = assert.log ; Default radix for all windows and commands... ; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned DefaultRadix = symbolic ; VSIM Startup command ; Startup = do startup.do ; File for saving command transcript TranscriptFile = transcript ; File for saving command history ; CommandHistory = cmdhist.log ; Specify whether paths in simulator commands should be described ; in VHDL or Verilog format. ; For VHDL, PathSeparator = / ; For Verilog, PathSeparator = . ; Must not be the same character as DatasetSeparator. PathSeparator = / ; Specify the dataset separator for fully rooted contexts. ; The default is ':'. For example, sim:/top ; Must not be the same character as PathSeparator. DatasetSeparator = : ; Disable VHDL assertion messages ; IgnoreNote = 1 ; IgnoreWarning = 1 ; IgnoreError = 1 ; IgnoreFailure = 1 ; Default force kind. May be freeze, drive, deposit, or default ; or in other terms, fixed, wired, or charged. ; A value of "default" will use the signal kind to determine the ; force kind, drive for resolved signals, freeze for unresolved signals ; DefaultForceKind = freeze ; If zero, open files when elaborated; otherwise, open files on ; first read or write. Default is 0. ; DelayFileOpen = 1 ; Control VHDL files opened for write. ; 0 = Buffered, 1 = Unbuffered UnbufferedOutput = 0 ; Control the number of VHDL files open concurrently. ; This number should always be less than the current ulimit ; setting for max file descriptors. ; 0 = unlimited ConcurrentFileLimit = 40 ; Control the number of hierarchical regions displayed as ; part of a signal name shown in the Wave window. ; A value of zero tells VSIM to display the full name. ; The default is 0. ; WaveSignalNameWidth = 0 ; Turn off warnings from the std_logic_arith, std_logic_unsigned ; and std_logic_signed packages. ; StdArithNoWarnings = 1 ; Turn off warnings from the IEEE numeric_std and numeric_bit packages. ; NumericStdNoWarnings = 1 ; Control the format of the (VHDL) FOR generate statement label ; for each iteration. Do not quote it. ; The format string here must contain the conversion codes %s and %d, ; in that order, and no other conversion codes. The %s represents ; the generate_label; the %d represents the generate parameter value ; at a particular generate iteration (this is the position number if ; the generate parameter is of an enumeration type). Embedded whitespace ; is allowed (but discouraged); leading and trailing whitespace is ignored. ; Application of the format must result in a unique scope name over all ; such names in the design so that name lookup can function properly. ; GenerateFormat = %s__%d ; Specify whether checkpoint files should be compressed. ; The default is 1 (compressed). ; CheckpointCompressMode = 0 ; List of dynamically loaded objects for Verilog PLI applications ; Veriuser = veriuser.sl ; Specify default options for the restart command. Options can be one ; or more of: -force -nobreakpoint -nolist -nolog -nowave ; DefaultRestartOptions = -force ; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs ; (> 500 megabyte memory footprint). Default is disabled. ; Specify number of megabytes to lock. ; LockedMemory = 1000 ; Turn on (1) or off (0) WLF file compression. ; The default is 1 (compress WLF file). ; WLFCompress = 0 ; Specify whether to save all design hierarchy (1) in the WLF file ; or only regions containing logged signals (0). ; The default is 0 (save only regions with logged signals). ; WLFSaveAllRegions = 1 ; WLF file time limit. Limit WLF file by time, as closely as possible, ; to the specified amount of simulation time. When the limit is exceeded ; the earliest times get truncated from the file. ; If both time and size limits are specified the most restrictive is used. ; UserTimeUnits are used if time units are not specified. ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} ; WLFTimeLimit = 0 ; WLF file size limit. Limit WLF file size, as closely as possible, ; to the specified number of megabytes. If both time and size limits ; are specified then the most restrictive is used. ; The default is 0 (no limit). ; WLFSizeLimit = 1000 ; Specify whether or not a WLF file should be deleted when the ; simulation ends. A value of 1 will cause the WLF file to be deleted. ; The default is 0 (do not delete WLF file when simulation ends). ; WLFDeleteOnQuit = 1 ; Automatic SDF compilation ; Disables automatic compilation of SDF files in flows that support it. ; Default is on, uncomment to turn off. ; NoAutoSDFCompile = 1 [lmc] [msg_system] ; Change a message severity or suppress a message. ; The format is: = [,...] ; Examples: ; note = 3009 ; warning = 3033 ; error = 3010,3016 ; fatal = 3016,3033 ; suppress = 3009,3016,3043 ; The command verror can be used to get the complete ; description of a message. ; Control transcripting of elaboration/runtime messages. ; The default is to have messages appear in the transcript and ; recorded in the wlf file (messages that are recorded in the ; wlf file can be viewed in the MsgViewer). The other settings ; are to send messages only to the transcript or only to the ; wlf file. The valid values are ; both {default} ; tran {transcript only} ; wlf {wlf file only} ; msgmode = both