xilinx.com xci unknown 1.0 clkpll_zcu false 100000000 false 100000000 false 100000000 false 100000000 100000000 0 0 0.0 1 LEVEL_HIGH 100000000 0 0 0.0 0 0 100000000 0 0 0.0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 0 MMCM cddcdone cddcreq 0000 0000 clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 33.330000000000005 100.0 0000 0000 100.00000 0000 0000 100.000 BUFG 50.0 false 100.00000 0.000 50.000 100.000 0.000 1 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 0000 0000 100.000 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 BUFG 50.000 false 100.000 0.000 50.000 100.000 0.000 1 0 VCO clk_in_sel clk_out1 clk_out2 clk_out3 clk_out4 clk_out5 clk_out6 clk_out7 CLK_VALID NA daddr dclk den din 0000 1 0.08333333333333333 0.08333333333333333 0.08333333333333333 0.08333333333333333 0.08333333333333333 0.08333333333333333 dout drdy dwe 93.000 1.000 0 0 0 0 0 0 0 0 FDBK_AUTO 0000 0000 0 Input Clock Freq (MHz) Input Jitter (UI) __primary_________300.000____________0.010 no_secondary_input_clock input_clk_stopped 0 Units_MHz No_Jitter locked 0000 0000 0000 false false false false false false false false OPTIMIZED 4.000 0.000 FALSE 3.333 10.0 12.000 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE 1 0.500 0.000 FALSE FALSE AUTO 1 None 0.010 0.010 FALSE 128.000 2.000 1 0 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) clk_out1__100.00000______0.000______50.0______101.475_____77.836 no_CLK_OUT2_output no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 0 0 128.000 1.000 LATENCY UNKNOWN false false false false false OPTIMIZED 1 0.000 1.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 No notes 0.010 power_down 0000 1 clk_in1 MMCM AUTO 300.000 0.010 10.000 Differential_clock_capable_pin psclk psdone psen psincdec 100.0 0 reset 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 4000 0.004 STATUS 11 32 100.0 100.0 100.0 100.0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 1600.000 800.000 clkpll_zcu MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 33.330000000000005 0.010 100.0 0.010 Buffer 101.475 false 77.836 50.000 100.000 0.000 1 true Buffer 0.0 false 0.0 50.000 100.000 0.000 1 false Buffer 0.0 false 0.0 50.000 100.000 0.000 1 false Buffer 0.0 false 0.0 50.000 100.000 0.000 1 false Buffer 0.0 false 0.0 50.000 100.000 0.000 1 false Buffer 0.0 false 0.0 50.000 100.000 0.000 1 false Buffer 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 user_si570_sysclk Custom clk_in_sel clk_out1 false clk_out2 false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto clkpll_zcu daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 4.000 0.000 false 3.333 10.0 12.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false AUTO 1 None 0.010 0.010 false 1 false false false LATENCY false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 clk_in1 MMCM mmcm_adv 300.000 0.010 10.000 Differential_clock_capable_pin psclk psdone psen psincdec 100.0 REL_PRIMARY reset reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false true false false false false false true false false false zynquplus xilinx.com:zcu102:part0:3.4 xczu9eg ffvb1156 VHDL VHDL -2 E TRUE TRUE IP_Flow 10 TRUE ../../../../nanoq_zcu.gen/sources_1/ip/clkpll_zcu . 2022.1 OUT_OF_CONTEXT