create_project zcu_pulse_channel ../../prj -force

set_property board_part xilinx.com:zcu102:part0:3.4 [current_project]

add_files {..\..\src\hdl\modules\qlaser_dacs_pulse_channel.vhdl}
add_files -fileset sim_1 {..\..\src\hdl\tb\tb_cpubus_dacs_pulse_channel_pd.vhdl}
add_files {..\..\src\hdl\pkg\qlaser_dac_dc_pkg.vhd}
add_files {..\..\src\hdl\pkg\qlaser_pkg.vhd}
add_files {..\..\src\hdl\pkg\iopakp.vhd}
add_files {..\..\src\hdl\pkg\iopakb.vhd}
read_ip {..\xilinx-zcu\bram_pulseposition\bram_pulseposition.xci}
read_ip {..\xilinx-zcu\bram_waveform\bram_waveform.xci}
read_ip {..\xilinx-zcu\fifo_data_to_stream\fifo_data_to_stream.xci}

# upgrade_ip [get_ips -filter {SCOPE !~ "*.bd"}]
generate_target all [get_ips -filter {SCOPE !~ "*.bd"}]

# Run the synthesis and generate the IP output products
launch_runs synth_1

# Wait for the synthesis to complete
wait_on_run synth_1

exit