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poly_rando
...
main
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*.log
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*.jou
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*.ini
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*.wlf
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*.vstf
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wlft*
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work
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transcript
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prj
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.Xil
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wave_values.txt
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*.ini
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@ -1,3 +0,0 @@
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{
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"digital-ide.dont-show-again.propose.issue": true
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}
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27
README.md
27
README.md
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@ -1,26 +1,3 @@
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# QLASER_PULSE_CHANNEL
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# QLASER_V_EYHC
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RAM tables for a single QLaser pulse channel. There are two tables, one defined the pulse shape and envelope, and another stores the waveform data.
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Do NOT "merge" any branches in this repository. The branches are used to keep track of the different versions of the project.
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## Build and Run
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First, make sure Vivado is in PATH. Then, run the following commands to build the project:
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```bash
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vivado -mode tcl -source tools/build_src/build.tcl
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```
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The build project will be in `prj` directory. If you modified the IP core, you need to close Vivado and run the above commands again.
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## Simulate in ModelSim
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Make sure you have ModelSim in PATH. Also make sure you already compiled the project and Xilinx libraries in Vivado. Make sure the `modelsim.ini` file is in `tools/sim` directory Then, run the following commands to simulate the project:
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```bash
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cd tools/sim
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modelsim -do run.do
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```
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#### Compile only (no simulation)
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```bash
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cd tools/sim
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vsim -c -quiet -do compile.do
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```
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## Do NOT "merge" any branches. Each branch is a separate thing!!!!
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@ -1,550 +0,0 @@
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---------------------------------------------------------------
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-- File : qlaser_dacs_pulse_channel.vhd
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-- Description : Single channel of pulse output
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----------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.qlaser_pkg.all;
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use work.qlaser_dacs_pulse_channel_pkg.all;
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entity qlaser_dacs_pulse_channel is
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port (
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reset : in std_logic;
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clk : in std_logic;
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enable : in std_logic; -- Set when DAC interface is running
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start : in std_logic; -- Set when pulse generation sequence begins (trigger)
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||||
cnt_time : in std_logic_vector(23 downto 0); -- Time since trigger.
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busy : out std_logic; -- Status signal
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||||
done_seq : in std_logic; -- Status signal to terminate sequence
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||||
-- TODO: Add another status signal to indicate any errors?
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||||
|
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-- CPU interface
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cpu_addr : in std_logic_vector(11 downto 0); -- Address input
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cpu_wdata : in std_logic_vector(31 downto 0); -- Data input
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cpu_wr : in std_logic; -- Write enable
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||||
cpu_sel : in std_logic; -- Block select
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||||
cpu_rdata : out std_logic_vector(31 downto 0); -- Data output
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||||
cpu_rdata_dv : out std_logic; -- Acknowledge output
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||||
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-- AXI-stream output
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||||
axis_tready : in std_logic; -- axi_stream ready from downstream module
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||||
axis_tdata : out std_logic_vector(15 downto 0); -- axi stream output data
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||||
axis_tvalid : out std_logic; -- axi_stream output data valid
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axis_tlast : out std_logic -- axi_stream output set on last data
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);
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end entity;
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||||
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---------------------------------------------------------------------------
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-- Single channel pulse generator with two RAMs
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---------------------------------------------------------------------------
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architecture channel of qlaser_dacs_pulse_channel is
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-- Signal declarations for pulse RAM
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signal ram_pulse_we : std_logic_vector( 0 downto 0); -- Write enable for pulse RAM
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signal ram_pulse_addra : std_logic_vector( 9 downto 0); -- Address for pulse RAM
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signal ram_pulse_dina : std_logic_vector(31 downto 0); -- Data for pulse RAM
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signal ram_pulse_douta : std_logic_vector(31 downto 0); -- Data out from pulse RAM
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signal ram_pulse_addrb : std_logic_vector( 9 downto 0); -- Address for pulse RAM
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signal ram_pulse_doutb : std_logic_vector(31 downto 0); -- Data out from pulse RAM
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-- Signal declarations for waveform RAM
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signal ram_waveform_wea : std_logic_vector( 0 downto 0); -- Write enable for waveform RAM
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signal ram_waveform_addra : std_logic_vector(10 downto 0); -- Address for waveform RAM
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signal ram_waveform_dina : std_logic_vector(31 downto 0); -- Data for waveform RAM
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signal ram_waveform_douta : std_logic_vector(31 downto 0); -- Data out from waveform RAM
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signal ram_waveform_addrb : std_logic_vector(19 downto 0); -- Address for waveform RAM
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signal ram_waveform_doutb : std_logic_vector(15 downto 0); -- Data out from waveform RAM
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-- State variable type declaration for main state machine
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type t_sm_state is (
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S_RESET, -- Wait for 'enable'. Stay here until JESD interface is up and running,
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S_IDLE, -- Wait for 'start'
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S_WAIT, -- Wait for cnt_time, external input, to match pulse position RAM output
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S_LOAD, -- Load the pulse channel RAM addresses and start the waveform output
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S_HOLD, -- Hold the last pulse definition address and output its data
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S_WAVE_UP, -- Output the rising edge of a waveform
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S_WAVE_FLAT,-- Output the flat top part of a waveform
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S_WAVE_DOWN -- Output the falling edge of a waveform
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);
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signal sm_state : t_sm_state;
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signal sm_wavedata : std_logic_vector(15 downto 0); -- Waveform RAM data
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signal sm_wavedata_dv : std_logic; -- Signal to indicate that waveform RAM data is valid
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signal sm_busy : std_logic; -- Signal to indicate that s.m. is not idle
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signal cnt_wave_len : unsigned(C_BITS_ADDR_LENGTH - 1 downto 0); -- Counter used for incremnet/decrement wave table addresses
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signal cnt_wave_top : unsigned(C_BITS_ADDR_TOP - 1 downto 0); -- Counter for the flat top of the waveform
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signal cnt_addr : unsigned(C_BITS_ADDR_START - 1 downto 0); -- Counter to keep track of address increments
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signal wave_last_addr : std_logic_vector(C_BITS_ADDR_FULL - 1 downto 0); -- Last address of the waveform table
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-- Misc signals
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signal cpu_rdata_dv_e1 : std_logic;
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signal cpu_rdata_dv_e2 : std_logic;
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signal cpu_rdata_ramsel_d1 : std_logic;
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signal cpu_rdata_ramsel_d2 : std_logic;
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signal pc : std_logic_vector(C_BITS_ADDR_PULSE - 1 downto 0); -- pulse counter, used to count the number of pulses generated
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----------------------------------------------------------------
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-- Assign values from the pulse definition ram to regfiles (?) with the following:
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-- 1. Start time 24 bits. [23:0]
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-- 2. Wave start addr 12 bit at [11:0]
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-- Wave length 10-bit at [25:16]
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-- 3. Scale factors 16, 16. [31:16] [15:0]
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-- 4. Flat-top 17-bit. [16:0]
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----------------------------------------------------------------
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signal reg_pulse_time : std_logic_vector(31 downto 0); -- first register which stores the pulse's start time
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signal reg_wave_start_addr : std_logic_vector(C_BITS_ADDR_START - 1 downto 0); -- the start address of the wavetable
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signal reg_wave_length : unsigned(C_BITS_ADDR_LENGTH - 1 downto 0); -- the length of the wavetable
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||||
signal reg_wave_end_addr : unsigned(C_BITS_ADDR_FULL - 1 downto 0); -- the end address of the wavetable
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signal reg_scale_gain : unsigned(C_BITS_TIME_FACTOR - 1 downto 0); -- scale factor for the gain, amplitude
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||||
signal reg_scale_time : unsigned(C_BITS_TIME_FACTOR - 1 downto 0); -- scale factor for the time, length
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||||
signal reg_pulse_flattop : unsigned(C_BITS_ADDR_TOP - 1 downto 0); -- fourth register which stores the pulse's flat top value
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||||
|
||||
-- Pipeline delays
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||||
signal sm_state_d1 : t_sm_state;
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||||
signal start_d1 : std_logic;
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||||
signal enable_d1 : std_logic;
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||||
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||||
-- error signal
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||||
signal err_addr_of : std_logic;
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||||
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||||
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||||
begin
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||||
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||||
----------------------------------------------------------------
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||||
-- Pulse Definition Block RAM.
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-- Synch write, Synch read
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||||
-- Port A is for CPU read/write. 1024x32-bit
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-- Port B is for pulse time data output. 1024x32-bit
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----------------------------------------------------------------
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u_ram_pulse : entity work.bram_pulse_definition
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port map(
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-- Port A CPU Bus
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clka => clk, -- input std_logic
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wea => ram_pulse_we, -- input slv( 0 to 0 )
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addra => ram_pulse_addra, -- input slv( 9 downto 0 )
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dina => ram_pulse_dina, -- input slv( 31 downto 0 )
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douta => ram_pulse_douta, -- output slv( 31 downto 0 ),
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-- Port B waveform input
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clkb => clk,
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web => (others=>'0'),
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addrb => ram_pulse_addrb, -- input slv( 9 downto 0 )
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dinb => (others=>'0'),
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doutb => ram_pulse_doutb -- output slv( 31 downto 0 )
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);
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----------------------------------------------------------------
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-- Waveform table Block RAM.
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-- Synch write, Synch read
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-- Port A is for CPU read/write. 2048x32-bit
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-- Port B is for waveform data. 4096x16-bit
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----------------------------------------------------------------
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u_ram_waveform : entity work.bram_waveform
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port map (
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-- Port A CPU Bus
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clka => clk , -- input std_logic
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wea => ram_waveform_wea , -- input slv(0 downto 0)
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addra => ram_waveform_addra , -- input slv(10 downto 0)
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dina => ram_waveform_dina , -- input slv(31 downto 0)
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douta => ram_waveform_douta , -- output slv(31 downto 0)
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||||
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-- Port B waveform output
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clkb => clk , -- input std_logic
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web => (others=>'0') , -- input slv(0 downto 0)
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addrb => ram_waveform_addrb(19 downto 8) , -- input slv(11 downto 0)
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dinb => (others=>'0') , -- input slv(15 downto 0)
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doutb => ram_waveform_doutb -- output slv(15 downto 0)
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);
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||||
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||||
----------------------------------------------------------------
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||||
-- CPU Read/Write RAM
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||||
-- MSB of cpu_addr is used to select one of the two RAMs
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-- to read/write, and the remainder are a 9-bit or 4-bit RAM address.
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||||
----------------------------------------------------------------
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||||
pr_ram_rw : process (reset, clk)
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begin
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if (reset = '1') then
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ram_pulse_addra <= (others=>'0');
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ram_pulse_dina <= (others=>'0');
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ram_pulse_we <= (others=>'0');
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ram_waveform_wea <= (others=>'0');
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||||
ram_waveform_addra <= (others=>'0');
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||||
ram_waveform_dina <= (others=>'0');
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||||
cpu_rdata <= (others=>'0');
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cpu_rdata_dv <= '0';
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cpu_rdata_dv_e1 <= '0';
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cpu_rdata_dv_e2 <= '0';
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cpu_rdata_ramsel_d1 <= '0';
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cpu_rdata_ramsel_d2 <= '0';
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elsif rising_edge(clk) then
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||||
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||||
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||||
-------------------------------------------------
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||||
-- CPU writing RAM
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||||
-------------------------------------------------
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||||
if (cpu_wr = '1') and (cpu_sel = '1') then
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||||
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||||
-- 0 for pulse definition, 1 for waveform table
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||||
if (cpu_addr(C_RAM_SELECT) = '1') then
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||||
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ram_pulse_addra <= (others=>'0');
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||||
ram_pulse_dina <= (others=>'0');
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ram_pulse_we <= (others=>'0');
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ram_waveform_wea(0) <= '1';
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ram_waveform_addra <= cpu_addr(10 downto 0);
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ram_waveform_dina <= cpu_wdata;
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else
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ram_pulse_addra <= cpu_addr(9 downto 0);
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ram_pulse_dina <= cpu_wdata;
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ram_pulse_we(0) <= '1';
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ram_waveform_wea <= (others=>'0');
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ram_waveform_addra <= (others=>'0');
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ram_waveform_dina <= (others=>'0');
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||||
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end if;
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cpu_rdata_dv_e1 <= '0';
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cpu_rdata_dv_e2 <= '0';
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cpu_rdata_ramsel_d1 <= '0';
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cpu_rdata_ramsel_d2 <= '0';
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||||
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||||
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||||
-------------------------------------------------
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||||
-- CPU read
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||||
-------------------------------------------------
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||||
elsif (cpu_wr = '0') and (cpu_sel = '1') then
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||||
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||||
if (cpu_addr(C_RAM_SELECT) = '1') then -- Waveform
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||||
ram_pulse_addra <= (others=>'0');
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||||
ram_waveform_addra <= cpu_addr(10 downto 0);
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else -- Pulse
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||||
ram_pulse_addra <= cpu_addr(9 downto 0);
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||||
ram_waveform_addra <= (others=>'0');
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||||
end if;
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||||
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||||
ram_pulse_we <= (others=>'0');
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||||
ram_waveform_wea(0) <= '0';
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||||
|
||||
cpu_rdata_dv_e2 <= '1'; -- DV for cycle, when RAM output occurs
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||||
cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
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||||
cpu_rdata_ramsel_d1 <= cpu_addr(C_RAM_SELECT); -- Save the select bit one cycle later
|
||||
cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1;
|
||||
|
||||
else
|
||||
ram_pulse_addra <= (others=>'0');
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||||
ram_pulse_we <= (others=>'0');
|
||||
ram_waveform_addra <= (others=>'0');
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||||
ram_waveform_wea(0) <= '0';
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||||
|
||||
cpu_rdata_dv_e2 <= '0';
|
||||
cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
|
||||
cpu_rdata_ramsel_d1 <= '0';
|
||||
cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1;
|
||||
|
||||
end if;
|
||||
|
||||
-------------------------------------------------
|
||||
-- Output the delayed RAM data
|
||||
-- This adds a pipeline delay to the cpu_rdata_dv to account for
|
||||
-- the delay in reading data from the RAM
|
||||
-------------------------------------------------
|
||||
if (cpu_rdata_dv_e1 = '1') then
|
||||
|
||||
cpu_rdata_dv <= '1';
|
||||
|
||||
-- Select source of output data
|
||||
if (cpu_rdata_ramsel_d2 = '1') then -- Output is from waveform table
|
||||
cpu_rdata <= ram_waveform_douta;
|
||||
|
||||
elsif (cpu_rdata_ramsel_d2 = '0') then
|
||||
cpu_rdata <= ram_pulse_douta;
|
||||
end if;
|
||||
|
||||
else
|
||||
cpu_rdata <= (others=>'0');
|
||||
cpu_rdata_dv <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- State machine:
|
||||
-- Compares cnt_time input against current output from pulse position RAM.
|
||||
-- When values match iti incremnts the pulse postion RAM address to
|
||||
-- retrieve the next pulse position and also starts reading the
|
||||
-- entire waveform table, one value every clock cycle, until it reaches the end.
|
||||
-- Once the pulse is complete it waits for the next cnt_time match.
|
||||
-- Repeat until all pulse position RAM times have triggered a pulse output
|
||||
-- or until the maximum counter time has been reached.
|
||||
----------------------------------------------------------------
|
||||
pr_sm : process (reset, clk)
|
||||
-- Temp variables for waveform output
|
||||
variable v_ram_waveform_doutb_multiplied : std_logic_vector(C_BITS_GAIN_FACTOR + 15 downto 0);
|
||||
variable v_ram_waveform_addrb_scaled : std_logic_vector(C_BITS_ADDR_START + 15 downto 0);
|
||||
variable v_ram_waveform_addrb_raw : unsigned(C_BITS_ADDR_START - 1 downto 0);
|
||||
begin
|
||||
if (reset = '1') then
|
||||
|
||||
sm_state <= S_IDLE; -- TODO: Eric: Should this be S_RESET since we reset the JEDS interface as well?
|
||||
ram_pulse_addrb <= (others=>'0');
|
||||
ram_waveform_addrb <= (others=>'0');
|
||||
cnt_addr <= (others=>'0');
|
||||
wave_last_addr <= (others=>'0');
|
||||
|
||||
sm_wavedata <= (others=>'0');
|
||||
sm_wavedata_dv <= '0';
|
||||
sm_busy <= '0';
|
||||
reg_wave_start_addr <= (others=>'0');
|
||||
reg_wave_length <= (others=>'0');
|
||||
reg_scale_gain <= (others=>'0');
|
||||
reg_scale_time <= (others=>'0');
|
||||
reg_wave_end_addr <= (others=>'0');
|
||||
reg_pulse_time <= (others=>'0');
|
||||
reg_pulse_flattop <= (others=>'0');
|
||||
|
||||
|
||||
pc <= (others=>'0');
|
||||
cnt_wave_len <= (others=>'0');
|
||||
cnt_wave_top <= (others=>'0');
|
||||
elsif rising_edge(clk) then
|
||||
|
||||
|
||||
-- Pipeline delays to use for rising edge detection
|
||||
enable_d1 <= enable;
|
||||
start_d1 <= start;
|
||||
sm_state_d1 <= sm_state;
|
||||
|
||||
-- Default
|
||||
sm_wavedata <= (others=>'0');
|
||||
sm_wavedata_dv <= '0';
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Main state machine
|
||||
------------------------------------------------------------------------
|
||||
case sm_state is
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Wait for rising edge of enable
|
||||
-- This is set when the JESD interface is aligned and functional.
|
||||
-- Send a zero value to initialize the DAC then go to idle.
|
||||
------------------------------------------------------------------------
|
||||
when S_RESET =>
|
||||
|
||||
if (enable = '1') and (enable_d1 = '0') then
|
||||
sm_wavedata <= (others=>'0');
|
||||
sm_wavedata_dv <= '1';
|
||||
sm_state <= S_IDLE;
|
||||
end if;
|
||||
sm_busy <= '0';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Wait for rising edge of 'start'.
|
||||
-- No data output.
|
||||
------------------------------------------------------------------------
|
||||
when S_IDLE =>
|
||||
|
||||
if (start = '1') and (start_d1 = '0') then
|
||||
sm_state <= S_LOAD;
|
||||
sm_busy <= '1';
|
||||
else
|
||||
sm_busy <= '0';
|
||||
end if;
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Load four addresses from pulse definition RAM into four 32 bits regesters
|
||||
------------------------------------------------------------------------
|
||||
when S_LOAD =>
|
||||
-- TODO: FromEric: does is needed here? or should be inside the if-else loops
|
||||
-- Load the pulse channel RAM addresses and start the waveform output
|
||||
sm_busy <= '1';
|
||||
if (sm_state_d1 = S_WAVE_DOWN) then -- output the last pulse definition address for one more clock cycle
|
||||
v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain);
|
||||
sm_wavedata <= v_ram_waveform_doutb_multiplied(30 downto 15);
|
||||
-- ram_waveform_addrb <= (others=>'0'); -- reset the address for the next waveform
|
||||
sm_wavedata_dv <= '1';
|
||||
end if;
|
||||
-- Pipline the pulse definition address
|
||||
if (unsigned(ram_pulse_addrb) mod 4 = 0) then
|
||||
ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 1);
|
||||
sm_state <= S_LOAD;
|
||||
-- first quarter of the pulse definition, no register is loaded
|
||||
|
||||
elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then
|
||||
ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 2);
|
||||
sm_state <= S_LOAD;
|
||||
-- second quarter of the pulse definition, the start time is loaded
|
||||
reg_pulse_time <= ram_pulse_doutb;
|
||||
|
||||
|
||||
elsif (unsigned(ram_pulse_addrb) mod 4 = 2) then
|
||||
ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 3);
|
||||
sm_state <= S_LOAD;
|
||||
-- third quarter of the pulse definition, the length and start address of the wavetable are loaded
|
||||
reg_wave_start_addr <= ram_pulse_doutb(C_BITS_ADDR_START - 1 downto 0);
|
||||
reg_wave_length <= unsigned(ram_pulse_doutb(25 downto 16)); -- TODO: make this a constant
|
||||
|
||||
elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then
|
||||
sm_state <= S_WAIT; -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state
|
||||
-- hold the last pulse definition address as it will be used in the next state
|
||||
pc <= std_logic_vector(unsigned(pc) + C_PC_INCR); -- incremnet the pulse counter and start waiting to output the wave
|
||||
-- forth quarter of the pulse definition, the scale factors are loaded
|
||||
reg_scale_gain <= unsigned(ram_pulse_doutb(31 downto 16));
|
||||
reg_scale_time <= unsigned(ram_pulse_doutb(15 downto 0));
|
||||
reg_wave_end_addr <= resize(unsigned(reg_wave_start_addr) + reg_wave_length, 20) sll 8; -- get the supposed last value of the wavetable
|
||||
|
||||
end if;
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Wait for cnt_time, external input, to match pulse position RAM output
|
||||
-- Return to idle state if max time is reached. Output waveform value zero.
|
||||
------------------------------------------------------------------------
|
||||
when S_WAIT =>
|
||||
-- read the last word of the pulse definition, the flat top value
|
||||
reg_pulse_flattop <= unsigned(ram_pulse_doutb(C_BITS_ADDR_TOP - 1 downto 0));
|
||||
-- Start to output wave and increment pulse position RAM address
|
||||
if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then
|
||||
sm_state <= S_WAVE_UP;
|
||||
|
||||
ram_waveform_addrb <= reg_wave_start_addr & std_logic_vector(to_unsigned(0, 8)); -- set the wavetable's address to the starting address defined from the pulse ram
|
||||
-- cnt_addr <= unsigned(reg_wave_start_addr);
|
||||
-- reset the wave lenth counter
|
||||
cnt_wave_len <= (others=>'0');
|
||||
elsif (cnt_time = X"FFFFFF") or (done_seq = '1') then
|
||||
sm_state <= S_IDLE;
|
||||
end if;
|
||||
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Output the raising edge of a waveform
|
||||
-- Hold the last address when complete
|
||||
------------------------------------------------------------------------
|
||||
when S_WAVE_UP =>
|
||||
-- Check if is end of rise of the waveform, next address >= end address. if so pad the address pointer to the end address and move to next state
|
||||
-- TODO: convert the numbers below to constaint. right now just make sure I'm not confused
|
||||
if (unsigned(ram_waveform_addrb) + reg_scale_time >= reg_wave_end_addr) then
|
||||
-- ram_waveform_addrb <= std_logic_vector(reg_wave_end_addr); -- pad the address pointer to the end address
|
||||
if (sm_state_d1 = S_WAVE_UP) then
|
||||
ram_waveform_addrb <= std_logic_vector(reg_wave_end_addr); -- pad the address pointer to the end address
|
||||
end if;
|
||||
wave_last_addr <= std_logic_vector(unsigned(ram_waveform_addrb)); -- hold the last address of the wavetable
|
||||
-- skip the flat top state if the flat top value is zero
|
||||
if (reg_pulse_flattop = 0) then
|
||||
sm_state <= S_WAVE_DOWN;
|
||||
-- reset the counter for the next transition
|
||||
cnt_wave_len <= (others=>'0');
|
||||
else
|
||||
sm_state <= S_WAVE_FLAT;
|
||||
-- reset the counter for the next transition
|
||||
cnt_wave_len <= (others=>'0');
|
||||
cnt_wave_top <= (others=>'0');
|
||||
end if;
|
||||
else
|
||||
cnt_wave_len <= cnt_wave_len + 1;
|
||||
cnt_addr <= cnt_addr + 1;
|
||||
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + reg_scale_time);
|
||||
wave_last_addr <= std_logic_vector(unsigned(ram_waveform_addrb) + reg_scale_time); -- hold the last address of the wavetable
|
||||
end if;
|
||||
|
||||
-- sm_wavedata <= std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain)(31 downto 16);
|
||||
-- Modelsim Cannot synthesize this above line, so we *have to* seperate them into two lines
|
||||
-- # ** Error: Prefix of slice name cannot be type conversion (STD_LOGIC_VECTOR) expression.
|
||||
v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain);
|
||||
sm_wavedata <= v_ram_waveform_doutb_multiplied(30 downto 15);
|
||||
if (sm_state_d1 = S_WAIT) then -- data valid is delayed by one clock cycle
|
||||
sm_wavedata_dv <= '0';
|
||||
else
|
||||
sm_wavedata_dv <= '1';
|
||||
end if;
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Hold the last address and output its data
|
||||
-- decrement from this address when finished waiting
|
||||
------------------------------------------------------------------------
|
||||
when S_WAVE_FLAT =>
|
||||
-- count the 17-bit flat top, if the counter reaches the flat top value, then go to the next state
|
||||
if (cnt_wave_top = reg_pulse_flattop) then
|
||||
sm_state <= S_WAVE_DOWN;
|
||||
|
||||
cnt_wave_top <= (others=>'0'); -- reset the counter for the next transition
|
||||
|
||||
else
|
||||
cnt_wave_top <= cnt_wave_top + 1;
|
||||
end if;
|
||||
v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain);
|
||||
sm_wavedata <= v_ram_waveform_doutb_multiplied(30 downto 15);
|
||||
sm_wavedata_dv <= '1';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Output the falling edge of a waveform
|
||||
-- Hold the start address when complete
|
||||
------------------------------------------------------------------------
|
||||
when S_WAVE_DOWN =>
|
||||
|
||||
-- End of waveform?
|
||||
-- TODO: convert the numbers below to constaint. right now just make sure I'm not confused
|
||||
if (unsigned(ram_waveform_addrb) - reg_scale_time < (resize(unsigned(reg_wave_start_addr), 20) sll 8)) or (unsigned(ram_waveform_addrb) = 0) then
|
||||
ram_waveform_addrb <= (others=>'0'); -- reset the address for the next waveform
|
||||
cnt_addr <= (others=>'0');
|
||||
-- If the end of the pulse table is reached then go to idle, increment pulse address for the next waveform otherwise
|
||||
if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_LEN_PULSE-1, C_BITS_ADDR_PULSE))) then
|
||||
ram_pulse_addrb <= (others=>'0');
|
||||
pc <= (others=>'0');
|
||||
sm_state <= S_IDLE;
|
||||
|
||||
else -- increment pulse address for the next waveform
|
||||
ram_pulse_addrb <= pc;
|
||||
sm_state <= S_LOAD;
|
||||
end if;
|
||||
|
||||
-- Output waveform from RAM with decremented address
|
||||
else
|
||||
cnt_wave_len <= cnt_wave_len + 1;
|
||||
-- ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - reg_scale_time);
|
||||
-- TODO: replace the above line with the following code if fall should be EXACTLY the same as rise
|
||||
if (sm_state_d1 = S_WAVE_FLAT) or (sm_state_d1 = S_WAVE_UP) then -- previous state was either S_WAVE_UP or S_WAVE_FLAT, so the ram_waveform_addrb should be whatever it was in the S_WAVE_UP state
|
||||
ram_waveform_addrb <= wave_last_addr; -- get the last address of the wavetable
|
||||
else
|
||||
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - reg_scale_time);
|
||||
end if;
|
||||
cnt_addr <= cnt_addr - 1;
|
||||
end if;
|
||||
v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain);
|
||||
sm_wavedata <= v_ram_waveform_doutb_multiplied(30 downto 15);
|
||||
sm_wavedata_dv <= '1';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Default
|
||||
------------------------------------------------------------------------
|
||||
when others =>
|
||||
sm_state <= S_IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
busy <= sm_busy;
|
||||
|
||||
-- AXI-Stream output.
|
||||
-- TBD: This should come from a FIFO
|
||||
-- TODO: the bits are not correct, should be top bits (C_BITS_GAIN_FACTOR + 16 downto C_BITS_GAIN_FACTOR), but for now just make it this way so modelsim can simulate
|
||||
axis_tdata <= sm_wavedata; -- axi stream output data, this output should be multiplied by the gain factor, then take the top 16 bits
|
||||
axis_tvalid <= sm_wavedata_dv; -- axi_stream output data valid
|
||||
|
||||
-- TBD : Generate in state machine?
|
||||
axis_tlast <= '0'; -- axi_stream output last
|
||||
end channel;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,30 +0,0 @@
|
|||
----------------------------------------------------------------------------------------
|
||||
-- Project : qlaser FPGA
|
||||
-- File : qlaser_dac_dc_pkg.vhd
|
||||
-- Description : Version package file.
|
||||
-- Author : akozyra
|
||||
----------------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
package qlaser_dac_dc_pkg is
|
||||
|
||||
----------------------------------------------------------------------------------------
|
||||
-- Constants
|
||||
----------------------------------------------------------------------------------------
|
||||
|
||||
-- Addresses
|
||||
constant C_ADDR_SPI0 : std_logic_vector(2 downto 0) := "000";
|
||||
constant C_ADDR_SPI1 : std_logic_vector(2 downto 0) := "001";
|
||||
constant C_ADDR_SPI2 : std_logic_vector(2 downto 0) := "010";
|
||||
constant C_ADDR_SPI3 : std_logic_vector(2 downto 0) := "011";
|
||||
constant C_ADDR_SPI_ALL : std_logic_vector(2 downto 0) := "100";
|
||||
constant C_ADDR_INTERNAL_REF : std_logic_vector(2 downto 0) := "101";
|
||||
constant C_ADDR_POWER_ON : std_logic_vector(2 downto 0) := "110";
|
||||
|
||||
-- Commands
|
||||
constant C_CMD_DAC_DC_WR : std_logic_vector(3 downto 0) := "0011";
|
||||
constant C_CMD_DAC_DC_INTERNAL_REF : std_logic_vector(3 downto 0) := "1000";
|
||||
constant C_CMD_DAC_DC_POWER : std_logic_vector(3 downto 0) := "0100";
|
||||
|
||||
end package qlaser_dac_dc_pkg;
|
||||
|
|
@ -1,38 +0,0 @@
|
|||
----------------------------------------------------------------------------------------
|
||||
-- Project : qlaser FPGA
|
||||
-- File : qlaser_dacs_pulse_channel.vhd
|
||||
-- Description : Pulse Channel package file specifying constants
|
||||
-- Author : eyhc
|
||||
----------------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
package qlaser_dacs_pulse_channel_pkg is
|
||||
-- Constants declearations
|
||||
constant C_RAM_SELECT : integer := 11; -- Select bit for which RAM for CPU read/write
|
||||
-- constant C_NUM_PULSE : integer := 16; -- Number of output data values from pulse RAM (16x24-bit)
|
||||
|
||||
constant C_START_TIME : integer := 24; -- Start time for pulse generation
|
||||
constant C_BITS_ADDR_START : integer := 12; -- Number of bits for starting address
|
||||
constant C_BITS_ADDR_LENGTH : integer := 10; -- Number of bits for length address used by an edge of a pulse
|
||||
constant C_BITS_GAIN_FACTOR : integer := 16; -- Number of bits in gain table
|
||||
constant C_BITS_TIME_FACTOR : integer := 16; -- Number of bits in time table
|
||||
constant C_BITS_TIME_INT : integer := 14; -- Starting bit for time integer part of the time factor, counting from MSB
|
||||
constant C_BITS_TIME_FRAC : integer := 5; -- Starting bit for time fractional part of the time factor, counting from MSB
|
||||
constant C_BITS_ADDR_TOP : integer := 17; -- Number of bits for the "flat top", the top of the pulse
|
||||
constant C_BITS_ADDR_FULL : integer := 20; -- Number of bits for the untruncated address, should be C_BITS_ADDR_LENGTH + fractional bits of time factor
|
||||
|
||||
constant C_LENGTH_WAVEFORM : integer := 4096; -- Number of output data values from waveform RAM (4kx16-bit)
|
||||
constant C_BITS_ADDR_WAVE : integer := 16; -- Number of bits in address for waveform RAM
|
||||
|
||||
constant C_BITS_ADDR_PULSE : integer := 10; -- Number of bits in address for pulse definition RAM
|
||||
constant C_LEN_PULSE : integer := 2**C_BITS_ADDR_PULSE; -- Numbers of address for pulse definition RAM
|
||||
constant C_PC_INCR : integer := 4;
|
||||
-- Width of pulse counter increment
|
||||
|
||||
|
||||
constant BIT_FRAC : integer := 8; -- Define the number of fractional bits
|
||||
constant BIT_FRAC_GAIN : integer := C_BITS_GAIN_FACTOR - 1; -- Define the number of fractional bits of the gain
|
||||
type real_array is array (natural range <>) of real;
|
||||
type int_array is array (natural range <>) of integer;
|
||||
end package qlaser_dacs_pulse_channel_pkg;
|
||||
|
|
@ -1,146 +0,0 @@
|
|||
-------------------------------------------------------------------------------
|
||||
-- Filename : qlaser_pkg.vhd
|
||||
-------------------------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.qlaser_dac_dc_pkg.all;
|
||||
-- use work.qlaser_dac_ac_pkg.all;
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- FPGA constant definitions
|
||||
-------------------------------------------------------------------------------
|
||||
package qlaser_pkg is
|
||||
|
||||
-- FPGA internal (PLL) clock freq expressed in MHz
|
||||
constant C_CLK_FREQ_MHZ : real := 100.0;
|
||||
-- Clock period
|
||||
constant C_CLK_PERIOD : time := integer(1.0E+6/(C_CLK_FREQ_MHZ)) * 1 ps;
|
||||
|
||||
constant C_NUM_CHAN_DC : integer := 32; -- Number of DC channels
|
||||
constant C_NUM_CHAN_AC : integer := 32; -- Number of AC (pulse) channels
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- FPGA Addresses
|
||||
-- Main blocks. Decoded from upper 4 bits of address [15:12]
|
||||
--------------------------------------------------------------------------------
|
||||
constant ADR_BASE_DC : std_logic_vector( 3 downto 0) := X"0"; -- Registers to load DC DAC values
|
||||
constant ADR_BASE_PULSE : std_logic_vector( 3 downto 0) := X"1"; -- RAMs for Pulse output start/stop times
|
||||
constant ADR_BASE_MISC : std_logic_vector( 3 downto 0) := X"2"; -- Misc, LEDs, switches, power control
|
||||
|
||||
--------------------------------------------------------------------------------
|
||||
-- Define the number of internal blocks that are addressed by the CPU
|
||||
--------------------------------------------------------------------------------
|
||||
constant C_NUM_BLOCKS : integer := 3;
|
||||
type t_arr_cpu_dout is array (0 to C_NUM_BLOCKS-1) of std_logic_vector(31 downto 0);
|
||||
type t_arr_dout_ac is array (0 to C_NUM_CHAN_AC-1) of std_logic_vector(15 downto 0);
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
-- 'DC' DAC block registers. 32 16-bit DAC outputs [5:3]
|
||||
constant C_ADDR_CH_SPI0 : std_logic_vector(2 downto 0) := "000";
|
||||
constant C_ADDR_CH_SPI1 : std_logic_vector(2 downto 0) := "001";
|
||||
constant C_ADDR_CH_SPI2 : std_logic_vector(2 downto 0) := "010";
|
||||
constant C_ADDR_CH_SPI3 : std_logic_vector(2 downto 0) := "011";
|
||||
constant C_ADDR_CH_SPI_ALL : std_logic_vector(2 downto 0) := "100";
|
||||
constant C_ADDR_INTERNAL_REF : std_logic_vector(2 downto 0) := "101";
|
||||
constant C_ADDR_POWER_ON : std_logic_vector(2 downto 0) := "110";
|
||||
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
-- Individual DAC data registers
|
||||
constant ADR_DAC_DC0 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "000"; --
|
||||
constant ADR_DAC_DC1 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "001"; --
|
||||
constant ADR_DAC_DC2 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "010"; --
|
||||
constant ADR_DAC_DC3 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "011"; --
|
||||
constant ADR_DAC_DC4 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "100"; --
|
||||
constant ADR_DAC_DC5 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "101"; --
|
||||
constant ADR_DAC_DC6 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "110"; --
|
||||
constant ADR_DAC_DC7 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "111"; --
|
||||
|
||||
constant ADR_DAC_DC8 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI1 & "000"; --
|
||||
constant ADR_DAC_DC9 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI1 & "001"; --
|
||||
|
||||
-- constant ADR_DAC_DC6 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI2 & "000"; --
|
||||
-- constant ADR_DAC_DC7 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI2 & "001"; --
|
||||
-- etc. etc.
|
||||
-- constant ADR_DAC_DC6 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI3 & "110"; --
|
||||
-- constant ADR_DAC_DC7 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI3 & "111"; --
|
||||
constant ADR_DAC_DC30 : std_logic_vector(15 downto 0) := ADR_BASE_DC & X"01E"; --
|
||||
constant ADR_DAC_DC31 : std_logic_vector(15 downto 0) := ADR_BASE_DC & X"01F"; --
|
||||
|
||||
constant ADR_DAC_DC_ALL : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_CH_SPI_ALL & "000"; -- Write all channels
|
||||
constant ADR_DAC_DC_IREF : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_INTERNAL_REF & "000"; --
|
||||
constant ADR_DAC_DC_POWER_ON : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_POWER_ON & "000"; --
|
||||
constant ADR_DAC_DC_STATUS : std_logic_vector(15 downto 0) := ADR_BASE_DC & X"000"; -- Reading any address returns SPI interface busy status (this was 32 bit, but decleared as 16, so I changed to 16)
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
-- 'Pulse' DAC block registers.
|
||||
-- The block has a set of block registers and contains 16 'channels'
|
||||
-- Each channel has a 40-bit memory to specify 24-bit time and a 16-bit level.
|
||||
-- Initially just using the MSB of the level to drive a single pin output
|
||||
--
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
-- Block-level registers
|
||||
-- CPU_ADDR(11) = '0' selects local regs
|
||||
-- CPU_ADDR(11) = '1' selects the channel specified in reg_ctrl(3 :0)
|
||||
-- Then CPU_ADDR(10:1) selects RAM word address (1024 address MAX)
|
||||
-- CPU_ADDR(0) selects MSB or LSB of 40-bit RAM word (time or amplitude)
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
-- Addresses for block-level registers.
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
constant ADR_DAC_PULSE_CTRL : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"800"; -- 4:0 select channel RAM for CPU read/write. Bit 8 is rising edge internal trigger
|
||||
constant ADR_DAC_PULSE_STATUS : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"801"; -- R/O Level status for output of each channel
|
||||
constant ADR_DAC_PULSE_RUNTIME : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"802"; -- Max time for pulse train
|
||||
constant ADR_DAC_PULSE_CH_EN : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"803"; -- Enable bit for each individual channel
|
||||
constant ADR_DAC_PULSE_TIMER : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"804"; -- R/O Current timer value (used by all channels)
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
-- Pulse Channel offsets
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
constant ADR_DAC_PULSE0 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"000"; -- Base address of a 16-word x 40-bit RAM
|
||||
constant ADR_DAC_PULSE1 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"040"; --
|
||||
constant ADR_DAC_PULSE2 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"080"; --
|
||||
constant ADR_DAC_PULSE3 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"0C0"; --
|
||||
--
|
||||
constant ADR_DAC_PULSE4 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"100"; --
|
||||
constant ADR_DAC_PULSE5 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"140"; --
|
||||
constant ADR_DAC_PULSE6 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"180"; --
|
||||
constant ADR_DAC_PULSE7 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"1C0"; --
|
||||
--
|
||||
constant ADR_DAC_PULSE8 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"200"; --
|
||||
constant ADR_DAC_PULSE9 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"240"; --
|
||||
constant ADR_DAC_PULSE10 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"280"; --
|
||||
constant ADR_DAC_PULSE11 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"2C0"; --
|
||||
--
|
||||
constant ADR_DAC_PULSE12 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"300"; --
|
||||
constant ADR_ADC_PULSE13 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"340"; --
|
||||
constant ADR_DAC_PULSE14 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"380"; --
|
||||
constant ADR_DAC_PULSE15 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"3C0"; --
|
||||
--
|
||||
-- etc. etc.
|
||||
constant ADR_DAC_PULSE28 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"700"; --
|
||||
constant ADR_DAC_PULSE29 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"740"; --
|
||||
constant ADR_DAC_PULSE30 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"780"; --
|
||||
constant ADR_DAC_PULSE31 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"7C0"; --
|
||||
|
||||
|
||||
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
-- Misc block registers
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
constant ADR_MISC_VERSION : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"000"; -- HDL code version
|
||||
constant ADR_MISC_LEDS : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"001"; -- LEDs
|
||||
constant ADR_MISC_LEDS_EN : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"002"; -- LEDs enable
|
||||
constant ADR_MISC_SW_IN : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"003"; -- Read board switch settings (if present)
|
||||
constant ADR_MISC_DEBUG_CTRL : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"004"; -- Select debug output from top level to pins
|
||||
|
||||
|
||||
end package;
|
||||
|
||||
package body qlaser_pkg is
|
||||
|
||||
end package body;
|
||||
|
||||
|
|
@ -1,44 +0,0 @@
|
|||
-----------------------------------------------------------
|
||||
-- File : poly_gen_nonsynth.vhdl
|
||||
-----------------------------------------------------------
|
||||
--
|
||||
-- Simulation-only module of a floating point polynomial calculator
|
||||
--
|
||||
-- Description : Calculates the value of a polynomial at a given time, using the coefficients
|
||||
--
|
||||
----------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_1164.all;
|
||||
use std.textio.all;
|
||||
|
||||
use ieee.math_real.uniform;
|
||||
use ieee.math_real.floor;
|
||||
|
||||
|
||||
use work.std_iopak.all;
|
||||
use work.qlaser_dacs_pulse_channel_pkg.all;
|
||||
entity poly_gen is
|
||||
generic (
|
||||
degrees : natural := 5 -- n-th degree polynomial
|
||||
);
|
||||
port (
|
||||
clk : in std_logic;
|
||||
direction : in std_logic; -- 0 = rising, 1 = falling
|
||||
times : in integer; -- time stamp
|
||||
coeffs : in real_array(0 to degrees-1); -- coefficients coeffs_array : real_array(0 to degrees-1);
|
||||
poly_out : out real
|
||||
);
|
||||
end entity poly_gen;
|
||||
|
||||
architecture nonsynth of poly_gen is
|
||||
-- type real_array is array (0 to degrees-1) of real;
|
||||
-- signal coeffs_array : real_array;
|
||||
-- variable poly_sum : real := 0.0;
|
||||
begin
|
||||
-- wait until clk'event and clk='0';
|
||||
-- for i in 0 to degrees loop
|
||||
-- poly_sum := poly_sum + coeffs_array(i) * times**i;
|
||||
-- end loop;
|
||||
-- poly_out <= poly_sum;
|
||||
end architecture nonsynth;
|
||||
|
|
@ -1,487 +0,0 @@
|
|||
-----------------------------------------------------------
|
||||
-- File : tb_cpubus_dacs_pulse_channel.vhd
|
||||
-----------------------------------------------------------
|
||||
--
|
||||
-- Testbench for CPU bus peripheral.
|
||||
--
|
||||
-- Description : Pulse output control of Qlaser FPGA
|
||||
-- Block drives AXI-stream to JESD DACs
|
||||
--
|
||||
----------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_1164.all;
|
||||
use std.textio.all;
|
||||
|
||||
use work.std_iopak.all;
|
||||
use work.qlaser_dacs_pulse_channel_pkg.all;
|
||||
|
||||
|
||||
entity tb_cpubus_dacs_pulse_channel is
|
||||
end tb_cpubus_dacs_pulse_channel;
|
||||
|
||||
architecture behave of tb_cpubus_dacs_pulse_channel is
|
||||
|
||||
signal clk : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal enable : std_logic;
|
||||
signal start : std_logic;
|
||||
signal cnt_time : std_logic_vector(23 downto 0);
|
||||
signal busy : std_logic;
|
||||
signal done_seq : std_logic;
|
||||
signal cpu_wr : std_logic;
|
||||
signal cpu_sel : std_logic;
|
||||
signal cpu_addr : std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata : std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata_dv : std_logic;
|
||||
|
||||
-- AXI-stream output interface
|
||||
signal axis_tready : std_logic := '1'; -- Always ready
|
||||
signal axis_tdata : std_logic_vector(15 downto 0);
|
||||
signal axis_tvalid : std_logic;
|
||||
signal axis_tlast : std_logic;
|
||||
|
||||
-- Halts simulation by stopping clock when set true
|
||||
signal sim_done : boolean := false;
|
||||
|
||||
-- Crystal clock freq expressed in MHz
|
||||
constant CLK_FREQ_MHZ : real := 100.0;
|
||||
-- Clock period
|
||||
constant CLK_PER : time := integer(1.0E+6/(CLK_FREQ_MHZ)) * 1 ps;
|
||||
|
||||
-- Block registers
|
||||
-- constant ADR_RAM_PULSE : integer := to_integer(unsigned(X"0000")); -- TODO: Modelsim cannot compile this
|
||||
-- constant ADR_RAM_WAVE : integer := to_integer(unsigned(X"0200")); -- TODO: Modelsim cannot compile this
|
||||
constant ADR_RAM_PULSE : integer := 0; -- TODO: Modelsim cannot compile this
|
||||
constant ADR_RAM_WAVE : integer := 2048; -- TODO: Modelsim cannot compile this
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write procedure. Address in decimal. Data in hex
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant d : in std_logic_vector(31 downto 0);
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
begin
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
cpu_wr <= '1';
|
||||
cpu_addr <= std_logic_vector(to_unsigned(a, 16));
|
||||
cpu_wdata <= std_logic_vector(d);
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '0';
|
||||
cpu_wr <= '0';
|
||||
cpu_addr <= (others=>'0');
|
||||
cpu_wdata <= (others=>'0');
|
||||
wait until clk'event and clk='0';
|
||||
end;
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write procedure. Address and Data in decimal
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant d : in integer;
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
begin
|
||||
cpu_write(clk, a , std_logic_vector(to_unsigned(d,32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write pulse definition RAM
|
||||
-- Make fore 32-bit data write
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write_pulsedef(
|
||||
signal clk : in std_logic;
|
||||
|
||||
constant num_entry : in integer;
|
||||
|
||||
-- TODO: Partial ? list of parameters, there could be more if need more features
|
||||
constant pulsetime : in integer; -- Pulse time in clock cycles
|
||||
constant timefactor : in real; -- Fixed point time scale factor
|
||||
constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000"
|
||||
constant wavestartaddr : in integer; -- Start address in waveform RAM
|
||||
constant wavesteps : in integer; -- Number of steps in waveform rise and fall
|
||||
constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall
|
||||
|
||||
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
-- Vectors for converted values
|
||||
variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time
|
||||
variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep
|
||||
variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain
|
||||
variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM
|
||||
variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform
|
||||
|
||||
-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg
|
||||
-- Define the number of fractional bits
|
||||
begin
|
||||
|
||||
-- Convert each field into its std_logic_vector equivalent
|
||||
slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24));
|
||||
slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12));
|
||||
slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10));
|
||||
slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17));
|
||||
|
||||
|
||||
--etc, etc.
|
||||
-- 4 writes. (Address is an integer)
|
||||
cpu_write(clk, ADR_RAM_PULSE+num_entry , x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
cpu_write(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"0" & slv_wavesteps & x"0" & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
cpu_write(clk, ADR_RAM_PULSE+(num_entry+2) , slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
cpu_write(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU read procedure
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_read(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant exp_d : in std_logic_vector(31 downto 0);
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata : in std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata_dv : in std_logic
|
||||
) is
|
||||
variable v_bdone : boolean := false;
|
||||
variable str_out : string(1 to 256);
|
||||
begin
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
cpu_wr <= '0';
|
||||
cpu_addr <= std_logic_vector(to_unsigned(a, 16));
|
||||
cpu_wdata <= (others=>'0');
|
||||
while (v_bdone = false) loop
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
if (cpu_rdata_dv = '1') then
|
||||
if (cpu_rdata /= exp_d) then
|
||||
fprint(str_out, "Read exp: 0x%s actual: 0x%s\n", to_string(to_bitvector(exp_d),"%08X"), to_string(to_bitvector(cpu_rdata),"%08X"));
|
||||
report str_out severity error;
|
||||
end if;
|
||||
v_bdone := true;
|
||||
cpu_sel <= '0';
|
||||
cpu_addr <= (others=>'0');
|
||||
end if;
|
||||
end loop;
|
||||
wait until clk'event and clk='0';
|
||||
wait until clk'event and clk='0';
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU read pulse definition RAM
|
||||
-- make four 32-bit reads
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_read_pulsedef(
|
||||
signal clk : in std_logic;
|
||||
|
||||
constant num_entry : in integer;
|
||||
|
||||
-- TODO: Partial ? list of parameters, there could be more if need more features
|
||||
constant pulsetime : in integer; -- Pulse time in clock cycles
|
||||
constant timefactor : in real; -- Fixed point time scale factor
|
||||
constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000"
|
||||
constant wavestartaddr : in integer; -- Start address in waveform RAM
|
||||
constant wavesteps : in integer; -- Number of steps in waveform rise and fall
|
||||
constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall
|
||||
|
||||
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
-- Vectors for converted values
|
||||
variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time
|
||||
variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep
|
||||
variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain
|
||||
variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM
|
||||
variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform
|
||||
|
||||
-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg
|
||||
-- Define the number of fractional bits
|
||||
begin
|
||||
|
||||
-- Convert each field into its std_logic_vector equivalent
|
||||
slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24));
|
||||
slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12));
|
||||
slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10));
|
||||
slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17));
|
||||
|
||||
|
||||
--etc, etc.
|
||||
-- 4 writes. (Address is an integer)
|
||||
cpu_read(clk, ADR_RAM_PULSE+num_entry, x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
cpu_read(clk, ADR_RAM_PULSE+(num_entry+1), "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
cpu_read(clk, ADR_RAM_PULSE+(num_entry+2), slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
cpu_read(clk, ADR_RAM_PULSE+(num_entry+3), "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Delay
|
||||
-------------------------------------------------------------
|
||||
procedure clk_delay(
|
||||
constant nclks : in integer
|
||||
) is
|
||||
begin
|
||||
for I in 0 to nclks loop
|
||||
wait until clk'event and clk ='0';
|
||||
end loop;
|
||||
end;
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Print a string with no time or instance path.
|
||||
----------------------------------------------------------------
|
||||
procedure cpu_print_msg(
|
||||
constant msg : in string
|
||||
) is
|
||||
variable line_out : line;
|
||||
begin
|
||||
write(line_out, msg);
|
||||
writeline(output, line_out);
|
||||
end procedure cpu_print_msg;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Unit Under Test
|
||||
-------------------------------------------------------------
|
||||
u_dac_pulse : entity work.qlaser_dacs_pulse_channel
|
||||
port map (
|
||||
clk => clk , -- in std_logic;
|
||||
reset => reset , -- in std_logic;
|
||||
|
||||
enable => enable , -- out std_logic;
|
||||
start => start , -- out std_logic;
|
||||
cnt_time => cnt_time , -- out std_logic_vector(23 downto 0); -- Set to '1' while SPI interface is busy
|
||||
|
||||
busy => busy , -- out std_logic; -- Set to '1' while SPI interface is busy
|
||||
done_seq => done_seq , -- in std_logic; -- Set to '1' when SPI sequence is done
|
||||
|
||||
-- CPU interface
|
||||
cpu_wr => cpu_wr , -- in std_logic;
|
||||
cpu_sel => cpu_sel , -- in std_logic;
|
||||
cpu_addr => cpu_addr(11 downto 0) , -- in std_logic_vector(11 downto 0);
|
||||
cpu_wdata => cpu_wdata , -- in std_logic_vector(31 downto 0);
|
||||
|
||||
cpu_rdata => cpu_rdata , -- out std_logic_vector(31 downto 0);
|
||||
cpu_rdata_dv => cpu_rdata_dv , -- out std_logic;
|
||||
|
||||
|
||||
-- AXI-Stream interface
|
||||
axis_tready => axis_tready , -- in std_logic; -- Clock (50 MHz max)
|
||||
axis_tdata => axis_tdata , -- out std_logic_vector(15 downto 0);
|
||||
axis_tvalid => axis_tvalid , -- out std_logic; -- Master out, Slave in. (Data to DAC)
|
||||
axis_tlast => axis_tlast -- out std_logic; -- Active low chip select (sync_n)
|
||||
);
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Generate system clock. Halt when sim_done is true.
|
||||
-------------------------------------------------------------
|
||||
pr_clk : process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for (CLK_PER/2);
|
||||
clk <= '1';
|
||||
wait for (CLK_PER-CLK_PER/2);
|
||||
if (sim_done=true) then
|
||||
wait;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Reset and drive CPU bus
|
||||
-------------------------------------------------------------
|
||||
pr_main : process
|
||||
variable v_ndata32 : integer := 0;
|
||||
variable v_ndata16 : integer := 0;
|
||||
|
||||
-- "global" variables for base definitions of each pulses, all pulses are based on these but scaled/offset a bit
|
||||
variable v_pulseaddr : integer := 0; -- manually set the pulse address, 0 to 255
|
||||
variable v_waveaddr : integer := 0; -- manually set the wave address, 0 to 2047
|
||||
variable v_pulsetime : integer := 0; -- For 24-bit pulse time
|
||||
variable v_timefactor : real := 0.0; -- For 16-bit fixed point timestep
|
||||
variable v_gainfactor : real := 0.0; -- For 16-bit fixed point gain
|
||||
variable v_wavestartaddr : integer := 0; -- For 12-bit address i.e. 1024 point waveform RAM
|
||||
variable v_wavesteps : integer := 0; -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable v_wavetopwidth : integer := 0; -- For 17-bit number of clock cycles in top of waveform
|
||||
|
||||
begin
|
||||
-- Reset
|
||||
reset <= '1';
|
||||
enable <= '0';
|
||||
start <= '0';
|
||||
done_seq <= '0';
|
||||
cnt_time <= (others=>'0');
|
||||
|
||||
cpu_sel <= '0';
|
||||
cpu_wr <= '0';
|
||||
cpu_wdata <= (others=>'0');
|
||||
cpu_addr <= (others=>'0');
|
||||
|
||||
cpu_print_msg("Simulation start");
|
||||
clk_delay(5);
|
||||
reset <= '0';
|
||||
|
||||
clk_delay(5);
|
||||
enable <= '1';
|
||||
|
||||
|
||||
clk_delay(20);
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Load pulse RAM with a series of pulse start times
|
||||
----------------------------------------------------------------
|
||||
-- v_ndata32 := 128; -- Time for first pulse
|
||||
v_pulsetime := 128;
|
||||
cpu_print_msg("Load pulse RAM");
|
||||
-- for NADDR in 0 to 255 loop
|
||||
-- -- TODO: In the real setting should we have the python script to check those parameters to make sure they are valid and non-overlapping?
|
||||
-- -- v_pulsetime := v_ndata32 + (NADDR*(1024+32)); -- todo: what is this math doing?
|
||||
|
||||
-- v_timefactor := 1.0;
|
||||
-- v_gainfactor := 1.0;
|
||||
-- v_wavestartaddr := v_wavesteps + v_wavestartaddr; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right?
|
||||
-- v_wavesteps := NADDR;
|
||||
-- v_wavetopwidth := 114;
|
||||
-- v_pulsetime := (v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3);
|
||||
-- -- cpu_write_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
-- cpu_write_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
-- end loop;
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Load pulse RAM with a series of pulse start times MANUALLY
|
||||
---------------------------------------------------------------
|
||||
v_pulseaddr := 0;
|
||||
v_pulsetime := 4;
|
||||
v_timefactor := 1.0;
|
||||
v_gainfactor := 1.0;
|
||||
v_wavestartaddr := 1; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right?
|
||||
v_wavesteps := 4;
|
||||
v_wavetopwidth := 1;
|
||||
cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
|
||||
|
||||
v_pulseaddr := 1;
|
||||
v_timefactor := 1.0;
|
||||
v_gainfactor := 1.0;
|
||||
v_wavestartaddr := 4; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right?
|
||||
v_wavesteps := 6;
|
||||
v_wavetopwidth := 9;
|
||||
v_pulsetime := v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3;
|
||||
cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
|
||||
|
||||
cpu_print_msg("Pulse RAM loaded");
|
||||
clk_delay(20);
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Load waveform RAM with a simple ramp
|
||||
-- Write two 16-bit values with each write
|
||||
----------------------------------------------------------------
|
||||
cpu_print_msg("Load waveform RAM");
|
||||
v_ndata16 := 1; -- first waveform value
|
||||
for NADDR in 0 to 2047 loop
|
||||
v_ndata32 := (((v_ndata16) * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1)); -- Write two 16-bit values with each write
|
||||
cpu_write(clk, (ADR_RAM_WAVE + NADDR) , v_ndata32, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
v_ndata16 := v_ndata16 + 2;
|
||||
end loop;
|
||||
|
||||
|
||||
-- ----------------------------------------------------------------
|
||||
-- -- Read back Pulse RAM.
|
||||
-- -- Comment out if not needed to check CPU R/W
|
||||
-- ----------------------------------------------------------------
|
||||
-- v_ndata32 := 128; -- Time for first pulse
|
||||
-- for NADDR in 0 to 255 loop
|
||||
-- v_pulsetime := v_ndata32 + (NADDR*(1024+32));
|
||||
-- v_timefactor := 1.0;
|
||||
-- v_gainfactor := 1.0;
|
||||
-- v_wavestartaddr := 0;
|
||||
-- v_wavesteps := NADDR*32;
|
||||
-- v_wavetopwidth := 0;
|
||||
-- cpu_read_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
-- end loop;
|
||||
-- clk_delay(20);
|
||||
|
||||
-- ----------------------------------------------------------------
|
||||
-- -- Read back Waveform RAM
|
||||
-- ----------------------------------------------------------------
|
||||
-- v_ndata16 := 1; -- first waveform value
|
||||
-- for NADDR in 0 to 2047 loop
|
||||
-- v_ndata32 := (((v_ndata16) * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1));
|
||||
-- cpu_read (clk, ADR_RAM_WAVE + NADDR , std_logic_vector(to_unsigned(v_ndata32, 32)) , cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
-- v_ndata16 := v_ndata16 + 2;
|
||||
-- end loop;
|
||||
|
||||
-- -- Done reg write/read check
|
||||
-- cpu_print_msg("RAM readback completed");
|
||||
-- clk_delay(20);
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Start the pulse outputs
|
||||
----------------------------------------------------------------
|
||||
done_seq <= '0';
|
||||
clk_delay(5);
|
||||
start <= '1';
|
||||
clk_delay(5);
|
||||
start <= '0';
|
||||
|
||||
-- TODO: we may need to modify the for loop to make sure the simulation time is long enough to cover all the pulses
|
||||
-- Wait for cnt_time to reach last pulse start time + waveform size
|
||||
for NCNT in 1 to v_pulsetime + 100 loop -- TODO: EricToGeoff/Sara: in the real settings do we have a constant amount of time or the total time also vary? if so, how much?
|
||||
-- for NCNT in 1 to 128 loop -- count the time shorter for now so it won't take too long to simulate
|
||||
cnt_time <= std_logic_vector(unsigned(cnt_time) + 1);
|
||||
-- if (NCNT = v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 8) then -- Stop simulation when last pulse is done
|
||||
-- done_seq <= '1';
|
||||
-- end if;
|
||||
clk_delay(0);
|
||||
end loop;
|
||||
|
||||
wait for 10 us;
|
||||
|
||||
cpu_print_msg("Simulation done");
|
||||
clk_delay(5);
|
||||
|
||||
sim_done <= true;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end behave;
|
||||
|
||||
|
|
@ -1,514 +0,0 @@
|
|||
-----------------------------------------------------------
|
||||
-- File : tb_cpubus_dacs_pulse_channel.vhd
|
||||
-----------------------------------------------------------
|
||||
--
|
||||
-- Testbench for CPU bus peripheral.
|
||||
--
|
||||
-- Description : Pulse output control of Qlaser FPGA
|
||||
-- Block drives AXI-stream to JESD DACs
|
||||
--
|
||||
----------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_1164.all;
|
||||
use std.textio.all;
|
||||
|
||||
use ieee.math_real.uniform;
|
||||
use ieee.math_real.floor;
|
||||
|
||||
|
||||
use work.std_iopak.all;
|
||||
use work.qlaser_dacs_pulse_channel_pkg.all;
|
||||
|
||||
|
||||
entity tb_cpubus_dacs_pulse_channel is
|
||||
end tb_cpubus_dacs_pulse_channel;
|
||||
|
||||
architecture behave of tb_cpubus_dacs_pulse_channel is
|
||||
|
||||
signal clk : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal enable : std_logic;
|
||||
signal start : std_logic;
|
||||
signal cnt_time : std_logic_vector(23 downto 0);
|
||||
signal busy : std_logic;
|
||||
signal done_seq : std_logic;
|
||||
signal cpu_wr : std_logic;
|
||||
signal cpu_sel : std_logic;
|
||||
signal cpu_addr : std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata : std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata_dv : std_logic;
|
||||
|
||||
-- AXI-stream output interface
|
||||
signal axis_tready : std_logic := '1'; -- Always ready
|
||||
signal axis_tdata : std_logic_vector(15 downto 0);
|
||||
signal axis_tvalid : std_logic;
|
||||
signal axis_tlast : std_logic;
|
||||
|
||||
-- Halts simulation by stopping clock when set true
|
||||
signal sim_done : boolean := false;
|
||||
|
||||
-- Crystal clock freq expressed in MHz
|
||||
constant CLK_FREQ_MHZ : real := 100.0;
|
||||
-- Clock period
|
||||
constant CLK_PER : time := integer(1.0E+6/(CLK_FREQ_MHZ)) * 1 ps;
|
||||
|
||||
-- Block registers
|
||||
-- constant ADR_RAM_PULSE : integer := to_integer(unsigned(X"0000")); -- TODO: Modelsim cannot compile this
|
||||
-- constant ADR_RAM_WAVE : integer := to_integer(unsigned(X"0200")); -- TODO: Modelsim cannot compile this
|
||||
constant ADR_RAM_PULSE : integer := 0; -- TODO: Modelsim cannot compile this
|
||||
constant ADR_RAM_WAVE : integer := 2048; -- TODO: Modelsim cannot compile this
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write procedure. Address in decimal. Data in hex
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant d : in std_logic_vector(31 downto 0);
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
begin
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
cpu_wr <= '1';
|
||||
cpu_addr <= std_logic_vector(to_unsigned(a, 16));
|
||||
cpu_wdata <= std_logic_vector(d);
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '0';
|
||||
cpu_wr <= '0';
|
||||
cpu_addr <= (others=>'0');
|
||||
cpu_wdata <= (others=>'0');
|
||||
wait until clk'event and clk='0';
|
||||
end;
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write procedure. Address and Data in decimal
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant d : in integer;
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
begin
|
||||
cpu_write(clk, a , std_logic_vector(to_unsigned(d,32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write pulse definition RAM
|
||||
-- Make fore 32-bit data write
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write_pulsedef(
|
||||
signal clk : in std_logic;
|
||||
|
||||
constant num_entry : in integer;
|
||||
|
||||
-- TODO: Partial ? list of parameters, there could be more if need more features
|
||||
constant pulsetime : in integer; -- Pulse time in clock cycles
|
||||
constant timefactor : in real; -- Fixed point time scale factor
|
||||
constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000"
|
||||
constant wavestartaddr : in integer; -- Start address in waveform RAM
|
||||
constant wavesteps : in integer; -- Number of steps in waveform rise and fall
|
||||
constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall
|
||||
|
||||
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
-- Vectors for converted values
|
||||
variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time
|
||||
variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep
|
||||
variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain
|
||||
variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM
|
||||
variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform
|
||||
|
||||
-- Define the number of fractional bits
|
||||
begin
|
||||
|
||||
-- Convert each field into its std_logic_vector equivalent
|
||||
slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24));
|
||||
slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12));
|
||||
slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10));
|
||||
slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17));
|
||||
|
||||
|
||||
--etc, etc.
|
||||
-- 4 writes. (Address is an integer)
|
||||
cpu_write(clk, ADR_RAM_PULSE+num_entry , x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
cpu_write(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"0" & slv_wavesteps & x"0" & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
cpu_write(clk, ADR_RAM_PULSE+(num_entry+2) , slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
cpu_write(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU read procedure
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_read(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant exp_d : in std_logic_vector(31 downto 0);
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata : in std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata_dv : in std_logic
|
||||
) is
|
||||
variable v_bdone : boolean := false;
|
||||
variable str_out : string(1 to 256);
|
||||
variable diff : integer;
|
||||
begin
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
cpu_wr <= '0';
|
||||
cpu_addr <= std_logic_vector(to_unsigned(a, 16));
|
||||
cpu_wdata <= (others=>'0');
|
||||
while (v_bdone = false) loop
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
if (cpu_rdata_dv = '1') then
|
||||
if (cpu_rdata /= exp_d) then
|
||||
diff := abs(to_integer(unsigned(exp_d)) - to_integer(unsigned(cpu_rdata)));
|
||||
fprint(str_out, "Read exp: 0x%s actual: 0x%s\n", to_string(to_bitvector(exp_d),"%08X"), to_string(to_bitvector(cpu_rdata),"%08X"));
|
||||
report str_out severity warning;
|
||||
-- TODO: this is not working, need to fix it
|
||||
-- fprint(str_out, "Absolute difference: 0x%s\n", to_string(to_bitvector(diff),"%08X"));
|
||||
report str_out severity warning;
|
||||
end if;
|
||||
v_bdone := true;
|
||||
cpu_sel <= '0';
|
||||
cpu_addr <= (others=>'0');
|
||||
end if;
|
||||
end loop;
|
||||
wait until clk'event and clk='0';
|
||||
wait until clk'event and clk='0';
|
||||
end;
|
||||
|
||||
-- TODO: implement the checker method for the the output of the entier wave
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU read pulse definition RAM
|
||||
-- make four 32-bit reads
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_read_pulsedef(
|
||||
signal clk : in std_logic;
|
||||
|
||||
constant num_entry : in integer;
|
||||
|
||||
-- TODO: Partial ? list of parameters, there could be more if need more features
|
||||
constant pulsetime : in integer; -- Pulse time in clock cycles
|
||||
constant timefactor : in real; -- Fixed point time scale factor
|
||||
constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000"
|
||||
constant wavestartaddr : in integer; -- Start address in waveform RAM
|
||||
constant wavesteps : in integer; -- Number of steps in waveform rise and fall
|
||||
constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall
|
||||
|
||||
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
-- Vectors for converted values
|
||||
variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time
|
||||
variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep
|
||||
variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain
|
||||
variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM
|
||||
variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform
|
||||
|
||||
-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg
|
||||
-- Define the number of fractional bits
|
||||
begin
|
||||
|
||||
-- Convert each field into its std_logic_vector equivalent
|
||||
slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24));
|
||||
slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12));
|
||||
slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10));
|
||||
slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17));
|
||||
|
||||
|
||||
--etc, etc.
|
||||
-- 4 writes. (Address is an integer)
|
||||
cpu_read(clk, ADR_RAM_PULSE+num_entry, x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
cpu_read(clk, ADR_RAM_PULSE+(num_entry+1), "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
cpu_read(clk, ADR_RAM_PULSE+(num_entry+2), slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
cpu_read(clk, ADR_RAM_PULSE+(num_entry+3), "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Delay
|
||||
-------------------------------------------------------------
|
||||
procedure clk_delay(
|
||||
constant nclks : in integer
|
||||
) is
|
||||
begin
|
||||
for I in 0 to nclks loop
|
||||
wait until clk'event and clk ='0';
|
||||
end loop;
|
||||
end;
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Print a string with no time or instance path.
|
||||
----------------------------------------------------------------
|
||||
procedure cpu_print_msg(
|
||||
constant msg : in string
|
||||
) is
|
||||
variable line_out : line;
|
||||
begin
|
||||
write(line_out, msg);
|
||||
writeline(output, line_out);
|
||||
end procedure cpu_print_msg;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Unit Under Test
|
||||
-------------------------------------------------------------
|
||||
u_dac_pulse : entity work.qlaser_dacs_pulse_channel
|
||||
port map (
|
||||
clk => clk , -- in std_logic;
|
||||
reset => reset , -- in std_logic;
|
||||
|
||||
enable => enable , -- out std_logic;
|
||||
start => start , -- out std_logic;
|
||||
cnt_time => cnt_time , -- out std_logic_vector(23 downto 0); -- Set to '1' while SPI interface is busy
|
||||
|
||||
busy => busy , -- out std_logic; -- Set to '1' while SPI interface is busy
|
||||
done_seq => done_seq , -- in std_logic; -- Set to '1' when SPI sequence is done
|
||||
|
||||
-- CPU interface
|
||||
cpu_wr => cpu_wr , -- in std_logic;
|
||||
cpu_sel => cpu_sel , -- in std_logic;
|
||||
cpu_addr => cpu_addr(11 downto 0) , -- in std_logic_vector(11 downto 0);
|
||||
cpu_wdata => cpu_wdata , -- in std_logic_vector(31 downto 0);
|
||||
|
||||
cpu_rdata => cpu_rdata , -- out std_logic_vector(31 downto 0);
|
||||
cpu_rdata_dv => cpu_rdata_dv , -- out std_logic;
|
||||
|
||||
|
||||
-- AXI-Stream interface
|
||||
axis_tready => axis_tready , -- in std_logic; -- Clock (50 MHz max)
|
||||
axis_tdata => axis_tdata , -- out std_logic_vector(15 downto 0);
|
||||
axis_tvalid => axis_tvalid , -- out std_logic; -- Master out, Slave in. (Data to DAC)
|
||||
axis_tlast => axis_tlast -- out std_logic; -- Active low chip select (sync_n)
|
||||
);
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Generate system clock. Halt when sim_done is true.
|
||||
-------------------------------------------------------------
|
||||
pr_clk : process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for (CLK_PER/2);
|
||||
clk <= '1';
|
||||
wait for (CLK_PER-CLK_PER/2);
|
||||
if (sim_done=true) then
|
||||
wait;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Reset and drive CPU bus
|
||||
-------------------------------------------------------------
|
||||
pr_main : process
|
||||
variable v_ndata32 : integer := 0;
|
||||
variable v_ndata16 : integer := 0;
|
||||
|
||||
-- "global" variables for base definitions of each pulses, all pulses are based on these but scaled/offset a bit
|
||||
variable v_pulseaddr : integer := 0; -- manually set the pulse address, 0 to 255
|
||||
variable v_waveaddr : integer := 0; -- manually set the wave address, 0 to 2047
|
||||
variable v_pulsetime : integer := 0; -- For 24-bit pulse time
|
||||
variable v_timefactor : real := 0.0; -- For 16-bit fixed point timestep
|
||||
variable v_gainfactor : real := 0.0; -- For 16-bit fixed point gain
|
||||
variable v_wavestartaddr : integer := 0; -- For 12-bit address i.e. 1024 point waveform RAM
|
||||
variable v_wavesteps : integer := 0; -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable v_wavetopwidth : integer := 0; -- For 17-bit number of clock cycles in top of waveform
|
||||
|
||||
variable seed1 : positive;
|
||||
variable seed2 : positive;
|
||||
variable x : real;
|
||||
variable y : real;
|
||||
|
||||
|
||||
begin
|
||||
-- Reset
|
||||
reset <= '1';
|
||||
enable <= '0';
|
||||
start <= '0';
|
||||
done_seq <= '0';
|
||||
cnt_time <= (others=>'0');
|
||||
|
||||
cpu_sel <= '0';
|
||||
cpu_wr <= '0';
|
||||
cpu_wdata <= (others=>'0');
|
||||
cpu_addr <= (others=>'0');
|
||||
|
||||
cpu_print_msg("Simulation start");
|
||||
clk_delay(5);
|
||||
reset <= '0';
|
||||
|
||||
clk_delay(5);
|
||||
enable <= '1';
|
||||
|
||||
|
||||
clk_delay(20);
|
||||
|
||||
seed1 := 2045;
|
||||
seed2 := 1024;
|
||||
----------------------------------------------------------------
|
||||
-- Load pulse RAM with a series of pulse start times
|
||||
----------------------------------------------------------------
|
||||
-- v_ndata32 := 128; -- Time for first pulse
|
||||
v_pulsetime := 128;
|
||||
cpu_print_msg("Load pulse RAM");
|
||||
-- for NADDR in 0 to 255 loop
|
||||
-- -- TODO: In the real setting should we have the python script to check those parameters to make sure they are valid and non-overlapping?
|
||||
-- -- v_pulsetime := v_ndata32 + (NADDR*(1024+32)); -- todo: what is this math doing?
|
||||
|
||||
-- v_timefactor := 1.0;
|
||||
-- v_gainfactor := 1.0;
|
||||
-- v_wavesteps := NADDR;
|
||||
-- v_wavetopwidth := 114;
|
||||
-- v_wavestartaddr := v_wavesteps + v_wavestartaddr; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right?
|
||||
-- v_pulsetime := (v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3 + 1);
|
||||
-- -- cpu_write_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
-- cpu_write_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
-- end loop;
|
||||
----------------------------------------------------------------
|
||||
-- Load pulse RAM with a series of pulse start times MANUALLY
|
||||
---------------------------------------------------------------
|
||||
v_pulseaddr := 0;
|
||||
v_timefactor := 1.0;
|
||||
v_gainfactor := 1.0;
|
||||
v_wavestartaddr := 4; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right?
|
||||
v_wavesteps := 10;
|
||||
v_wavetopwidth := 6;
|
||||
v_pulsetime := 4;
|
||||
cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
|
||||
-- Same pulse but scaled addr
|
||||
v_pulseaddr := 1;
|
||||
v_timefactor := 2.25;
|
||||
v_gainfactor := 1.0;
|
||||
v_wavestartaddr := 4;
|
||||
v_wavesteps := 10;
|
||||
v_wavetopwidth := 9;
|
||||
v_pulsetime := v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3 + 1;
|
||||
cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
|
||||
-- Same pulse but scaled gain
|
||||
v_pulseaddr := 2;
|
||||
v_timefactor := 1.0;
|
||||
v_gainfactor := 0.25;
|
||||
v_wavestartaddr := 4;
|
||||
v_wavesteps := 10;
|
||||
v_wavetopwidth := 0;
|
||||
v_pulsetime := v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3 + 1;
|
||||
cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
|
||||
cpu_print_msg("Pulse RAM loaded");
|
||||
clk_delay(20);
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Load waveform RAM with a simple ramp
|
||||
-- Write two 16-bit values with each write
|
||||
----------------------------------------------------------------
|
||||
cpu_print_msg("Load waveform RAM");
|
||||
v_ndata16 := 1; -- first waveform value
|
||||
|
||||
for NADDR in 0 to 2047 loop
|
||||
uniform(seed1, seed2, x);
|
||||
uniform(seed1, seed2, y);
|
||||
v_ndata32 := ((v_ndata16 * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1)); -- Write two 16-bit values with each write
|
||||
cpu_write(clk, (ADR_RAM_WAVE + NADDR) , v_ndata32, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
v_ndata16 := v_ndata16 + 2;
|
||||
end loop;
|
||||
|
||||
|
||||
-- ----------------------------------------------------------------
|
||||
-- -- Read back Pulse RAM.
|
||||
-- -- Comment out if not needed to check CPU R/W
|
||||
-- ----------------------------------------------------------------
|
||||
-- v_ndata32 := 128; -- Time for first pulse
|
||||
-- for NADDR in 0 to 255 loop
|
||||
-- v_pulsetime := v_ndata32 + (NADDR*(1024+32));
|
||||
-- v_timefactor := 1.0;
|
||||
-- v_gainfactor := 1.0;
|
||||
-- v_wavestartaddr := 0;
|
||||
-- v_wavesteps := NADDR*32;
|
||||
-- v_wavetopwidth := 0;
|
||||
-- cpu_read_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
-- end loop;
|
||||
-- clk_delay(20);
|
||||
|
||||
-- ----------------------------------------------------------------
|
||||
-- -- Read back Waveform RAM
|
||||
-- ----------------------------------------------------------------
|
||||
-- v_ndata16 := 1; -- first waveform value
|
||||
-- for NADDR in 0 to 2047 loop
|
||||
-- v_ndata32 := (((v_ndata16) * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1));
|
||||
-- cpu_read (clk, ADR_RAM_WAVE + NADDR , std_logic_vector(to_unsigned(v_ndata32, 32)) , cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
-- v_ndata16 := v_ndata16 + 2;
|
||||
-- end loop;
|
||||
|
||||
-- -- Done reg write/read check
|
||||
-- cpu_print_msg("RAM readback completed");
|
||||
-- clk_delay(20);
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Start the pulse outputs
|
||||
----------------------------------------------------------------
|
||||
clk_delay(5);
|
||||
start <= '1';
|
||||
clk_delay(5);
|
||||
start <= '0';
|
||||
|
||||
-- TODO: we may need to modify the for loop to make sure the simulation time is long enough to cover all the pulses
|
||||
-- Wait for cnt_time to reach last pulse start time + waveform size
|
||||
for NCNT in 1 to v_pulsetime loop -- TODO: EricToGeoff/Sara: in the real settings do we have a constant amount of time or the total time also vary? if so, how much?
|
||||
-- for NCNT in 1 to 128 loop -- count the time shorter for now so it won't take too long to simulate
|
||||
cnt_time <= std_logic_vector(unsigned(cnt_time) + 1);
|
||||
-- if (NCNT = 32) then -- Stop simulation at some point
|
||||
-- done_seq <= '1';
|
||||
-- end if;
|
||||
clk_delay(0);
|
||||
end loop;
|
||||
|
||||
wait for 10 us;
|
||||
|
||||
cpu_print_msg("Simulation done");
|
||||
clk_delay(5);
|
||||
done_seq <= '1';
|
||||
sim_done <= true;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end behave;
|
||||
|
||||
|
|
@ -1,422 +0,0 @@
|
|||
-----------------------------------------------------------
|
||||
-- File : tb_pulse_channel_random_polynomials.vhd
|
||||
-----------------------------------------------------------
|
||||
--
|
||||
-- More complex testbench for the pulse channel.
|
||||
--
|
||||
-- Description : Generates random polynomials and tests the pulse channel
|
||||
-- Compare the output of the pulse channel with the output of a
|
||||
-- floating-point reference model.
|
||||
--
|
||||
----------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
use std.textio.all;
|
||||
|
||||
use ieee.math_real.all;
|
||||
|
||||
|
||||
use work.std_iopak.all;
|
||||
use work.qlaser_dacs_pulse_channel_pkg.all;
|
||||
|
||||
|
||||
entity tb_pulse_channel_random_polynomials is
|
||||
end tb_pulse_channel_random_polynomials;
|
||||
|
||||
architecture verify of tb_pulse_channel_random_polynomials is
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Pulse Channel DUT signals
|
||||
------------------------------------------------------------------------
|
||||
signal clk : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal enable : std_logic;
|
||||
signal start : std_logic;
|
||||
signal cnt_time : std_logic_vector(23 downto 0);
|
||||
signal busy : std_logic;
|
||||
signal done_seq : std_logic;
|
||||
signal cpu_wr : std_logic;
|
||||
signal cpu_sel : std_logic;
|
||||
signal cpu_addr : std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata : std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata_dv : std_logic;
|
||||
|
||||
-- AXI-stream output interface
|
||||
signal axis_tready : std_logic := '1'; -- Always ready
|
||||
signal axis_tdata : std_logic_vector(15 downto 0);
|
||||
signal axis_tvalid : std_logic;
|
||||
signal axis_tlast : std_logic;
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Simulation signals
|
||||
------------------------------------------------------------------------
|
||||
-- Halts simulation by stopping clock when set true
|
||||
signal sim_done : boolean := false;
|
||||
|
||||
-- Crystal clock freq expressed in MHz
|
||||
constant CLK_FREQ_MHZ : real := 100.0;
|
||||
-- Clock period
|
||||
constant CLK_PER : time := integer(1.0E+6/(CLK_FREQ_MHZ)) * 1 ps;
|
||||
|
||||
-- Block registers
|
||||
constant ADR_RAM_PULSE : integer := 0;
|
||||
constant ADR_RAM_WAVE : integer := 2048;
|
||||
|
||||
signal direction : std_logic := '0';
|
||||
signal degrees : integer := 0;
|
||||
signal times : integer := 0;
|
||||
-- signal wave_values : real_array(0 to degrees-1);
|
||||
signal wave_values : real;
|
||||
signal wave_values_next : real;
|
||||
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Delay
|
||||
-------------------------------------------------------------
|
||||
procedure clk_delay(
|
||||
constant nclks : in integer
|
||||
) is
|
||||
begin
|
||||
for I in 0 to nclks loop
|
||||
wait until clk'event and clk ='0';
|
||||
end loop;
|
||||
end;
|
||||
----------------------------------------------------------------
|
||||
-- Print a string with no time or instance path.
|
||||
----------------------------------------------------------------
|
||||
procedure cpu_print_msg(
|
||||
constant msg : in string
|
||||
) is
|
||||
variable line_out : line;
|
||||
begin
|
||||
write(line_out, msg);
|
||||
writeline(output, line_out);
|
||||
end procedure cpu_print_msg;
|
||||
-------------------------------------------------------------
|
||||
-- CPU write procedure. Address in decimal. Data in hex
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant d : in std_logic_vector(31 downto 0);
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
begin
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
cpu_wr <= '1';
|
||||
cpu_addr <= std_logic_vector(to_unsigned(a, 16));
|
||||
cpu_wdata <= std_logic_vector(d);
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '0';
|
||||
cpu_wr <= '0';
|
||||
cpu_addr <= (others=>'0');
|
||||
cpu_wdata <= (others=>'0');
|
||||
wait until clk'event and clk='0';
|
||||
end;
|
||||
-------------------------------------------------------------
|
||||
-- CPU write procedure. Address and Data in decimal
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant d : in integer;
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
begin
|
||||
cpu_write(clk, a , std_logic_vector(to_unsigned(d,32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write pulse definition RAM
|
||||
-- Make fore 32-bit data write
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write_pulsedef(
|
||||
signal clk : in std_logic;
|
||||
|
||||
constant num_entry : in integer;
|
||||
|
||||
-- TODO: Partial ? list of parameters, there could be more if need more features
|
||||
constant pulsetime : in integer; -- Pulse time in clock cycles
|
||||
constant timefactor : in real; -- Fixed point time scale factor
|
||||
constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000"
|
||||
constant wavestartaddr : in integer; -- Start address in waveform RAM
|
||||
constant wavesteps : in integer; -- Number of steps in waveform rise and fall
|
||||
constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall
|
||||
|
||||
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
-- Vectors for converted values
|
||||
variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time
|
||||
variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep
|
||||
variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain
|
||||
variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM
|
||||
variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform
|
||||
begin
|
||||
-- Convert each field into its std_logic_vector equivalent
|
||||
slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24));
|
||||
slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12));
|
||||
slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10));
|
||||
slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17));
|
||||
|
||||
|
||||
--etc, etc.
|
||||
-- 4 writes. (Address is an integer)
|
||||
cpu_write(clk, ADR_RAM_PULSE+num_entry , x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
cpu_write(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"0" & slv_wavesteps & x"0" & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
cpu_write(clk, ADR_RAM_PULSE+(num_entry+2) , slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
cpu_write(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Output comparison
|
||||
-------------------------------------------------------------
|
||||
procedure pulse_check(
|
||||
signal clk : in std_logic;
|
||||
|
||||
-- TODO: should this be real so that it can take the floating point value from the reference model?
|
||||
constant exp_d : in real;
|
||||
|
||||
signal axis_tdata : in std_logic_vector(15 downto 0); -- axi stream output data
|
||||
signal axis_tvalid : in std_logic; -- axi_stream output data valid
|
||||
signal axis_tlast : in std_logic; -- axi_stream output set on last data
|
||||
signal axis_tready : out std_logic -- axi_stream ready from downstream module
|
||||
|
||||
) is
|
||||
variable v_bdone : boolean := false;
|
||||
variable str_out : string(1 to 256);
|
||||
variable diff : integer;
|
||||
begin
|
||||
wait until clk'event and clk='0';
|
||||
-- TODO: determine if we need any additional signals here
|
||||
while (v_bdone = false) loop
|
||||
wait until clk'event and clk='0';
|
||||
if (axis_tvalid = '1') then
|
||||
if (real(to_integer(unsigned(axis_tdata))) /= exp_d) then
|
||||
-- diff := abs(exp_d - real(to_integer(unsigned(axis_tdata))));
|
||||
fprint(str_out, "Read exp: 0x%s actual: 0x%s\n", to_string(exp_d,"%08X"), to_string(to_bitvector(axis_tdata),"%08X"));
|
||||
report str_out severity error;
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
wait until clk'event and clk='0';
|
||||
wait until clk'event and clk='0';
|
||||
end;
|
||||
|
||||
|
||||
-- TODO: Add reference model for pulse channel
|
||||
|
||||
-- TODO: write polynomial generator/solver
|
||||
-------------------------------------------------------------
|
||||
-- Polynomial Solver
|
||||
-- Given a set of random coefficients and time stamps, output values for the polynomial
|
||||
-- Assume the numbers of coefficients is the same as the number of time stamps which is the degrees number
|
||||
-------------------------------------------------------------
|
||||
-- procedure poly_gen(
|
||||
-- signal clk : in std_logic;
|
||||
|
||||
-- constant degrees : in integer; -- number of coefficients
|
||||
-- signal direction : in std_logic; -- 0 = rising, 1 = falling
|
||||
-- constant times : in integer; -- time stamp
|
||||
-- constant coeff : in real -- coefficient
|
||||
|
||||
-- -- signal coeffs : real_array(0 to degrees-1);
|
||||
-- ) is
|
||||
-- variable poly_sum : real := 0.0;
|
||||
-- begin
|
||||
-- -- wait until clk'event and clk='0';
|
||||
-- -- for i in 0 to degrees loop
|
||||
-- -- poly_sum := poly_sum + coeffs(i) * times**i;
|
||||
-- -- end loop;
|
||||
-- -- poly_out <= poly_sum;
|
||||
-- end;
|
||||
|
||||
procedure poly_gen(
|
||||
signal clk : in std_logic;
|
||||
signal direction : in std_logic; -- 0 = rising, 1 = falling
|
||||
constant degrees : in integer; -- number of coefficients
|
||||
constant times : in integer; -- time stamp (should be real?)
|
||||
constant coeff : in real_array; -- coefficient
|
||||
constant offset : in real; -- offset, or the constant C in the polynomial. This value should be 0.0 for the first term
|
||||
signal wave_values : out real
|
||||
) is
|
||||
variable poly_sum : real := 0.0;
|
||||
variable time_prime : real := real(times) / 4096.0; -- x' = x/4096
|
||||
begin
|
||||
wait until rising_edge(clk);
|
||||
-- add from first to the Nth term. We always assume the zeroth term is 0
|
||||
for i in 1 to degrees loop
|
||||
-- poly_sum := poly_sum + coeff(i - 1)*real(times)**i;
|
||||
poly_sum := poly_sum + coeff(i - 1)*time_prime**i;
|
||||
end loop;
|
||||
-- wave_values <= poly_sum;
|
||||
-- wave_values <= ((coeff(2)*real(times**2) + coeff(1)*real(times))/(real(degrees-1))) * real(2**16); -- for smaller test
|
||||
wave_values <= ((poly_sum)/(real(degrees-1))) * real(2**16) + offset; -- out = (f{x'} / (N-1)) * ADC height
|
||||
|
||||
-- wave_values <= SIN(real(times)); -- possible to use sine wave for testing
|
||||
end;
|
||||
|
||||
begin
|
||||
-------------------------------------------------------------
|
||||
-- Unit Under Test
|
||||
-------------------------------------------------------------
|
||||
u_dac_pulse : entity work.qlaser_dacs_pulse_channel
|
||||
port map (
|
||||
clk => clk , -- in std_logic;
|
||||
reset => reset , -- in std_logic;
|
||||
|
||||
enable => enable , -- out std_logic;
|
||||
start => start , -- out std_logic;
|
||||
cnt_time => cnt_time , -- out std_logic_vector(23 downto 0); -- Set to '1' while SPI interface is busy
|
||||
|
||||
busy => busy , -- out std_logic; -- Set to '1' while SPI interface is busy
|
||||
done_seq => done_seq , -- in std_logic; -- Set to '1' when SPI sequence is done
|
||||
|
||||
-- CPU interface
|
||||
cpu_wr => cpu_wr , -- in std_logic;
|
||||
cpu_sel => cpu_sel , -- in std_logic;
|
||||
cpu_addr => cpu_addr(11 downto 0) , -- in std_logic_vector(11 downto 0);
|
||||
cpu_wdata => cpu_wdata , -- in std_logic_vector(31 downto 0);
|
||||
|
||||
cpu_rdata => cpu_rdata , -- out std_logic_vector(31 downto 0);
|
||||
cpu_rdata_dv => cpu_rdata_dv , -- out std_logic;
|
||||
|
||||
|
||||
-- AXI-Stream interface
|
||||
axis_tready => axis_tready , -- in std_logic; -- Clock (50 MHz max)
|
||||
axis_tdata => axis_tdata , -- out std_logic_vector(15 downto 0);
|
||||
axis_tvalid => axis_tvalid , -- out std_logic; -- Master out, Slave in. (Data to DAC)
|
||||
axis_tlast => axis_tlast -- out std_logic; -- Active low chip select (sync_n)
|
||||
);
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Generate system clock. Halt when sim_done is true.
|
||||
-------------------------------------------------------------
|
||||
pr_clk : process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for (CLK_PER/2);
|
||||
clk <= '1';
|
||||
wait for (CLK_PER-CLK_PER/2);
|
||||
if (sim_done=true) then
|
||||
wait;
|
||||
end if;
|
||||
end process;
|
||||
-------------------------------------------------------------
|
||||
-- Reset and drive CPU bus
|
||||
-------------------------------------------------------------
|
||||
pr_main : process
|
||||
-- Write to files
|
||||
file f_out : text open write_mode is "wave_values.txt";
|
||||
variable line_var : line;
|
||||
|
||||
-- "global" variables for base definitions of each pulses, all pulses are based on these but scaled/offset a bit
|
||||
variable v_pulseaddr : integer := 0; -- manually set the pulse address, 0 to 255
|
||||
variable v_waveaddr : integer := 0; -- manually set the wave address, 0 to 2047
|
||||
variable v_pulsetime : integer := 0; -- For 24-bit pulse time
|
||||
variable v_timefactor : real := 0.0; -- For 16-bit fixed point timestep
|
||||
variable v_gainfactor : real := 0.0; -- For 16-bit fixed point gain
|
||||
variable v_wavestartaddr : integer := 0; -- For 12-bit address i.e. 1024 point waveform RAM
|
||||
variable v_wavesteps : integer := 0; -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable v_wavetopwidth : integer := 0; -- For 17-bit number of clock cycles in top of waveform
|
||||
|
||||
-- for RNG's
|
||||
variable seed1 : positive;
|
||||
variable seed2 : positive;
|
||||
variable x : real;
|
||||
variable y : real;
|
||||
|
||||
variable offset : real;
|
||||
variable v_coeffs : real_array(0 to 4095);
|
||||
|
||||
begin
|
||||
-- Reset
|
||||
reset <= '1';
|
||||
enable <= '0';
|
||||
start <= '0';
|
||||
done_seq <= '0';
|
||||
cnt_time <= (others=>'0');
|
||||
|
||||
cpu_sel <= '0';
|
||||
cpu_wr <= '0';
|
||||
cpu_wdata <= (others=>'0');
|
||||
cpu_addr <= (others=>'0');
|
||||
|
||||
wave_values <= 0.0;
|
||||
wave_values_next <= 0.0;
|
||||
|
||||
cpu_print_msg("Simulation start");
|
||||
clk_delay(5);
|
||||
reset <= '0';
|
||||
|
||||
clk_delay(5);
|
||||
enable <= '1';
|
||||
|
||||
clk_delay(20);
|
||||
|
||||
v_coeffs := (others => 0.0);
|
||||
seed1 := 2045;
|
||||
seed2 := 1024;
|
||||
-- TODO: write to the pulse definition RAM
|
||||
degrees <= 2;
|
||||
-- construct an array contains random coefficients
|
||||
for i in 0 to 4095 loop
|
||||
uniform(seed1, seed2, x);
|
||||
v_coeffs(i) := x;
|
||||
end loop;
|
||||
|
||||
offset := 0.0;
|
||||
for i in 0 to 2047 loop
|
||||
times <= i;
|
||||
poly_gen(clk, direction, degrees, times, v_coeffs, offset, wave_values);
|
||||
|
||||
write(line_var, real'image(wave_values));
|
||||
writeline(f_out, line_var);
|
||||
end loop;
|
||||
|
||||
degrees <= 3;
|
||||
clk_delay(1);
|
||||
poly_gen(clk, direction, degrees, times + 1, v_coeffs, offset, wave_values_next);
|
||||
clk_delay(1);
|
||||
-- -- construct an array contains random coefficients
|
||||
-- for i in 0 to degrees loop
|
||||
-- uniform(seed1, seed2, x);
|
||||
-- v_coeffs(i) := x;
|
||||
-- end loop;
|
||||
|
||||
offset := wave_values - wave_values_next; -- offset is the difference between the last two values
|
||||
|
||||
for i in 2048 to 4095 loop
|
||||
times <= i;
|
||||
poly_gen(clk, direction, degrees, times, v_coeffs, offset, wave_values);
|
||||
|
||||
write(line_var, real'image(wave_values));
|
||||
writeline(f_out, line_var);
|
||||
end loop;
|
||||
|
||||
-- End of test
|
||||
cpu_print_msg("Simulation done");
|
||||
clk_delay(5);
|
||||
done_seq <= '1';
|
||||
sim_done <= true;
|
||||
wait;
|
||||
end process;
|
||||
end verify;
|
||||
|
|
@ -1,26 +0,0 @@
|
|||
import matplotlib.pyplot as plt
|
||||
import numpy as np
|
||||
|
||||
def generate_wave(length=100, amplitude=1, num_waves=3):
|
||||
x = np.linspace(0, 10, length) # Create a linearly spaced array
|
||||
wave = np.zeros(length) # Initialize wave array
|
||||
|
||||
for _ in range(num_waves):
|
||||
phase = np.random.rand() * 2 * np.pi # Random phase
|
||||
frequency = np.random.rand() * 2 # Random frequency
|
||||
amplitude = np.random.rand() * amplitude # Random amplitude
|
||||
|
||||
wave += amplitude * np.sin(2 * np.pi * frequency * x + phase) # Add random sine wave
|
||||
|
||||
return wave
|
||||
|
||||
def plot_wave(wave):
|
||||
plt.plot(wave)
|
||||
plt.xlabel('Time')
|
||||
plt.ylabel('Amplitude')
|
||||
plt.title('Randomly Generated Wave')
|
||||
plt.show()
|
||||
|
||||
if __name__ == "__main__":
|
||||
wave = generate_wave()
|
||||
plot_wave(wave)
|
||||
|
|
@ -1,48 +0,0 @@
|
|||
import matplotlib
|
||||
import matplotlib.pyplot as plt
|
||||
import numpy as np
|
||||
matplotlib.use("WXAgg") # force use wxPython as backend UI for plotting
|
||||
|
||||
def generate_polynomial(coefficients, times, degree):
|
||||
"""Generate polynomial values.
|
||||
|
||||
Args:
|
||||
coefficients (list): List of coefficients for the polynomial, from highest degree to constant term.
|
||||
times (list): List of x-values at which to evaluate the polynomial.
|
||||
degree (int): Degree of the polynomial (not used in computation but included for clarity).
|
||||
|
||||
Returns:
|
||||
list: Polynomial values at the given times.
|
||||
"""
|
||||
|
||||
# Calculate polynomial value for each time
|
||||
polynomial_values = []
|
||||
for t in times:
|
||||
value = 0
|
||||
for i, coeff in enumerate(coefficients):
|
||||
value += coeff * (t ** (degree - i))
|
||||
polynomial_values.append(value)
|
||||
|
||||
return polynomial_values
|
||||
|
||||
|
||||
def plot_wave(wave):
|
||||
plt.plot(wave)
|
||||
plt.xlabel('Time')
|
||||
plt.ylabel('Amplitude')
|
||||
plt.title('Randomly Generated Wave')
|
||||
plt.show()
|
||||
|
||||
|
||||
wavesize = 10
|
||||
|
||||
inputData = np.random.rand(wavesize)*10
|
||||
|
||||
times = np.arange(0, wavesize, 1)
|
||||
|
||||
degree = 3
|
||||
|
||||
|
||||
|
||||
# plot_wave(inputData)
|
||||
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
# simple calculation of the scale factor
|
||||
import numpy as np
|
||||
|
||||
START = 1
|
||||
LENGTH = 10
|
||||
FACTOR = 2.25
|
||||
|
||||
END = START+LENGTH
|
||||
addr_raw = np.arange(START, END)
|
||||
|
||||
addr_scaled = np.zeros(len(addr_raw))
|
||||
|
||||
addr = START
|
||||
|
||||
# for i in range(len(addr_raw)):
|
||||
# addr_scaled[i] = addr_raw[i] * FACTOR
|
||||
|
||||
# print(np.floor(addr_scaled))
|
||||
|
||||
for i in range(LENGTH):
|
||||
print(i * FACTOR, end=" ")
|
||||
# addr_scaled[i] = (addr + i) * FACTOR
|
||||
# addr += 1
|
||||
|
||||
print()
|
||||
|
||||
# now decrement it back
|
||||
for i in range(LENGTH - 1, 0, -1):
|
||||
# addr -= 1
|
||||
# addr_scaled[i] = (addr - i) * FACTOR
|
||||
print(i * FACTOR, end=" ")
|
||||
|
||||
|
||||
print()
|
||||
|
|
@ -1,530 +0,0 @@
|
|||
---------------------------------------------------------------
|
||||
-- File : qlaser_dacs_pulse_channel.vhd
|
||||
-- Description : Single channel of pulse output
|
||||
----------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.qlaser_pkg.all;
|
||||
use work.qlaser_dacs_pulse_channel_pkg.all;
|
||||
|
||||
entity qlaser_dacs_pulse_channel is
|
||||
port (
|
||||
reset : in std_logic;
|
||||
clk : in std_logic;
|
||||
|
||||
enable : in std_logic; -- Set when DAC interface is running
|
||||
start : in std_logic; -- Set when pulse generation sequence begins (trigger)
|
||||
cnt_time : in std_logic_vector(23 downto 0); -- Time since trigger.
|
||||
|
||||
busy : out std_logic; -- Status signal
|
||||
|
||||
-- CPU interface
|
||||
cpu_addr : in std_logic_vector(11 downto 0); -- Address input
|
||||
cpu_wdata : in std_logic_vector(31 downto 0); -- Data input
|
||||
cpu_wr : in std_logic; -- Write enable
|
||||
cpu_sel : in std_logic; -- Block select
|
||||
cpu_rdata : out std_logic_vector(31 downto 0); -- Data output
|
||||
cpu_rdata_dv : out std_logic; -- Acknowledge output
|
||||
|
||||
-- AXI-stream output
|
||||
axis_tready : in std_logic; -- axi_stream ready from downstream module
|
||||
axis_tdata : out std_logic_vector(15 downto 0); -- axi stream output data
|
||||
axis_tvalid : out std_logic; -- axi_stream output data valid
|
||||
axis_tlast : out std_logic -- axi_stream output set on last data
|
||||
);
|
||||
end entity;
|
||||
|
||||
---------------------------------------------------------------------------
|
||||
-- Single channel pulse generator with two RAMs
|
||||
---------------------------------------------------------------------------
|
||||
architecture channel of qlaser_dacs_pulse_channel is
|
||||
-- Signal declarations for pulse RAM
|
||||
signal ram_pulse_we : std_logic_vector( 0 downto 0); -- Write enable for pulse RAM
|
||||
signal ram_pulse_addra : std_logic_vector( 9 downto 0); -- Address for pulse RAM
|
||||
signal ram_pulse_dina : std_logic_vector(31 downto 0); -- Data for pulse RAM
|
||||
signal ram_pulse_douta : std_logic_vector(31 downto 0); -- Data out from pulse RAM
|
||||
signal ram_pulse_addrb : std_logic_vector( 9 downto 0); -- Address for pulse RAM
|
||||
signal ram_pulse_doutb : std_logic_vector(31 downto 0); -- Data out from pulse RAM
|
||||
|
||||
-- Signal declarations for waveform RAM
|
||||
signal ram_waveform_wea : std_logic_vector( 0 downto 0); -- Write enable for waveform RAM
|
||||
signal ram_waveform_addra : std_logic_vector(10 downto 0); -- Address for waveform RAM
|
||||
signal ram_waveform_dina : std_logic_vector(31 downto 0); -- Data for waveform RAM
|
||||
signal ram_waveform_douta : std_logic_vector(31 downto 0); -- Data out from waveform RAM
|
||||
signal ram_waveform_addrb : std_logic_vector(11 downto 0); -- Address for waveform RAM
|
||||
signal ram_waveform_doutb : std_logic_vector(15 downto 0); -- Data out from waveform RAM
|
||||
|
||||
-- State variable type declaration for main state machine
|
||||
-- TODO: add a fetch state to get four address from pd ram?
|
||||
type t_sm_state is (
|
||||
S_RESET, -- Wait for 'enable'. Stay here until JESD interface is up and running,
|
||||
S_IDLE, -- Wait for 'start'
|
||||
S_WAIT, -- Wait for cnt_time, external input, to match pulse position RAM output
|
||||
S_LOAD, -- Load the pulse channel RAM addresses and start the waveform output
|
||||
S_HOLD, -- Hold the last pulse definition address and output its data
|
||||
S_WAVE_UP, -- Output the rising edge of a waveform
|
||||
S_WAVE_FLAT,-- Output the flat top part of a waveform
|
||||
S_WAVE_DOWN -- Output the falling edge of a waveform
|
||||
);
|
||||
signal sm_state : t_sm_state;
|
||||
signal sm_wavedata : std_logic_vector(15 downto 0); -- Waveform RAM data
|
||||
signal sm_wavedata_dv : std_logic; -- Signal to indicate that waveform RAM data is valid
|
||||
signal sm_busy : std_logic; -- Signal to indicate that s.m. is not idle
|
||||
signal cnt_wave_len : unsigned(C_BITS_ADDR_LENGTH - 1 downto 0); -- Counter used for incremnet/decrement wave table addresses
|
||||
signal cnt_wave_top : unsigned(C_BITS_ADDR_TOP - 1 downto 0); -- Counter for the flat top of the waveform
|
||||
|
||||
-- Misc signals
|
||||
signal cpu_rdata_dv_e1 : std_logic;
|
||||
signal cpu_rdata_dv_e2 : std_logic;
|
||||
signal cpu_rdata_ramsel_d1 : std_logic;
|
||||
signal cpu_rdata_ramsel_d2 : std_logic;
|
||||
|
||||
signal pc : std_logic_vector(C_BITS_ADDR_PULSE - 1 downto 0); -- pulse counter, used to count the number of pulses generated
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Assign values from the pulse definition ram to regfiles (?) with the following:
|
||||
-- 1. Start time 24 bits. [23:0]
|
||||
-- 2. Wave start addr 12 bit at [11:0]
|
||||
-- Wave length 10-bit at [25:16]
|
||||
-- 3. Scale factors 16, 16. [31:16] [15:0]
|
||||
-- 4. Flat-top 17-bit. [16:0]
|
||||
----------------------------------------------------------------
|
||||
signal reg_start_time : std_logic_vector(23 downto 0); -- first register which stores the pulse's start time
|
||||
signal reg_pulse_sizes : std_logic_vector(31 downto 0); -- second register which stores the pulse's length, the bit width should increase with the amount of addresses the wavetable has, and its start address
|
||||
-- TODO: replace the above one w/ below two
|
||||
signal reg_wave_start_addr : std_logic_vector(11 downto 0); -- the start address of the wavetable
|
||||
signal reg_wave_length : unsigned(9 downto 0); -- the length of the wavetable
|
||||
|
||||
signal reg_pulse_factors : std_logic_vector(31 downto 0); -- third register which stores the pulse's amplitude and time scale factors
|
||||
-- TODO: replace the above one w/ below two
|
||||
signal reg_scale_gain : unsigned(15 downto 0); -- scale factor for the gain, amplitude
|
||||
signal reg_scale_time : unsigned(15 downto 0); -- scale factor for the time, length
|
||||
|
||||
signal reg_flattop : std_logic_vector(16 downto 0); -- fourth register which stores the pulse's flat top value
|
||||
|
||||
|
||||
|
||||
-- Pipeline delays
|
||||
signal start_d1 : std_logic;
|
||||
signal enable_d1 : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Pulse Definition Block RAM.
|
||||
-- Synch write, Synch read
|
||||
-- Port A is for CPU read/write. 1024x32-bit
|
||||
-- Port B is for pulse time data output. 1024x32-bit
|
||||
----------------------------------------------------------------
|
||||
u_ram_pulse : entity work.bram_pulse_definition
|
||||
port map(
|
||||
-- Port A CPU Bus
|
||||
clka => clk, -- input std_logic
|
||||
wea => ram_pulse_we, -- input slv( 0 to 0 )
|
||||
addra => ram_pulse_addra, -- input slv( 9 downto 0 )
|
||||
dina => ram_pulse_dina, -- input slv( 31 downto 0 )
|
||||
douta => ram_pulse_douta, -- output slv( 31 downto 0 ),
|
||||
-- Port B waveform input
|
||||
clkb => clk,
|
||||
web => (others=>'0'),
|
||||
addrb => ram_pulse_addrb, -- input slv( 9 downto 0 )
|
||||
dinb => (others=>'0'),
|
||||
doutb => ram_pulse_doutb -- output slv( 31 downto 0 )
|
||||
);
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Waveform table Block RAM.
|
||||
-- Synch write, Synch read
|
||||
-- Port A is for CPU read/write. 2048x32-bit
|
||||
-- Port B is for waveform data. 4096x16-bit
|
||||
----------------------------------------------------------------
|
||||
u_ram_waveform : entity work.bram_waveform
|
||||
port map (
|
||||
-- Port A CPU Bus
|
||||
clka => clk , -- input std_logic
|
||||
wea => ram_waveform_wea , -- input slv(0 downto 0)
|
||||
addra => ram_waveform_addra , -- input slv(10 downto 0)
|
||||
dina => ram_waveform_dina , -- input slv(31 downto 0)
|
||||
douta => ram_waveform_douta , -- output slv(31 downto 0)
|
||||
|
||||
-- Port B waveform output
|
||||
clkb => clk , -- input std_logic
|
||||
web => (others=>'0') , -- input slv(0 downto 0)
|
||||
addrb => ram_waveform_addrb , -- input slv(11 downto 0)
|
||||
dinb => (others=>'0') , -- input slv(15 downto 0)
|
||||
doutb => ram_waveform_doutb -- output slv(15 downto 0)
|
||||
);
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- CPU Read/Write RAM
|
||||
-- MSB of cpu_addr is used to select one of the two RAMs
|
||||
-- to read/write, and the remainder are a 9-bit or 4-bit RAM address.
|
||||
----------------------------------------------------------------
|
||||
pr_ram_rw : process (reset, clk)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
|
||||
ram_pulse_addra <= (others=>'0');
|
||||
ram_pulse_dina <= (others=>'0');
|
||||
ram_pulse_we <= (others=>'0');
|
||||
|
||||
ram_waveform_wea <= (others=>'0');
|
||||
ram_waveform_addra <= (others=>'0');
|
||||
ram_waveform_dina <= (others=>'0');
|
||||
|
||||
cpu_rdata <= (others=>'0');
|
||||
cpu_rdata_dv <= '0';
|
||||
cpu_rdata_dv_e1 <= '0';
|
||||
cpu_rdata_dv_e2 <= '0';
|
||||
cpu_rdata_ramsel_d1 <= '0';
|
||||
cpu_rdata_ramsel_d2 <= '0';
|
||||
|
||||
elsif rising_edge(clk) then
|
||||
|
||||
|
||||
-------------------------------------------------
|
||||
-- CPU writing RAM
|
||||
-------------------------------------------------
|
||||
if (cpu_wr = '1') and (cpu_sel = '1') then
|
||||
|
||||
-- 0 for pulse definition, 1 for waveform table
|
||||
if (cpu_addr(C_RAM_SELECT) = '1') then
|
||||
|
||||
ram_pulse_addra <= (others=>'0');
|
||||
ram_pulse_dina <= (others=>'0');
|
||||
ram_pulse_we <= (others=>'0');
|
||||
|
||||
ram_waveform_wea(0) <= '1';
|
||||
ram_waveform_addra <= cpu_addr(10 downto 0);
|
||||
ram_waveform_dina <= cpu_wdata;
|
||||
|
||||
else
|
||||
|
||||
ram_pulse_addra <= cpu_addr(9 downto 0);
|
||||
ram_pulse_dina <= cpu_wdata;
|
||||
ram_pulse_we(0) <= '1';
|
||||
ram_waveform_wea <= (others=>'0');
|
||||
ram_waveform_addra <= (others=>'0');
|
||||
ram_waveform_dina <= (others=>'0');
|
||||
|
||||
end if;
|
||||
|
||||
cpu_rdata_dv_e1 <= '0';
|
||||
cpu_rdata_dv_e2 <= '0';
|
||||
cpu_rdata_ramsel_d1 <= '0';
|
||||
cpu_rdata_ramsel_d2 <= '0';
|
||||
|
||||
|
||||
-------------------------------------------------
|
||||
-- CPU read
|
||||
-------------------------------------------------
|
||||
elsif (cpu_wr = '0') and (cpu_sel = '1') then
|
||||
|
||||
if (cpu_addr(C_RAM_SELECT) = '1') then -- Waveform
|
||||
ram_pulse_addra <= (others=>'0');
|
||||
ram_waveform_addra <= cpu_addr(10 downto 0);
|
||||
else -- Pulse
|
||||
ram_pulse_addra <= cpu_addr(9 downto 0);
|
||||
ram_waveform_addra <= (others=>'0');
|
||||
end if;
|
||||
|
||||
ram_pulse_we <= (others=>'0');
|
||||
ram_waveform_wea(0) <= '0';
|
||||
|
||||
cpu_rdata_dv_e2 <= '1'; -- DV for cycle, when RAM output occurs
|
||||
cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
|
||||
cpu_rdata_ramsel_d1 <= cpu_addr(C_RAM_SELECT); -- Save the select bit one cycle later
|
||||
cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1;
|
||||
|
||||
else
|
||||
ram_pulse_addra <= (others=>'0');
|
||||
ram_pulse_we <= (others=>'0');
|
||||
ram_waveform_addra <= (others=>'0');
|
||||
ram_waveform_wea(0) <= '0';
|
||||
|
||||
cpu_rdata_dv_e2 <= '0';
|
||||
cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
|
||||
cpu_rdata_ramsel_d1 <= '0';
|
||||
cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1;
|
||||
|
||||
end if;
|
||||
|
||||
-------------------------------------------------
|
||||
-- Output the delayed RAM data
|
||||
-- This adds a pipeline delay to the cpu_rdata_dv to account for
|
||||
-- the delay in reading data from the RAM
|
||||
-------------------------------------------------
|
||||
if (cpu_rdata_dv_e1 = '1') then
|
||||
|
||||
cpu_rdata_dv <= '1';
|
||||
|
||||
-- Select source of output data
|
||||
if (cpu_rdata_ramsel_d2 = '1') then -- Output is from waveform table
|
||||
cpu_rdata <= ram_waveform_douta;
|
||||
|
||||
elsif (cpu_rdata_ramsel_d2 = '0') then
|
||||
cpu_rdata <= ram_pulse_douta;
|
||||
end if;
|
||||
|
||||
else
|
||||
cpu_rdata <= (others=>'0');
|
||||
cpu_rdata_dv <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- State machine:
|
||||
-- Compares cnt_time input against current output from pulse position RAM.
|
||||
-- When values match iti incremnts the pulse postion RAM address to
|
||||
-- retrieve the next pulse position and also starts reading the
|
||||
-- entire waveform table, one value every clock cycle, until it reaches the end.
|
||||
-- Once the pulse is complete it waits for the next cnt_time match.
|
||||
-- Repeat until all pulse position RAM times have triggered a pulse output
|
||||
-- or until the maximum counter time has been reached.
|
||||
----------------------------------------------------------------
|
||||
pr_sm : process (reset, clk)
|
||||
variable v_amp_factor : std_logic_vector(C_BITS_GAIN_FACTOR - 1 downto 0);
|
||||
variable v_time_factor : std_logic_vector(C_BITS_TIME_FACTOR - 1 downto 0);
|
||||
|
||||
-- Temp variables for waveform output
|
||||
variable v_ram_waveform_doutb_multiplied : std_logic_vector(C_BITS_GAIN_FACTOR + 15 downto 0);
|
||||
begin
|
||||
if (reset = '1') then
|
||||
|
||||
sm_state <= S_IDLE; -- TODO: Eric: Should this be S_RESET since we reset the JEDS interface as well?
|
||||
ram_pulse_addrb <= (others=>'0');
|
||||
ram_waveform_addrb <= (others=>'0');
|
||||
|
||||
sm_wavedata <= (others=>'0');
|
||||
sm_wavedata_dv <= '0';
|
||||
sm_busy <= '0';
|
||||
|
||||
reg_start_time <= (others=>'0');
|
||||
reg_pulse_sizes <= (others=>'0');
|
||||
reg_pulse_factors <= (others=>'0');
|
||||
reg_flattop <= (others=>'0');
|
||||
reg_scale_gain <= (others=>'0');
|
||||
reg_scale_time <= (others=>'0');
|
||||
|
||||
pc <= (others=>'0');
|
||||
cnt_wave_len <= (others=>'0');
|
||||
cnt_wave_top <= (others=>'0');
|
||||
elsif rising_edge(clk) then
|
||||
|
||||
|
||||
-- Pipeline delays to use for rising edge detection
|
||||
enable_d1 <= enable;
|
||||
start_d1 <= start;
|
||||
|
||||
-- Default
|
||||
sm_wavedata <= (others=>'0');
|
||||
sm_wavedata_dv <= '0';
|
||||
|
||||
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Main state machine
|
||||
------------------------------------------------------------------------
|
||||
case sm_state is
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Wait for rising edge of enable
|
||||
-- This is set when the JESD interface is aligned and functional.
|
||||
-- Send a zero value to initialize the DAC then go to idle.
|
||||
------------------------------------------------------------------------
|
||||
when S_RESET =>
|
||||
|
||||
if (enable = '1') and (enable_d1 = '0') then
|
||||
sm_wavedata <= (others=>'0');
|
||||
sm_wavedata_dv <= '1';
|
||||
sm_state <= S_IDLE;
|
||||
end if;
|
||||
sm_busy <= '0';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Wait for rising edge of 'start'.
|
||||
-- No data output.
|
||||
------------------------------------------------------------------------
|
||||
when S_IDLE =>
|
||||
|
||||
if (start = '1') and (start_d1 = '0') then
|
||||
sm_state <= S_LOAD;
|
||||
sm_busy <= '1';
|
||||
else
|
||||
sm_busy <= '0';
|
||||
end if;
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Load four addresses from pulse definition RAM into four 32 bits regesters
|
||||
------------------------------------------------------------------------
|
||||
when S_LOAD =>
|
||||
-- TODO: Eric: does is needed here? or should be inside the if-else loops
|
||||
-- Load the pulse channel RAM addresses and start the waveform output
|
||||
sm_busy <= '1';
|
||||
-- Pipline the pulse definition address
|
||||
|
||||
-- TODO: is it better to make a counter to count the quarter or just mod 4?
|
||||
-- TODO: maybe C-slow around the pulse ram to get it down to 1 cycle??
|
||||
if (unsigned(ram_pulse_addrb) mod 4 = 0) then
|
||||
ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 1);
|
||||
sm_state <= S_LOAD;
|
||||
-- first quarter of the pulse definition, no register is loaded
|
||||
-- reg_start_time <= ram_pulse_doutb;
|
||||
|
||||
elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then
|
||||
ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 2);
|
||||
sm_state <= S_LOAD;
|
||||
-- reg_pulse_sizes <= ram_pulse_doutb;
|
||||
-- second quarter of the pulse definition, the start time is loaded
|
||||
reg_start_time <= ram_pulse_doutb;
|
||||
|
||||
|
||||
elsif (unsigned(ram_pulse_addrb) mod 4 = 2) then
|
||||
ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 3);
|
||||
sm_state <= S_LOAD;
|
||||
-- reg_pulse_factors <= ram_pulse_doutb;
|
||||
-- third quarter of the pulse definition, the length and start address of the wavetable are loaded
|
||||
reg_pulse_sizes <= ram_pulse_doutb;
|
||||
|
||||
|
||||
elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then
|
||||
-- ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 4);
|
||||
sm_state <= S_WAIT; -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state
|
||||
-- hold the last pulse definition address as it will be used in the next state
|
||||
-- reg_flattop <= ram_pulse_doutb;
|
||||
pc <= std_logic_vector(unsigned(pc) + C_PC_INCR); -- incremnet the pulse counter and start waiting to output the wave
|
||||
-- forth quarter of the pulse definition, the scale factors are loaded
|
||||
reg_pulse_factors <= ram_pulse_doutb;
|
||||
|
||||
reg_scale_gain <= unsigned(ram_pulse_doutb(31 downto 16));
|
||||
reg_scale_time <= unsigned(ram_pulse_doutb(15 downto 0));
|
||||
|
||||
|
||||
end if;
|
||||
|
||||
-- ------------------------------------------------------------------------
|
||||
-- -- Hold the last pulse definition address and output its data for one more clock cycle
|
||||
-- ------------------------------------------------------------------------
|
||||
-- when S_HOLD =>
|
||||
-- sm_state <= S_LOAD;
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Wait for cnt_time, external input, to match pulse position RAM output
|
||||
-- Return to idle state if max time is reached. Output waveform value zero.
|
||||
------------------------------------------------------------------------
|
||||
when S_WAIT =>
|
||||
-- read the last word of the pulse definition, the flat top value
|
||||
reg_flattop <= ram_pulse_doutb;
|
||||
-- Start to output wave and increment pulse position RAM address
|
||||
if (reg_start_time(C_START_TIME - 1 downto 0) = cnt_time) then
|
||||
sm_state <= S_WAVE_UP;
|
||||
-- set the wavetable's address to the starting address defined from the pulse ram
|
||||
ram_waveform_addrb <= reg_pulse_sizes(C_BITS_ADDR_START - 1 downto 0);
|
||||
-- reset the wave lenth counter
|
||||
cnt_wave_len <= (others=>'0');
|
||||
-- parse the scale factors from reg_pulse_factors register
|
||||
v_time_factor := reg_pulse_factors(C_BITS_TIME_FACTOR - 1 downto 0);
|
||||
v_amp_factor := reg_pulse_factors(31 downto 16);
|
||||
elsif (cnt_time = X"FFFFFF") then
|
||||
sm_state <= S_IDLE;
|
||||
end if;
|
||||
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Output the raising edge of a waveform
|
||||
-- Hold the last address when complete
|
||||
------------------------------------------------------------------------
|
||||
when S_WAVE_UP =>
|
||||
-- Check if is end of rise of the waveform, and hold the address
|
||||
|
||||
-- TODO: convert the numbers below to constaint. right now just make sure I'm not confused
|
||||
if (cnt_wave_len = reg_wave_length) then
|
||||
sm_state <= S_WAVE_FLAT;
|
||||
-- reset counters for transitions
|
||||
cnt_wave_len <= (others=>'0');
|
||||
cnt_wave_top <= (others=>'0');
|
||||
-- TODO: toSara: do we need to consider the even of no flat top?
|
||||
else
|
||||
cnt_wave_len <= cnt_wave_len + 1;
|
||||
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1);
|
||||
end if;
|
||||
|
||||
v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain);
|
||||
sm_wavedata <= std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain)(31 downto 16);
|
||||
sm_wavedata_dv <= '1';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Hold the last address and output its data
|
||||
-- decrement from this address when finished waiting
|
||||
------------------------------------------------------------------------
|
||||
when S_WAVE_FLAT =>
|
||||
-- count the 17-bit flat top, if the counter reaches the flat top value, then go to the next state
|
||||
if (cnt_wave_top = reg_flattop(C_BITS_ADDR_TOP - 1 downto 0)) then
|
||||
sm_state <= S_WAVE_DOWN;
|
||||
-- reset the counter for the next transition
|
||||
cnt_wave_top <= (others=>'0');
|
||||
else
|
||||
cnt_wave_top <= std_logic_vector(unsigned(cnt_wave_top) + 1);
|
||||
end if;
|
||||
v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * unsigned(v_amp_factor));
|
||||
sm_wavedata <= std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain)(31 downto 16); ;
|
||||
sm_wavedata_dv <= '1';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Output the falling edge of a waveform
|
||||
-- Hold the start address when complete
|
||||
------------------------------------------------------------------------
|
||||
when S_WAVE_DOWN =>
|
||||
|
||||
-- End of waveform?
|
||||
-- TODO: convert the numbers below to constaint. right now just make sure I'm not confused
|
||||
if (cnt_wave_len = reg_wave_length) then
|
||||
|
||||
-- If the end of the pulse table is reached then go to idle, increment pulse address for the next waveform otherwise
|
||||
if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_LEN_PULSE-1, C_BITS_ADDR_PULSE))) then
|
||||
ram_pulse_addrb <= (others=>'0');
|
||||
pc <= (others=>'0');
|
||||
sm_state <= S_IDLE;
|
||||
|
||||
else -- increment pulse address for the next waveform
|
||||
ram_pulse_addrb <= pc;
|
||||
-- the above line will now happen in the load state
|
||||
-- pc <= std_logic_vector(unsigned(pc) + C_PC_INCR);
|
||||
sm_state <= S_LOAD;
|
||||
end if;
|
||||
|
||||
-- Output waveform from RAM with decremented address
|
||||
else
|
||||
cnt_wave_len <= cnt_wave_len + 1;
|
||||
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - 1);
|
||||
end if;
|
||||
sm_wavedata <= std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain)(31 downto 16);
|
||||
sm_wavedata_dv <= '1';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Default
|
||||
------------------------------------------------------------------------
|
||||
when others =>
|
||||
sm_state <= S_IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- AXI-Stream output.
|
||||
-- TBD: This should come from a FIFO
|
||||
-- TODO: the bits are not correct, should be top bits (C_BITS_GAIN_FACTOR + 16 downto C_BITS_GAIN_FACTOR), but for now just make it this way so modelsim can simulate
|
||||
-- TODO: apply scaling factor to the output
|
||||
axis_tdata <= sm_wavedata; -- axi stream output data, this output should be multiplied by the gain factor, then take the top 16 bits
|
||||
axis_tvalid <= sm_wavedata_dv; -- axi_stream output data valid
|
||||
|
||||
-- TBD : Generate in state machine?
|
||||
axis_tlast <= '0'; -- axi_stream output last
|
||||
|
||||
end channel;
|
||||
|
|
@ -1,606 +0,0 @@
|
|||
---------------------------------------------------------------
|
||||
-- File : qlaser_dacs_pulse_channel.vhd
|
||||
-- Description : Single channel of pulse output
|
||||
----------------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
use work.qlaser_pkg.all;
|
||||
|
||||
entity qlaser_dacs_pulse_channel is
|
||||
port (
|
||||
reset : in std_logic;
|
||||
clk : in std_logic;
|
||||
|
||||
enable : in std_logic; -- Set when DAC interface is running
|
||||
start : in std_logic; -- Set when pulse generation sequence begins (trigger)
|
||||
cnt_time : in std_logic_vector(23 downto 0); -- Time since trigger.
|
||||
|
||||
busy : out std_logic; -- Status signal
|
||||
|
||||
-- CPU interface
|
||||
cpu_addr : in std_logic_vector( 9 downto 0); -- Address input
|
||||
cpu_wdata : in std_logic_vector(31 downto 0); -- Data input
|
||||
cpu_wr : in std_logic; -- Write enable
|
||||
cpu_sel : in std_logic; -- Block select
|
||||
cpu_rdata : out std_logic_vector(31 downto 0); -- Data output
|
||||
cpu_rdata_dv : out std_logic; -- Acknowledge output
|
||||
|
||||
-- AXI-stream output
|
||||
axis_tready : in std_logic; -- axi_stream ready from downstream module
|
||||
axis_tdata : out std_logic_vector(15 downto 0); -- axi stream output data
|
||||
axis_tvalid : out std_logic; -- axi_stream output data valid
|
||||
axis_tlast : out std_logic -- axi_stream output set on last data
|
||||
);
|
||||
end entity;
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Single channel pulse generator with two RAMs and a FIFO
|
||||
----------------------------------------------------------------
|
||||
architecture rtl of qlaser_dacs_pulse_channel is
|
||||
|
||||
-- RAM, pulse position, CPU port, read/write
|
||||
constant C_NUM_PULSE : integer := 16; -- Number of output data values from pulse RAM (16x24-bit)
|
||||
signal ram_pulse_addra : std_logic_vector( 3 downto 0); -- 16 entry RAM
|
||||
signal ram_pulse_dina : std_logic_vector(95 downto 0);
|
||||
signal ram_pulse_douta : std_logic_vector(95 downto 0);
|
||||
signal ram_pulse_douta_d1 : std_logic_vector(95 downto 0); -- Delay distrib RAM output to match pipeline of Block RAM
|
||||
signal ram_pulse_we : std_logic;
|
||||
|
||||
-- RAM, pulse position, from state machine
|
||||
constant C_BITS_GAIN_FACTOR : integer := 16; -- Number of bits in gain table
|
||||
constant C_BITS_TIME_FACTOR : integer := 16; -- Number of bits in time table
|
||||
constant C_BITS_TIME_INT : integer := 14; -- Starting bit for time integer part of the time factor, counting from MSB
|
||||
constant C_BITS_TIME_FRAC : integer := 5; -- Starting bit for time fractional part of the time factor, counting from MSB
|
||||
constant C_BITS_ADDR_START : integer := 10; -- Number of bits for starting address
|
||||
constant C_BITS_ADDR_LENGTH : integer := 10; -- Number of bits for length address used by an edge of a pulse
|
||||
constant C_BITS_ADDR_TOP : integer := 17; -- Number of bits for the "flat top", the top of the pulse
|
||||
signal cnt_wave_top : std_logic_vector( C_BITS_ADDR_TOP - 1 downto 0); -- Counter for the top of the waveform
|
||||
signal ram_pulse_addrb : std_logic_vector( 3 downto 0);
|
||||
signal ram_pulse_doutb : std_logic_vector(95 downto 0);
|
||||
|
||||
signal cpu_rdata_dv_e1 : std_logic;
|
||||
signal cpu_rdata_dv_e2 : std_logic;
|
||||
signal cpu_rdata_ramsel_d1 : std_logic;
|
||||
signal cpu_rdata_ramsel_d2 : std_logic;
|
||||
|
||||
signal cpu_wdata_top : std_logic_vector(31 downto 0); -- Top 32 bits of CPU write data (95:64)
|
||||
signal cpu_wdata_mid : std_logic_vector(31 downto 0); -- Middle 32 bits of CPU write data (63:32)
|
||||
|
||||
-- Waveform RAM port connections.
|
||||
-- NOTE: Port A is 32-bit data, port B is 16-bit
|
||||
constant C_LENGTH_WAVEFORM : integer := 1024; -- Number of output data values from waveform RAM (1024x16-bit)
|
||||
constant C_BITS_ADDR_WAVE : integer := 10; -- Number of bits in address for waveform RAM
|
||||
signal ram_waveform_ena : std_logic;
|
||||
signal ram_waveform_wea : std_logic_vector( 0 downto 0);
|
||||
signal ram_waveform_addra : std_logic_vector( 8 downto 0);
|
||||
signal ram_waveform_dina : std_logic_vector(31 downto 0);
|
||||
signal ram_waveform_douta : std_logic_vector(31 downto 0);
|
||||
|
||||
signal ram_waveform_enb : std_logic := '0';
|
||||
signal ram_waveform_web : std_logic_vector( 0 downto 0) := (others=>'0');
|
||||
signal ram_waveform_addrb : std_logic_vector( 9 downto 0);
|
||||
signal ram_waveform_dinb : std_logic_vector(15 downto 0) := (others=>'0');
|
||||
signal ram_waveform_doutb : std_logic_vector(15 downto 0);
|
||||
|
||||
|
||||
-- State variable type declaration for main state machine
|
||||
type t_sm_state is (
|
||||
S_RESET, -- Wait for 'enable'. Stay here until JESD interface is up and running,
|
||||
S_IDLE, -- Wait for 'start'
|
||||
S_WAIT, -- Wait for cnt_time, external input, to match pulse position RAM output
|
||||
S_WAVE_UP, -- Output the rising edge of a waveform
|
||||
S_WAVE_FLAT,-- Output the flat top part of a waveform
|
||||
S_WAVE_DOWN -- Output the falling edge of a waveform
|
||||
);
|
||||
signal sm_state : t_sm_state;
|
||||
signal sm_wavedata : std_logic_vector(15 downto 0); -- Waveform RAM data
|
||||
signal sm_wavedata_dv : std_logic; -- Signal to indicate that waveform RAM data is valid
|
||||
signal sm_busy : std_logic; -- Signal to indicate that s.m. is not idle
|
||||
|
||||
|
||||
---- FIFO port connections
|
||||
--signal fifo_wr_en : std_logic;
|
||||
--signal fifo_full : std_logic;
|
||||
--signal fifo_empty : std_logic;
|
||||
--signal fifo_wr_rst_busy : std_logic;
|
||||
--signal fifo_rd_rst_busy : std_logic;
|
||||
--signal fifo_rd_en : std_logic;
|
||||
---- FIFO status signals for debug purpose
|
||||
--signal fifo_wr_ack : std_logic;
|
||||
--signal fifo_overflow : std_logic;
|
||||
--signal fifo_valid : std_logic;
|
||||
--signal fifo_underflow : std_logic;
|
||||
|
||||
-- Pipeline delays
|
||||
signal start_d1 : std_logic;
|
||||
signal enable_d1 : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
busy <= sm_busy;
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Distributed RAM to hold 16 24-bit Pulse start times.
|
||||
-- Synch write, Asynch read
|
||||
-- Port A is for CPU read/write. 16x24-bit
|
||||
-- Port B is for pulse time data output. 16x24-bit
|
||||
----------------------------------------------------------------
|
||||
u_ram_pulse : entity work.bram_pulseposition
|
||||
port map(
|
||||
clk => clk , -- input std_logic
|
||||
a => ram_pulse_addra , -- input slv[3:0]
|
||||
d => ram_pulse_dina , -- input slv[95 downto 0]
|
||||
we => ram_pulse_we ,
|
||||
spo => ram_pulse_douta , -- output slv(95 downto 0]
|
||||
|
||||
dpra => ram_pulse_addrb , -- input slv[3:0]
|
||||
dpo => ram_pulse_doutb -- output slv(95 downto 0)
|
||||
);
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Waveform table Block RAM.
|
||||
-- Synch write, Synch read
|
||||
-- Port A is for CPU read/write. 512x32-bit
|
||||
-- Port B is for waveform data. 1024x16-bit
|
||||
----------------------------------------------------------------
|
||||
u_ram_waveform : entity work.bram_waveform
|
||||
port map (
|
||||
-- Port A CPU Bus
|
||||
clka => clk , -- input std_logic
|
||||
ena => ram_waveform_ena , -- input std_logic
|
||||
wea => ram_waveform_wea , -- input slv(0 downto 0)
|
||||
addra => ram_waveform_addra , -- input slv(8 downto 0)
|
||||
dina => ram_waveform_dina , -- input slv(31 downto 0)
|
||||
douta => ram_waveform_douta , -- output slv(31 downto 0)
|
||||
|
||||
-- Port B waveform output
|
||||
clkb => clk , -- input std_logic
|
||||
enb => ram_waveform_enb , -- input std_logic
|
||||
web => (others=>'0') , -- input slv(0 downto 0)
|
||||
addrb => ram_waveform_addrb , -- input slv(9 downto 0)
|
||||
dinb => (others=>'0') , -- input slv(15 downto 0)
|
||||
doutb => ram_waveform_doutb -- output slv(15 downto 0)
|
||||
);
|
||||
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- State machine:
|
||||
-- Compares cnt_time input against current output from pulse position RAM.
|
||||
-- When values match iti incremnts the pulse postion RAM address to
|
||||
-- retrieve the next pulse position and also starts reading the
|
||||
-- entire waveform table, one value every clock cycle, until it reaches the end.
|
||||
-- Once the pulse is complete it waits for the next cnt_time match.
|
||||
-- Repeat until all pulse position RAM times have triggered a pulse output
|
||||
-- or until the maximum counter time has been reached.
|
||||
----------------------------------------------------------------
|
||||
pr_sm : process (reset, clk)
|
||||
-- TODO: those bitwidth are not correct, we could optimize it later and find out how many bits each variable should be. But for now just make it big
|
||||
variable v_flattop : std_logic_vector(C_BITS_ADDR_TOP - 1 downto 0); -- wait times (flat_top), managed by an internal counter process sm_top_counter unter state S_WAVE_TOP
|
||||
variable v_addr_length : std_logic_vector(C_BITS_ADDR_LENGTH - 1 downto 0); -- number of points/addresses used by the pulse edge, the bit width should increase with the amount of addresses the wavetable has
|
||||
variable v_addr_start : std_logic_vector(C_BITS_ADDR_START - 1 downto 0); -- start address of the pulse edge data in the Waveform RAM, the bit width should increase with the amount of address the wavetable has.
|
||||
variable v_addr_end : std_logic_vector(C_BITS_ADDR_START - 1 downto 0); -- end address of the pulse edge data in the Waveform RAM, the bit width should align with the bit width of v_addr_start
|
||||
variable v_amplitude_factor : std_logic_vector(C_BITS_GAIN_FACTOR - 1 downto 0); -- pulse edge amplitude scale factor
|
||||
variable v_time_factor : std_logic_vector(C_BITS_TIME_FACTOR - 1 downto 0); -- pulse edge time scale factor
|
||||
variable v_cnt_time : std_logic_vector(23 downto 0); -- counter for the time, the bit width should increase with the amount of addresses the wavetable has
|
||||
|
||||
variable v_ram_waveform_addrb : unsigned(95 downto 0);
|
||||
begin
|
||||
if (reset = '1') then
|
||||
|
||||
sm_state <= S_IDLE; -- TODO: Eric: Should this be S_RESET since we reset the JEDS interface as well?
|
||||
ram_pulse_addrb <= (others=>'0');
|
||||
ram_waveform_addrb <= (others=>'0');
|
||||
|
||||
sm_wavedata <= (others=>'0');
|
||||
sm_wavedata_dv <= '0';
|
||||
sm_busy <= '0';
|
||||
ram_waveform_enb <= '0';
|
||||
|
||||
elsif rising_edge(clk) then
|
||||
|
||||
-- Pipeline delays to use for rising edge detection
|
||||
enable_d1 <= enable;
|
||||
start_d1 <= start;
|
||||
|
||||
-- Default
|
||||
sm_wavedata <= (others=>'0');
|
||||
sm_wavedata_dv <= '0';
|
||||
|
||||
-- Actively read pulse definition RAM and update the variables
|
||||
v_flattop := ram_pulse_doutb(C_BITS_ADDR_TOP - 1 downto 0);
|
||||
v_addr_length := ram_pulse_doutb(C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_ADDR_TOP);
|
||||
v_addr_start := ram_pulse_doutb(C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP);
|
||||
v_addr_end := std_logic_vector(unsigned(v_addr_start) + unsigned(v_addr_length) - 1);
|
||||
v_amplitude_factor := ram_pulse_doutb(C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP);
|
||||
v_time_factor := ram_pulse_doutb(C_BITS_TIME_FACTOR + C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP);
|
||||
v_cnt_time := ram_pulse_doutb(24 + C_BITS_TIME_FACTOR + C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_TIME_FACTOR + C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP);
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Main state machine
|
||||
------------------------------------------------------------------------
|
||||
case sm_state is
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Wait for rising edge of enable
|
||||
-- This is set when the JESD interface is aligned and functional.
|
||||
-- Send a zero value to initialize the DAC then go to idle.
|
||||
------------------------------------------------------------------------
|
||||
when S_RESET =>
|
||||
|
||||
if (enable = '1') and (enable_d1 = '0') then
|
||||
sm_wavedata <= (others=>'0');
|
||||
sm_wavedata_dv <= '1';
|
||||
sm_state <= S_IDLE;
|
||||
end if;
|
||||
sm_busy <= '0';
|
||||
ram_waveform_enb <= '0';
|
||||
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Wait for rising edge of 'start'.
|
||||
-- No data output.
|
||||
------------------------------------------------------------------------
|
||||
when S_IDLE =>
|
||||
|
||||
if (start = '1') and (start_d1 = '0') then
|
||||
sm_state <= S_WAIT;
|
||||
sm_busy <= '1';
|
||||
else
|
||||
sm_busy <= '0';
|
||||
end if;
|
||||
|
||||
ram_waveform_enb <= '0';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Wait for cnt_time, external input, to match pulse position RAM output
|
||||
-- Return to idle state if max time is reached. Output waveform value zero.
|
||||
------------------------------------------------------------------------
|
||||
when S_WAIT =>
|
||||
|
||||
-- Start to output wave and increment pulse position RAM address
|
||||
if (v_cnt_time = cnt_time) then
|
||||
sm_state <= S_WAVE_UP;
|
||||
-- set the wavetable's address to the starting address defined from the pulse ram
|
||||
ram_waveform_addrb <= v_addr_start;
|
||||
elsif (cnt_time = X"FFFFFF") then
|
||||
sm_state <= S_IDLE;
|
||||
end if;
|
||||
|
||||
ram_waveform_enb <= '1';
|
||||
------------------------------------------------------------------------
|
||||
-- Output the raising edge of a waveform
|
||||
-- Hold the last address when complete
|
||||
------------------------------------------------------------------------
|
||||
when S_WAVE_UP =>
|
||||
-- Check if is end of rise of the waveform, and hold the address
|
||||
if (ram_waveform_addrb = v_addr_end) then
|
||||
sm_state <= S_WAVE_FLAT;
|
||||
-- initialize the counter for the flat top of the waveform
|
||||
cnt_wave_top <= std_logic_vector(to_unsigned(0, C_BITS_ADDR_TOP));
|
||||
else
|
||||
-- Output waveform from RAM , and increment the address
|
||||
-- TODO: apply scaling factor to the address and then to the output
|
||||
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1);
|
||||
end if;
|
||||
sm_wavedata <= ram_waveform_doutb;
|
||||
sm_wavedata_dv <= '1';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Hold the last address and output its data
|
||||
-- decrement from this address when finished waiting
|
||||
------------------------------------------------------------------------
|
||||
when S_WAVE_FLAT =>
|
||||
if (cnt_wave_top = v_flattop) then
|
||||
sm_state <= S_WAVE_DOWN;
|
||||
else
|
||||
cnt_wave_top <= std_logic_vector(unsigned(cnt_wave_top) + 1);
|
||||
end if;
|
||||
sm_wavedata <= ram_waveform_doutb;
|
||||
sm_wavedata_dv <= '1';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Output the falling edge of a waveform
|
||||
-- Hold the start address when complete
|
||||
------------------------------------------------------------------------
|
||||
when S_WAVE_DOWN =>
|
||||
|
||||
-- End of waveform?
|
||||
if (ram_waveform_addrb = v_addr_start) then
|
||||
|
||||
-- If the end of the pulse table is reached then go to idle
|
||||
if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_NUM_PULSE-1,4))) then
|
||||
ram_pulse_addrb <= (others=>'0');
|
||||
sm_state <= S_IDLE;
|
||||
|
||||
else -- increment pulse address for the next waveform
|
||||
ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
|
||||
sm_state <= S_WAIT;
|
||||
end if;
|
||||
|
||||
-- Output waveform from RAM with decremented address
|
||||
else
|
||||
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - 1);
|
||||
end if;
|
||||
sm_wavedata <= ram_waveform_doutb;
|
||||
sm_wavedata_dv <= '1';
|
||||
|
||||
------------------------------------------------------------------------
|
||||
-- Default
|
||||
------------------------------------------------------------------------
|
||||
when others =>
|
||||
sm_state <= S_IDLE;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
-- AXI-Stream output.
|
||||
-- TBD: This should come from a FIFO
|
||||
-- TODO: the bits are not correct, should be top bits (C_BITS_GAIN_FACTOR + 16 downto C_BITS_GAIN_FACTOR), but for now just make it this way so modelsim can simulate
|
||||
-- TODO: apply scaling factor to the output
|
||||
axis_tdata <= sm_wavedata; -- axi stream output data, this output should be multiplied by the gain factor, then take the top 16 bits
|
||||
axis_tvalid <= sm_wavedata_dv; -- axi_stream output data valid
|
||||
|
||||
-- TBD : Generate in state machine?
|
||||
axis_tlast <= '0'; -- axi_stream output last
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- **** TBD : ADD FIFO ****
|
||||
----------------------------------------------------------------
|
||||
-- FIFO for waveform data
|
||||
-- connect to external output to whatever we want to connect
|
||||
----------------------------------------------------------------
|
||||
--u_data_to_stream : entity work.fifo_data_to_stream
|
||||
--port map (
|
||||
-- clk => clk, -- input std_logic
|
||||
-- srst => reset, -- input std_logic
|
||||
-- rd_en => fifo_rd_en, -- input std_logic
|
||||
-- wr_en => fifo_wr_en, -- input std_logic
|
||||
-- empty => fifo_empty, -- output std_logic
|
||||
-- full => fifo_full, -- output std_logic
|
||||
-- din => ram_waveform_doutb, -- input slv(15 downto 0)
|
||||
-- dout => fifo_dout, -- output slv(15 downto 0)
|
||||
--
|
||||
-- -- FIFO signals, some of then are for debug purpose
|
||||
-- wr_ack => fifo_wr_ack, -- output std_logic
|
||||
-- overflow => fifo_overflow, -- output std_logic
|
||||
-- valid => fifo_valid, -- output std_logic
|
||||
-- underflow => fifo_underflow, -- output std_logic
|
||||
-- wr_rst_busy => fifo_wr_rst_busy, -- output std_logic
|
||||
-- rd_rst_busy => fifo_rd_rst_busy -- output std_logic
|
||||
--);
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- CPU Read/Write RAM
|
||||
-- MSB of cpu_addr is used to select one of the two RAMs
|
||||
-- to read/write, and the remainder are a 9-bit or 4-bit RAM address.
|
||||
----------------------------------------------------------------
|
||||
pr_ram_rw : process (reset, clk)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
|
||||
ram_pulse_addra <= (others=>'0');
|
||||
ram_pulse_dina <= (others=>'0');
|
||||
ram_pulse_we <= '0';
|
||||
|
||||
ram_waveform_ena <= '0';
|
||||
ram_waveform_wea <= (others=>'0');
|
||||
ram_waveform_addra <= (others=>'0');
|
||||
ram_waveform_dina <= (others=>'0');
|
||||
|
||||
cpu_rdata <= (others=>'0');
|
||||
cpu_rdata_dv <= '0';
|
||||
cpu_rdata_dv_e1 <= '0';
|
||||
cpu_rdata_dv_e2 <= '0';
|
||||
cpu_rdata_ramsel_d1 <= '0';
|
||||
cpu_rdata_ramsel_d2 <= '0';
|
||||
|
||||
elsif rising_edge(clk) then
|
||||
|
||||
ram_waveform_ena <= '0';
|
||||
|
||||
-------------------------------------------------
|
||||
-- CPU writing RAM
|
||||
-------------------------------------------------
|
||||
if (cpu_wr = '1') and (cpu_sel = '1') then
|
||||
|
||||
-- 0 for pulse position, 1 for waveform table
|
||||
if (cpu_addr(9) = '1') then
|
||||
|
||||
ram_pulse_addra <= (others=>'0');
|
||||
ram_pulse_dina <= (others=>'0');
|
||||
ram_pulse_we <= '0';
|
||||
|
||||
ram_waveform_wea(0) <= '1';
|
||||
ram_waveform_ena <= '1';
|
||||
ram_waveform_addra <= cpu_addr(8 downto 0);
|
||||
ram_waveform_dina <= cpu_wdata;
|
||||
|
||||
else
|
||||
|
||||
ram_pulse_addra <= cpu_addr(5 downto 2);
|
||||
-- select which part of the 96-bit data to write
|
||||
if (cpu_addr(1 downto 0) = "00") then
|
||||
ram_pulse_dina(31 downto 0) <= cpu_wdata;
|
||||
elsif (cpu_addr(1 downto 0) = "01") then
|
||||
ram_pulse_dina(63 downto 32) <= cpu_wdata;
|
||||
elsif (cpu_addr(1 downto 0) = "10") then
|
||||
ram_pulse_dina(95 downto 64) <= cpu_wdata;
|
||||
ram_pulse_we <= '1'; -- Write on the thrid cycle
|
||||
end if;
|
||||
|
||||
|
||||
ram_waveform_ena <= '0';
|
||||
ram_waveform_wea <= (others=>'0');
|
||||
ram_waveform_addra <= (others=>'0');
|
||||
ram_waveform_dina <= (others=>'0');
|
||||
|
||||
end if;
|
||||
|
||||
cpu_rdata_dv_e1 <= '0';
|
||||
cpu_rdata_dv_e2 <= '0';
|
||||
cpu_rdata_ramsel_d1 <= '0';
|
||||
cpu_rdata_ramsel_d2 <= '0';
|
||||
|
||||
|
||||
-------------------------------------------------
|
||||
-- CPU read
|
||||
-------------------------------------------------
|
||||
elsif (cpu_wr = '0') and (cpu_sel = '1') then
|
||||
|
||||
if (cpu_addr(9) = '1') then -- Waveform
|
||||
ram_waveform_ena <= '1';
|
||||
ram_pulse_addra <= (others=>'0');
|
||||
ram_waveform_addra <= cpu_addr(8 downto 0);
|
||||
else -- Pulse
|
||||
ram_pulse_addra <= cpu_addr(5 downto 2);
|
||||
ram_pulse_douta_d1 <= ram_pulse_douta; -- Delay distrib RAM output to match pipeline of Block RAM
|
||||
ram_waveform_addra <= (others=>'0');
|
||||
end if;
|
||||
|
||||
ram_pulse_we <= '0';
|
||||
ram_waveform_wea(0) <= '0';
|
||||
|
||||
cpu_rdata_dv_e2 <= '1'; -- DV for cycle, when RAM output occurs
|
||||
cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
|
||||
cpu_rdata_ramsel_d1 <= cpu_addr(9); -- Save the select bit one cycle later
|
||||
cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1;
|
||||
|
||||
else
|
||||
ram_pulse_addra <= (others=>'0');
|
||||
ram_pulse_we <= '0';
|
||||
ram_waveform_addra <= (others=>'0');
|
||||
ram_waveform_wea(0) <= '0';
|
||||
|
||||
cpu_rdata_dv_e2 <= '0';
|
||||
cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
|
||||
cpu_rdata_ramsel_d1 <= '0';
|
||||
cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1;
|
||||
|
||||
end if;
|
||||
|
||||
-------------------------------------------------
|
||||
-- Output the delayed RAM data
|
||||
-- This adds a pipeline delay to the cpu_rdata_dv to account for
|
||||
-- the delay in reading data from the RAM
|
||||
-------------------------------------------------
|
||||
if (cpu_rdata_dv_e1 = '1') then
|
||||
|
||||
cpu_rdata_dv <= '1';
|
||||
|
||||
-- Select source of output data
|
||||
if (cpu_rdata_ramsel_d2 = '1') then -- Output is from waveform table
|
||||
cpu_rdata <= ram_waveform_douta;
|
||||
|
||||
elsif (cpu_rdata_ramsel_d2 = '0') then
|
||||
-- cpu_rdata <= X"00" & ram_pulse_douta_d1;
|
||||
-- select which part of the 96-bit data to read
|
||||
if (cpu_addr(1 downto 0) = "00") then
|
||||
cpu_rdata <= ram_pulse_douta_d1(31 downto 0);
|
||||
elsif (cpu_addr(1 downto 0) = "01") then
|
||||
cpu_rdata <= ram_pulse_douta_d1(63 downto 32);
|
||||
elsif (cpu_addr(1 downto 0) = "10") then
|
||||
cpu_rdata <= ram_pulse_douta_d1(95 downto 64);
|
||||
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else
|
||||
cpu_rdata <= (others=>'0');
|
||||
cpu_rdata_dv <= '0';
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process;
|
||||
|
||||
|
||||
-- ----------------------------------------------------------------
|
||||
-- -- Read time from RAM to generate pulses
|
||||
-- -- When input cnt_time equals RAM time output then set dout
|
||||
-- -- to RAM amplitude output and read next set of RAM data.
|
||||
-- -- Keep reading waveform RAM every clock cycle until the end of the RAM
|
||||
-- ----------------------------------------------------------------
|
||||
-- pr_ram_pulse : process(reset, clk)
|
||||
-- begin
|
||||
-- if (reset = '1') then
|
||||
--
|
||||
-- ram_pulse_addrb <= (others => '0');
|
||||
-- start_pulse <= '0';
|
||||
-- dout_dv <= '0';
|
||||
--
|
||||
-- elsif rising_edge(clk) then
|
||||
--
|
||||
-- -- dout <= ram_amplitude;
|
||||
--
|
||||
-- if (cnt_time = X"000000") then -- Not triggered
|
||||
-- ram_pulse_addrb <= (others=>'0');
|
||||
-- dout_dv <= '0';
|
||||
-- start_pulse <= '0';
|
||||
--
|
||||
-- elsif (ram_time = cnt_time) then
|
||||
--
|
||||
-- ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
|
||||
-- dout_dv <= '1';
|
||||
-- start_pulse <= '1';
|
||||
--
|
||||
-- else
|
||||
-- dout_dv <= '0';
|
||||
-- start_pulse <= '0';
|
||||
-- end if;
|
||||
--
|
||||
-- end if;
|
||||
--
|
||||
-- end process;
|
||||
--
|
||||
--
|
||||
-- ----------------------------------------------------------------
|
||||
-- -- Read amplitude from Waveform RAM to generate pulses
|
||||
-- -- When start_pulse is asserted, and when FIFO is not full, write
|
||||
-- -- amplitude to FIFO.
|
||||
-- ----------------------------------------------------------------
|
||||
-- pr_ram_wavetable : process(reset, clk)
|
||||
-- begin
|
||||
-- if (reset = '1') then
|
||||
-- fifo_wr_en <= '0';
|
||||
-- ram_waveform_addrb <= (others => '0');
|
||||
-- ram_waveform_enb <= '0';
|
||||
-- busy <= '0';
|
||||
-- elsif rising_edge(clk) then
|
||||
-- if (read_table = '1') then -- start_pulse get asserted
|
||||
-- busy <= '1';
|
||||
-- -- TODO EricToGeoff : This condition may not satisfy all cases of a fifo_ready, maybe also utilize fifo_wr_ack or just a simple FSM?
|
||||
-- if (fifo_full = '0') then
|
||||
-- fifo_wr_en <= '1';
|
||||
-- ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1);
|
||||
-- ram_waveform_enb <= '1';
|
||||
-- else
|
||||
-- fifo_wr_en <= '0';
|
||||
-- -- FIFO is full, wait
|
||||
-- ram_waveform_addrb <= ram_waveform_addrb;
|
||||
-- ram_waveform_enb <= '0';
|
||||
-- end if;
|
||||
-- else
|
||||
-- fifo_wr_en <= '0';
|
||||
-- ram_waveform_addrb <= (others => '0');
|
||||
-- ram_waveform_enb <= '0';
|
||||
-- end if;
|
||||
-- end if;
|
||||
--
|
||||
-- end process;
|
||||
--
|
||||
-- -- For new versions, ram_doutb are differnt RAMs b port outputs, ram_amplitude should go thought a FIFO first from RAM
|
||||
-- ram_time <= ram_doutb;
|
||||
-- read_table <= start_pulse;
|
||||
--
|
||||
-- fifo_rd_en <= axi_tready and fifo_full;
|
||||
|
||||
end rtl;
|
||||
|
|
@ -1,395 +0,0 @@
|
|||
-----------------------------------------------------------
|
||||
-- File : tb_cpubus_dacs_pulse_channel.vhd
|
||||
-----------------------------------------------------------
|
||||
--
|
||||
-- Testbench for CPU bus peripheral.
|
||||
--
|
||||
-- Description : Pulse output control of Qlaser FPGA
|
||||
-- Block drives AXI-stream to JESD DACs
|
||||
--
|
||||
----------------------------------------------------------
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
use ieee.std_logic_1164.all;
|
||||
use std.textio.all;
|
||||
|
||||
use work.std_iopak.all;
|
||||
|
||||
|
||||
entity tb_cpubus_dacs_pulse_channel is
|
||||
end tb_cpubus_dacs_pulse_channel;
|
||||
|
||||
architecture behave of tb_cpubus_dacs_pulse_channel is
|
||||
|
||||
signal clk : std_logic;
|
||||
signal reset : std_logic;
|
||||
signal enable : std_logic;
|
||||
signal start : std_logic;
|
||||
signal cnt_time : std_logic_vector(23 downto 0);
|
||||
signal busy : std_logic;
|
||||
signal cpu_wr : std_logic;
|
||||
signal cpu_sel : std_logic;
|
||||
signal cpu_addr : std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata : std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata_dv : std_logic;
|
||||
|
||||
-- AXI-stream output interface
|
||||
signal axis_tready : std_logic := '1'; -- Always ready
|
||||
signal axis_tdata : std_logic_vector(15 downto 0);
|
||||
signal axis_tvalid : std_logic;
|
||||
signal axis_tlast : std_logic;
|
||||
|
||||
-- Halts simulation by stopping clock when set true
|
||||
signal sim_done : boolean := false;
|
||||
|
||||
-- Crystal clock freq expressed in MHz
|
||||
constant CLK_FREQ_MHZ : real := 100.0;
|
||||
-- Clock period
|
||||
constant CLK_PER : time := integer(1.0E+6/(CLK_FREQ_MHZ)) * 1 ps;
|
||||
|
||||
-- Block registers
|
||||
constant ADR_RAM_PULSE : integer := 0; -- base address for pulse RAM, TODO: this constant should eventually go to qlaser_pkg
|
||||
constant ADR_RAM_WAVE : integer := 512; --
|
||||
|
||||
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write procedure. Address in decimal. Data in hex
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant d : in std_logic_vector(31 downto 0);
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
begin
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
cpu_wr <= '1';
|
||||
cpu_addr <= std_logic_vector(to_unsigned(a, 16));
|
||||
cpu_wdata <= std_logic_vector(d);
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '0';
|
||||
cpu_wr <= '0';
|
||||
cpu_addr <= (others=>'0');
|
||||
cpu_wdata <= (others=>'0');
|
||||
wait until clk'event and clk='0';
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write pulse definition RAM
|
||||
-- Use 96 bit data to make three 32-bit writes
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write_pulsedef(
|
||||
signal clk : in std_logic;
|
||||
|
||||
constant num_entry : in integer;
|
||||
|
||||
-- TODO: Partial ? list of parameters
|
||||
constant pulsetime : in integer; -- Pulse time in clock cycles
|
||||
constant timefactor : in real; -- Fixed point time scale factor
|
||||
constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000"
|
||||
constant wavestartaddr : in integer; -- Start address in waveform RAM
|
||||
constant wavesteps : in integer; -- Number of steps in waveform rise and fall
|
||||
constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall
|
||||
|
||||
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
-- Vectors for converted values
|
||||
variable slv_pulsetime : std_logic_vector(26 downto 0); -- For 27-bit pulse time
|
||||
variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep
|
||||
variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain
|
||||
variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM
|
||||
variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform
|
||||
|
||||
variable slv_entry_data : std_logic_vector(95 downto 0); -- Vector for entire memory entry
|
||||
|
||||
-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg
|
||||
-- Define the number of fractional bits
|
||||
constant BIT_FRAC : integer := 4; -- TODO: this should be defined in qlaser_pkg
|
||||
begin
|
||||
|
||||
-- Convert each field into its std_logic_vector equivalent
|
||||
slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 27));
|
||||
slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12));
|
||||
slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10));
|
||||
slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17));
|
||||
|
||||
|
||||
--etc, etc.
|
||||
|
||||
-- Build full entry out of component fields. Final length should be 96 bits.
|
||||
-- slv_entry_data := "000" & slv_pulsetime & slv_timefactor & slv_gainfactor & slv_wavestartaddr & slv_wavesteps & slv_wavetopwidth; -- This might not correct
|
||||
|
||||
-- -- Write 96-bit entry in 3 writes. (Address is an integer)
|
||||
-- cpu_write(clk, ADR_RAM_PULSE+(4*num_entry) , slv_entry_data(31 downto 0), cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
-- cpu_write(clk, ADR_RAM_PULSE+(4*num_entry)+1 , slv_entry_data(63 downto 32), cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
-- cpu_write(clk, ADR_RAM_PULSE+(4*num_entry)+2 , slv_entry_data(95 downto 64), cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
-- Write 32-bit entry in
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU write procedure. Address and Data in decimal
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_write(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant d : in integer;
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
begin
|
||||
cpu_write(clk, a , std_logic_vector(to_unsigned(d,32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
end;
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU read procedure
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_read(
|
||||
signal clk : in std_logic;
|
||||
constant a : in integer;
|
||||
constant exp_d : in std_logic_vector(31 downto 0);
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata : in std_logic_vector(31 downto 0);
|
||||
signal cpu_rdata_dv : in std_logic
|
||||
) is
|
||||
variable v_bdone : boolean := false;
|
||||
variable str_out : string(1 to 256);
|
||||
begin
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
cpu_wr <= '0';
|
||||
cpu_addr <= std_logic_vector(to_unsigned(a, 16));
|
||||
cpu_wdata <= (others=>'0');
|
||||
while (v_bdone = false) loop
|
||||
wait until clk'event and clk='0';
|
||||
cpu_sel <= '1';
|
||||
if (cpu_rdata_dv = '1') then
|
||||
if (cpu_rdata /= exp_d) then
|
||||
fprint(str_out, "Read exp: 0x%s actual: 0x%s\n", to_string(to_bitvector(exp_d),"%08X"), to_string(to_bitvector(cpu_rdata),"%08X"));
|
||||
report str_out severity error;
|
||||
end if;
|
||||
v_bdone := true;
|
||||
cpu_sel <= '0';
|
||||
cpu_addr <= (others=>'0');
|
||||
end if;
|
||||
end loop;
|
||||
wait until clk'event and clk='0';
|
||||
wait until clk'event and clk='0';
|
||||
end;
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- CPU read pulse definition RAM
|
||||
-- Use 96 bit data to make three 32-bit writes
|
||||
-------------------------------------------------------------
|
||||
procedure cpu_read_pulsedef(
|
||||
signal clk : in std_logic;
|
||||
|
||||
constant num_entry : in integer;
|
||||
|
||||
-- TODO: Partial ? list of parameters
|
||||
constant pulsetime : in integer; -- Pulse time in clock cycles
|
||||
constant timefactor : in real; -- Fixed point time scale factor
|
||||
constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000"
|
||||
constant wavestartaddr : in integer; -- Start address in waveform RAM
|
||||
constant wavesteps : in integer; -- Number of steps in waveform rise and fall
|
||||
constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall
|
||||
|
||||
|
||||
signal cpu_sel : out std_logic;
|
||||
signal cpu_wr : out std_logic;
|
||||
signal cpu_addr : out std_logic_vector(15 downto 0);
|
||||
signal cpu_wdata : out std_logic_vector(31 downto 0)
|
||||
) is
|
||||
-- Vectors for converted values
|
||||
variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time
|
||||
variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep
|
||||
variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain
|
||||
variable slv_wavestartaddr : std_logic_vector( 9 downto 0); -- For 10-bit address i.e. 1024 point waveform RAM
|
||||
variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
|
||||
variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform
|
||||
|
||||
variable slv_entry_data : std_logic_vector(95 downto 0); -- Vector for entire memory entry
|
||||
|
||||
-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg
|
||||
-- Define the number of fractional bits
|
||||
constant BIT_FRAC : integer := 4; -- TODO: this should be defined in qlaser_pkg
|
||||
begin
|
||||
|
||||
-- Convert each field into its std_logic_vector equivalent
|
||||
slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24));
|
||||
slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part
|
||||
slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 10));
|
||||
slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10));
|
||||
slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17));
|
||||
|
||||
|
||||
--etc, etc.
|
||||
|
||||
-- Build full entry out of component fields. Final length should be 96 bits.
|
||||
slv_entry_data := "000" & slv_pulsetime & slv_timefactor & slv_gainfactor & slv_wavestartaddr & slv_wavesteps & slv_wavetopwidth; -- This might not correct
|
||||
|
||||
-- Write 96-bit entry in 3 writes. (Address is an integer)
|
||||
cpu_read(clk, ADR_RAM_PULSE+(4*num_entry), slv_entry_data(31 downto 0), cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
cpu_read(clk, ADR_RAM_PULSE+(4*num_entry) + 1, slv_entry_data(63 downto 32), cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
cpu_read(clk, ADR_RAM_PULSE+(4*num_entry) + 2, slv_entry_data(95 downto 64), cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
|
||||
|
||||
end;
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Delay
|
||||
-------------------------------------------------------------
|
||||
procedure clk_delay(
|
||||
constant nclks : in integer
|
||||
) is
|
||||
begin
|
||||
for I in 0 to nclks loop
|
||||
wait until clk'event and clk ='0';
|
||||
end loop;
|
||||
end;
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Print a string with no time or instance path.
|
||||
----------------------------------------------------------------
|
||||
procedure cpu_print_msg(
|
||||
constant msg : in string
|
||||
) is
|
||||
variable line_out : line;
|
||||
begin
|
||||
write(line_out, msg);
|
||||
writeline(output, line_out);
|
||||
end procedure cpu_print_msg;
|
||||
|
||||
|
||||
begin
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Unit Under Test
|
||||
-------------------------------------------------------------
|
||||
u_dac_pulse : entity work.qlaser_dacs_pulse_channel
|
||||
port map (
|
||||
clk => clk , -- in std_logic;
|
||||
reset => reset , -- in std_logic;
|
||||
|
||||
enable => enable , -- out std_logic;
|
||||
start => start , -- out std_logic;
|
||||
cnt_time => cnt_time , -- out std_logic_vector(23 downto 0); -- Set to '1' while SPI interface is busy
|
||||
|
||||
busy => busy , -- out std_logic; -- Set to '1' while SPI interface is busy
|
||||
|
||||
-- CPU interface
|
||||
cpu_wr => cpu_wr , -- in std_logic;
|
||||
cpu_sel => cpu_sel , -- in std_logic;
|
||||
cpu_addr => cpu_addr(11 downto 0) , -- in std_logic_vector(11 downto 0);
|
||||
cpu_wdata => cpu_wdata , -- in std_logic_vector(31 downto 0);
|
||||
|
||||
cpu_rdata => cpu_rdata , -- out std_logic_vector(31 downto 0);
|
||||
cpu_rdata_dv => cpu_rdata_dv , -- out std_logic;
|
||||
|
||||
|
||||
-- AXI-Stream interface
|
||||
axis_tready => axis_tready , -- in std_logic; -- Clock (50 MHz max)
|
||||
axis_tdata => axis_tdata , -- out std_logic_vector(15 downto 0);
|
||||
axis_tvalid => axis_tvalid , -- out std_logic; -- Master out, Slave in. (Data to DAC)
|
||||
axis_tlast => axis_tlast -- out std_logic; -- Active low chip select (sync_n)
|
||||
);
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Generate system clock. Halt when sim_done is true.
|
||||
-------------------------------------------------------------
|
||||
pr_clk : process
|
||||
begin
|
||||
clk <= '0';
|
||||
wait for (CLK_PER/2);
|
||||
clk <= '1';
|
||||
wait for (CLK_PER-CLK_PER/2);
|
||||
if (sim_done=true) then
|
||||
wait;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
-------------------------------------------------------------
|
||||
-- Reset and drive CPU bus
|
||||
-------------------------------------------------------------
|
||||
pr_main : process
|
||||
variable v_ndata32 : integer := 0;
|
||||
variable v_ndata16 : integer := 0;
|
||||
begin
|
||||
-- Reset
|
||||
reset <= '1';
|
||||
enable <= '0';
|
||||
start <= '0';
|
||||
cnt_time <= (others=>'0');
|
||||
|
||||
cpu_sel <= '0';
|
||||
cpu_wr <= '0';
|
||||
cpu_wdata <= (others=>'0');
|
||||
cpu_addr <= (others=>'0');
|
||||
|
||||
cpu_print_msg("Simulation start");
|
||||
clk_delay(5);
|
||||
reset <= '0';
|
||||
|
||||
clk_delay(5);
|
||||
enable <= '1';
|
||||
|
||||
|
||||
clk_delay(20);
|
||||
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Load pulse RAM with a series of pulse start times
|
||||
----------------------------------------------------------------
|
||||
v_ndata32 := 128; -- Time for first pulse
|
||||
cpu_print_msg("Load pulse RAM");
|
||||
for NADDR in 0 to 15 loop
|
||||
-- cpu_write(clk, ADR_RAM_PULSE + NADDR , v_ndata32 + (NADDR*(1024+32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata); -- TODO: rn don't know how to make it write three difference places, for now I', just gonna manually write it
|
||||
cpu_write_pulsedef(clk, NADDR, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 512, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
end loop;
|
||||
cpu_print_msg("Pulse RAM loaded");
|
||||
clk_delay(20);
|
||||
|
||||
----------------------------------------------------------------
|
||||
-- Read back Pulse RAM.
|
||||
----------------------------------------------------------------
|
||||
v_ndata32 := 128; -- Time for first pulse
|
||||
for NADDR in 0 to 15 loop
|
||||
cpu_read_pulsedef(clk, NADDR, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 512, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
|
||||
end loop;
|
||||
clk_delay(20);
|
||||
|
||||
wait for 10 us;
|
||||
|
||||
cpu_print_msg("Simulation done");
|
||||
clk_delay(5);
|
||||
|
||||
sim_done <= true;
|
||||
wait;
|
||||
|
||||
end process;
|
||||
|
||||
end behave;
|
||||
|
||||
|
|
@ -1,45 +0,0 @@
|
|||
# "cd" to the directory where this script is located
|
||||
cd [file dirname [info script]]
|
||||
|
||||
create_project zcu_pulse_channel ../../prj -force
|
||||
|
||||
set_property board_part xilinx.com:zcu102:part0:3.4 [current_project]
|
||||
|
||||
add_files {..\..\src\hdl\modules\qlaser_dacs_pulse_channel.vhdl}
|
||||
add_files -fileset sim_1 {..\..\src\hdl\tb\tb_cpubus_dacs_pulse_channel.vhdl}
|
||||
add_files {..\..\src\hdl\pkg\qlaser_dacs_pulse_channel_pkg.vhd}
|
||||
add_files {..\..\src\hdl\pkg\qlaser_dac_dc_pkg.vhd}
|
||||
add_files {..\..\src\hdl\pkg\qlaser_pkg.vhd}
|
||||
add_files {..\..\src\hdl\pkg\iopakp.vhd}
|
||||
add_files {..\..\src\hdl\pkg\iopakb.vhd}
|
||||
read_ip {..\xilinx-zcu\bram_pulseposition\bram_pulseposition.xci}
|
||||
read_ip {..\xilinx-zcu\bram_waveform\bram_waveform.xci}
|
||||
read_ip {..\xilinx-zcu\fifo_data_to_stream\fifo_data_to_stream.xci}
|
||||
read_ip {..\xilinx-zcu\bram_pulse_definition\bram_pulse_definition.xci}
|
||||
|
||||
# upgrade_ip [get_ips -filter {SCOPE !~ "*.bd"}]
|
||||
generate_target all [get_ips -filter {SCOPE !~ "*.bd"}]
|
||||
|
||||
# Run the synthesis and generate the IP output products
|
||||
launch_runs synth_1
|
||||
|
||||
# Wait for the synthesis to complete
|
||||
wait_on_run synth_1
|
||||
|
||||
# Generate the simulation models
|
||||
proc recursive_glob {dir} {
|
||||
set files [glob -nocomplain -type f -directory $dir *_sim_netlist.vhdl]
|
||||
foreach subdir [glob -nocomplain -type d -directory $dir *] {
|
||||
lappend files {*}[recursive_glob $subdir]
|
||||
}
|
||||
return $files
|
||||
}
|
||||
|
||||
set src_dir ../../prj/zcu_pulse_channel.gen/sources_1/ip/
|
||||
set files [recursive_glob $src_dir]
|
||||
|
||||
foreach file $files {
|
||||
file copy -force $file ../../src/hdl/ip_gen
|
||||
}
|
||||
|
||||
exit
|
||||
|
|
@ -1,2 +1 @@
|
|||
Please put your modelsim.ini file in this directory and compile modelsim in this directory.
|
||||
|
||||
|
|
|
|||
|
|
@ -1,2 +0,0 @@
|
|||
echo off
|
||||
vsim -c -quiet -do compile.do
|
||||
|
|
@ -1,8 +0,0 @@
|
|||
vlib work
|
||||
|
||||
vcom ../../src/hdl/ip_gen/*.vhd*
|
||||
vcom ../../src/hdl/pkg/*pkg.vhd
|
||||
vcom ../../src/hdl/pkg/iopakp.vhd
|
||||
vcom ../../src/hdl/pkg/iopakb.vhd
|
||||
vcom ../../src/hdl/modules/*.vhd*
|
||||
vcom ../../src/hdl/tb/*.vhd*
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
# take wave_values.txt and plot it
|
||||
import matplotlib
|
||||
import matplotlib.pyplot as plt
|
||||
import numpy as np
|
||||
import sys
|
||||
|
||||
matplotlib.use('wxAgg')
|
||||
|
||||
f = open('wave_values.txt', 'r')
|
||||
lines = f.readlines()
|
||||
f.close()
|
||||
|
||||
# convert to float
|
||||
vals = np.array([float(x) for x in lines])
|
||||
times = np.arange(0, len(vals), 1)/4096.0
|
||||
|
||||
# plot. range is 0 to 1
|
||||
plt.plot(times, vals)
|
||||
plt.show()
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,762 +0,0 @@
|
|||
; Copyright 1991-2009 Mentor Graphics Corporation
|
||||
;
|
||||
; All Rights Reserved.
|
||||
;
|
||||
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
|
||||
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
|
||||
;
|
||||
|
||||
[Library]
|
||||
others = $MODEL_TECH/../modelsim.ini
|
||||
|
||||
; Altera Primitive libraries
|
||||
;
|
||||
; VHDL Section
|
||||
;
|
||||
;
|
||||
; Verilog Section
|
||||
;
|
||||
|
||||
secureip = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/secureip
|
||||
unisim = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/unisim
|
||||
unimacro = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/unimacro
|
||||
unifast = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/unifast
|
||||
unisims_ver = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/unisims_ver
|
||||
unimacro_ver = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/unimacro_ver
|
||||
unifast_ver = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/unifast_ver
|
||||
simprims_ver = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/simprims_ver
|
||||
xpm = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xpm
|
||||
xilinx_vip = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xilinx_vip
|
||||
adc_dac_if_phy_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/adc_dac_if_phy_v1_0_0
|
||||
advanced_io_wizard_phy_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/advanced_io_wizard_phy_v1_0_0
|
||||
advanced_io_wizard_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/advanced_io_wizard_v1_0_7
|
||||
ahblite_axi_bridge_v3_0_21 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ahblite_axi_bridge_v3_0_21
|
||||
ai_noc = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ai_noc
|
||||
ai_pl_trig = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ai_pl_trig
|
||||
ai_pl = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ai_pl
|
||||
an_lt_v1_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/an_lt_v1_0_6
|
||||
audio_clock_recovery_unit_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/audio_clock_recovery_unit_v1_0_2
|
||||
audio_tpg_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/audio_tpg_v1_0_0
|
||||
av_pat_gen_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/av_pat_gen_v1_0_1
|
||||
av_pat_gen_v2_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/av_pat_gen_v2_0_0
|
||||
axis_cap_ctrl_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_cap_ctrl_v1_0_0
|
||||
axis_dbg_stub_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_dbg_stub_v1_0_0
|
||||
axis_dbg_sync_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_dbg_sync_v1_0_0
|
||||
axis_ila_adv_trig_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_ila_adv_trig_v1_0_0
|
||||
axis_ila_ct_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_ila_ct_v1_0_0
|
||||
axis_ila_pp_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_ila_pp_v1_0_0
|
||||
axis_ila_txns_cntr_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_ila_txns_cntr_v1_0_0
|
||||
axis_infrastructure_v1_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_infrastructure_v1_1_0
|
||||
axis_itct_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_itct_v1_0_0
|
||||
axis_mem_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_mem_v1_0_0
|
||||
axis_mu_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_mu_v1_0_0
|
||||
axis_protocol_checker_v2_0_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_protocol_checker_v2_0_10
|
||||
axi_ahblite_bridge_v3_0_23 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_ahblite_bridge_v3_0_23
|
||||
axi_amm_bridge_v1_0_16 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_amm_bridge_v1_0_16
|
||||
axi_bram_ctrl_v4_1_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_bram_ctrl_v4_1_6
|
||||
axi_chip2chip_v5_0_15 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_chip2chip_v5_0_15
|
||||
axi_dbg_hub = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_dbg_hub
|
||||
axi_infrastructure_v1_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_infrastructure_v1_1_0
|
||||
axi_jtag_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_jtag_v1_0_0
|
||||
axi_lite_ipif_v3_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_lite_ipif_v3_0_4
|
||||
axi_lmb_bridge_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_lmb_bridge_v1_0_0
|
||||
axi_pcie3_v3_0_22 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_pcie3_v3_0_22
|
||||
axi_perf_mon_v5_0_28 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_perf_mon_v5_0_28
|
||||
axi_pmon_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_pmon_v1_0_0
|
||||
axi_remapper_rx_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_remapper_rx_v1_0_0
|
||||
axi_remapper_tx_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_remapper_tx_v1_0_0
|
||||
blk_mem_gen_v8_3_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/blk_mem_gen_v8_3_6
|
||||
blk_mem_gen_v8_4_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/blk_mem_gen_v8_4_5
|
||||
bsip_v1_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/bsip_v1_1_0
|
||||
bs_mux_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/bs_mux_v1_0_0
|
||||
cam_v2_3_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/cam_v2_3_0
|
||||
clk_gen_sim_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/clk_gen_sim_v1_0_2
|
||||
clk_vip_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/clk_vip_v1_0_2
|
||||
cmac_usplus_v3_1_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/cmac_usplus_v3_1_9
|
||||
cmac_v2_6_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/cmac_v2_6_7
|
||||
compact_gt_v1_0_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/compact_gt_v1_0_12
|
||||
cpm4_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/cpm4_v1_0_7
|
||||
cpm5_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/cpm5_v1_0_7
|
||||
dcmac_v2_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dcmac_v2_0_0
|
||||
ddr4_pl_phy_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ddr4_pl_phy_v1_0_0
|
||||
ddr4_pl_v1_0_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ddr4_pl_v1_0_8
|
||||
displayport_v8_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/displayport_v8_1_5
|
||||
dist_mem_gen_v8_0_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dist_mem_gen_v8_0_13
|
||||
dprx_fec_8b10b_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dprx_fec_8b10b_v1_0_1
|
||||
dp_videoaxi4s_bridge_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dp_videoaxi4s_bridge_v1_0_1
|
||||
ecc_v2_0_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ecc_v2_0_13
|
||||
emb_fifo_gen_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/emb_fifo_gen_v1_0_2
|
||||
emb_mem_gen_v1_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/emb_mem_gen_v1_0_6
|
||||
emc_common_v3_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/emc_common_v3_0_5
|
||||
ethernet_1_10_25g_v2_7_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ethernet_1_10_25g_v2_7_5
|
||||
fast_adapter_v1_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/fast_adapter_v1_0_3
|
||||
fifo_generator_v13_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/fifo_generator_v13_0_6
|
||||
fifo_generator_v13_1_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/fifo_generator_v13_1_4
|
||||
fifo_generator_v13_2_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/fifo_generator_v13_2_7
|
||||
fit_timer_v2_0_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/fit_timer_v2_0_10
|
||||
generic_baseblocks_v2_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/generic_baseblocks_v2_1_0
|
||||
gigantic_mux = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/gigantic_mux
|
||||
gig_ethernet_pcs_pma_v16_2_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/gig_ethernet_pcs_pma_v16_2_8
|
||||
gmii_to_rgmii_v4_1_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/gmii_to_rgmii_v4_1_4
|
||||
gtwizard_ultrascale_v1_5_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/gtwizard_ultrascale_v1_5_4
|
||||
gtwizard_ultrascale_v1_6_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/gtwizard_ultrascale_v1_6_13
|
||||
gtwizard_ultrascale_v1_7_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/gtwizard_ultrascale_v1_7_13
|
||||
hbm2e_pl_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hbm2e_pl_v1_0_0
|
||||
hbm_v1_0_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hbm_v1_0_12
|
||||
hdcp22_cipher_dp_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hdcp22_cipher_dp_v1_0_0
|
||||
hdcp22_cipher_v1_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hdcp22_cipher_v1_0_3
|
||||
hdcp22_rng_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hdcp22_rng_v1_0_1
|
||||
hdcp_keymngmt_blk_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hdcp_keymngmt_blk_v1_0_0
|
||||
hdcp_v1_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hdcp_v1_0_3
|
||||
hdmi_acr_ctrl_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hdmi_acr_ctrl_v1_0_0
|
||||
hdmi_gt_controller_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hdmi_gt_controller_v1_0_7
|
||||
high_speed_selectio_wiz_v3_6_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/high_speed_selectio_wiz_v3_6_3
|
||||
i2s_receiver_v1_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/i2s_receiver_v1_0_5
|
||||
i2s_transmitter_v1_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/i2s_transmitter_v1_0_5
|
||||
ibert_lib_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ibert_lib_v1_0_7
|
||||
ieee802d3_clause74_fec_v1_0_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ieee802d3_clause74_fec_v1_0_13
|
||||
ilknf_v1_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ilknf_v1_1_0
|
||||
interlaken_v2_4_11 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/interlaken_v2_4_11
|
||||
in_system_ibert_v1_0_16 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/in_system_ibert_v1_0_16
|
||||
iomodule_v3_1_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/iomodule_v3_1_8
|
||||
jesd204c_v4_2_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/jesd204c_v4_2_8
|
||||
jesd204_v7_2_15 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/jesd204_v7_2_15
|
||||
jtag_axi = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/jtag_axi
|
||||
lib_cdc_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lib_cdc_v1_0_2
|
||||
lib_pkg_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lib_pkg_v1_0_2
|
||||
ll_compress_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ll_compress_v1_0_0
|
||||
ll_compress_v1_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ll_compress_v1_1_0
|
||||
ll_compress_v2_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ll_compress_v2_0_1
|
||||
ll_compress_v2_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ll_compress_v2_1_0
|
||||
lmb_bram_if_cntlr_v4_0_21 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lmb_bram_if_cntlr_v4_0_21
|
||||
lmb_v10_v3_0_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lmb_v10_v3_0_12
|
||||
ltlib_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ltlib_v1_0_0
|
||||
lut_buffer_v2_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lut_buffer_v2_0_0
|
||||
l_ethernet_v3_3_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/l_ethernet_v3_3_0
|
||||
mammoth_transcode_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mammoth_transcode_v1_0_0
|
||||
mem_pl_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mem_pl_v1_0_0
|
||||
microblaze_v11_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/microblaze_v11_0_9
|
||||
microblaze_v9_5_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/microblaze_v9_5_4
|
||||
mipi_csi2_rx_ctrl_v1_0_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mipi_csi2_rx_ctrl_v1_0_8
|
||||
mipi_csi2_tx_ctrl_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mipi_csi2_tx_ctrl_v1_0_4
|
||||
mipi_dphy_v4_3_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mipi_dphy_v4_3_4
|
||||
mipi_dsi_tx_ctrl_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mipi_dsi_tx_ctrl_v1_0_7
|
||||
mpegtsmux_v1_1_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mpegtsmux_v1_1_4
|
||||
mrmac_v1_6_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mrmac_v1_6_0
|
||||
multi_channel_25g_rs_fec_v1_0_18 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/multi_channel_25g_rs_fec_v1_0_18
|
||||
mutex_v2_1_11 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mutex_v2_1_11
|
||||
axi_tg_lib = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_tg_lib
|
||||
noc_hbm_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/noc_hbm_v1_0_0
|
||||
noc_ncrb_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/noc_ncrb_v1_0_0
|
||||
noc_nidb_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/noc_nidb_v1_0_0
|
||||
noc_nmu_phydir_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/noc_nmu_phydir_v1_0_0
|
||||
noc_npp_rptr_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/noc_npp_rptr_v1_0_0
|
||||
noc_nps4_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/noc_nps4_v1_0_0
|
||||
noc_nps6_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/noc_nps6_v1_0_0
|
||||
noc_nps_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/noc_nps_v1_0_0
|
||||
noc_nsu_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/noc_nsu_v1_0_0
|
||||
nvmeha_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/nvmeha_v1_0_7
|
||||
nvme_tc_v3_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/nvme_tc_v3_0_1
|
||||
oddr_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/oddr_v1_0_2
|
||||
oran_radio_if_v2_2_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/oran_radio_if_v2_2_0
|
||||
pci32_v5_0_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pci32_v5_0_12
|
||||
pci64_v5_0_11 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pci64_v5_0_11
|
||||
pcie_axi4lite_tap_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pcie_axi4lite_tap_v1_0_1
|
||||
pcie_dma_versal_v2_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pcie_dma_versal_v2_0_9
|
||||
pcie_jtag_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pcie_jtag_v1_0_0
|
||||
pcie_qdma_mailbox_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pcie_qdma_mailbox_v1_0_0
|
||||
pc_cfr_v6_4_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pc_cfr_v6_4_2
|
||||
pc_cfr_v7_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pc_cfr_v7_0_1
|
||||
pc_cfr_v7_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pc_cfr_v7_1_0
|
||||
picxo = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/picxo
|
||||
ptp_1588_timer_syncer_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ptp_1588_timer_syncer_v1_0_2
|
||||
ptp_1588_timer_syncer_v2_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ptp_1588_timer_syncer_v2_0_3
|
||||
qdma_v4_0_11 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/qdma_v4_0_11
|
||||
qdriv_pl_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/qdriv_pl_v1_0_7
|
||||
rama_v1_1_12_lib = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/rama_v1_1_12_lib
|
||||
rld3_pl_phy_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/rld3_pl_phy_v1_0_0
|
||||
rld3_pl_v1_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/rld3_pl_v1_0_9
|
||||
roe_framer_v3_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/roe_framer_v3_0_3
|
||||
rst_vip_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/rst_vip_v1_0_4
|
||||
smartconnect_v1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/smartconnect_v1_0
|
||||
sem_ultra_v3_1_23 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/sem_ultra_v3_1_23
|
||||
sem_v4_1_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/sem_v4_1_13
|
||||
shell_utils_msp432_bsl_crc_gen_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/shell_utils_msp432_bsl_crc_gen_v1_0_0
|
||||
sim_clk_gen_v1_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/sim_clk_gen_v1_0_3
|
||||
sim_rst_gen_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/sim_rst_gen_v1_0_2
|
||||
sim_trig_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/sim_trig_v1_0_7
|
||||
stm_v1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/stm_v1_0
|
||||
stm_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/stm_v1_0_0
|
||||
system_cache_v5_0_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/system_cache_v5_0_8
|
||||
ta_dma_v1_0_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ta_dma_v1_0_10
|
||||
tcc_decoder_3gpplte_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tcc_decoder_3gpplte_v3_0_6
|
||||
ten_gig_eth_mac_v15_1_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ten_gig_eth_mac_v15_1_10
|
||||
ten_gig_eth_pcs_pma_v6_0_22 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ten_gig_eth_pcs_pma_v6_0_22
|
||||
timer_sync_1588_v1_2_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/timer_sync_1588_v1_2_4
|
||||
tmr_inject_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tmr_inject_v1_0_4
|
||||
tmr_manager_v1_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tmr_manager_v1_0_9
|
||||
tmr_voter_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tmr_voter_v1_0_4
|
||||
trace_s2mm_v1_2_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/trace_s2mm_v1_2_0
|
||||
tsn_endpoint_ethernet_mac_block_v1_0_11 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tsn_endpoint_ethernet_mac_block_v1_0_11
|
||||
uhdsdi_gt_v2_0_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/uhdsdi_gt_v2_0_8
|
||||
uram_rd_back_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/uram_rd_back_v1_0_2
|
||||
usxgmii_v1_2_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/usxgmii_v1_2_7
|
||||
util_ff_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/util_ff_v1_0_0
|
||||
util_idelay_ctrl_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/util_idelay_ctrl_v1_0_2
|
||||
util_reduced_logic_v2_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/util_reduced_logic_v2_0_4
|
||||
util_vector_logic_v2_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/util_vector_logic_v2_0_2
|
||||
vfb_v1_0_20 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/vfb_v1_0_20
|
||||
video_frame_crc_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/video_frame_crc_v1_0_4
|
||||
vid_edid_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/vid_edid_v1_0_0
|
||||
vid_phy_controller_v2_1_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/vid_phy_controller_v2_1_13
|
||||
vid_phy_controller_v2_2_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/vid_phy_controller_v2_2_13
|
||||
vitis_deadlock_detector_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/vitis_deadlock_detector_v1_0_1
|
||||
v_axi4s_remap_v1_0_19 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_axi4s_remap_v1_0_19
|
||||
v_axi4s_remap_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_axi4s_remap_v1_1_5
|
||||
v_csc_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_csc_v1_1_5
|
||||
v_deinterlacer_v5_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_deinterlacer_v5_1_0
|
||||
v_demosaic_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_demosaic_v1_1_5
|
||||
v_frmbuf_rd_v2_2_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_frmbuf_rd_v2_2_5
|
||||
v_frmbuf_wr_v2_2_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_frmbuf_wr_v2_2_5
|
||||
v_gamma_lut_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_gamma_lut_v1_1_5
|
||||
v_hcresampler_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_hcresampler_v1_1_5
|
||||
v_hdmi_phy1_v1_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_hdmi_phy1_v1_0_6
|
||||
v_hdmi_rx_v3_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_hdmi_rx_v3_0_0
|
||||
v_hdmi_tx_v3_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_hdmi_tx_v3_0_0
|
||||
v_hscaler_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_hscaler_v1_1_5
|
||||
v_letterbox_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_letterbox_v1_1_5
|
||||
v_mix_v5_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_mix_v5_1_5
|
||||
v_scenechange_v1_1_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_scenechange_v1_1_4
|
||||
v_sdi_rx_vid_bridge_v2_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_sdi_rx_vid_bridge_v2_0_0
|
||||
v_smpte_sdi_v3_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_smpte_sdi_v3_0_9
|
||||
v_smpte_uhdsdi_rx_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_smpte_uhdsdi_rx_v1_0_1
|
||||
v_smpte_uhdsdi_tx_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_smpte_uhdsdi_tx_v1_0_1
|
||||
v_smpte_uhdsdi_v1_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_smpte_uhdsdi_v1_0_9
|
||||
v_tpg_v8_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_tpg_v8_0_9
|
||||
v_tpg_v8_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_tpg_v8_1_5
|
||||
v_tpg_v8_2_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_tpg_v8_2_1
|
||||
v_uhdsdi_audio_v2_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_uhdsdi_audio_v2_0_6
|
||||
v_uhdsdi_vidgen_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_uhdsdi_vidgen_v1_0_1
|
||||
v_vcresampler_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_vcresampler_v1_1_5
|
||||
v_vid_in_axi4s_v4_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_vid_in_axi4s_v4_0_9
|
||||
v_vid_in_axi4s_v5_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_vid_in_axi4s_v5_0_1
|
||||
v_vscaler_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_vscaler_v1_1_5
|
||||
v_warp_filter_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_warp_filter_v1_0_2
|
||||
v_warp_init_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_warp_init_v1_0_2
|
||||
xbip_dsp48_wrapper_v3_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_dsp48_wrapper_v3_0_4
|
||||
xbip_utils_v3_0_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_utils_v3_0_10
|
||||
xdfe_nlf_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xdfe_nlf_v1_0_0
|
||||
xdfe_resampler_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xdfe_resampler_v1_0_4
|
||||
xdma_v4_1_17 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xdma_v4_1_17
|
||||
xlconcat_v2_1_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xlconcat_v2_1_4
|
||||
xlconstant_v1_1_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xlconstant_v1_1_7
|
||||
xlslice_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xlslice_v1_0_2
|
||||
xpm_cdc_gen_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xpm_cdc_gen_v1_0_1
|
||||
xsdbm_v3_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xsdbm_v3_0_0
|
||||
xxv_ethernet_v4_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xxv_ethernet_v4_1_0
|
||||
aurora_8b10b_versal_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/aurora_8b10b_versal_v1_0_1
|
||||
axi_c2c_v1_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_c2c_v1_0_3
|
||||
lib_srl_fifo_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lib_srl_fifo_v1_0_2
|
||||
lib_fifo_v1_0_16 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lib_fifo_v1_0_16
|
||||
axi_datamover_v5_1_28 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_datamover_v5_1_28
|
||||
amm_axi_bridge_v1_0_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/amm_axi_bridge_v1_0_12
|
||||
axis_register_slice_v1_1_26 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_register_slice_v1_1_26
|
||||
axis_switch_v1_1_26 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_switch_v1_1_26
|
||||
axis_clock_converter_v1_1_27 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_clock_converter_v1_1_27
|
||||
axis_data_fifo_v2_0_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_data_fifo_v2_0_8
|
||||
ats_switch_v1_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ats_switch_v1_0_5
|
||||
audio_formatter_v1_0_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/audio_formatter_v1_0_8
|
||||
axi4stream_vip_v1_1_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi4stream_vip_v1_1_12
|
||||
v_tc_v6_2_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_tc_v6_2_4
|
||||
v_dp_axi4s_vid_out_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_dp_axi4s_vid_out_v1_0_4
|
||||
v_tc_v6_1_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_tc_v6_1_13
|
||||
v_axi4s_vid_out_v4_0_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_axi4s_vid_out_v4_0_14
|
||||
axi4svideo_bridge_v1_0_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi4svideo_bridge_v1_0_14
|
||||
axis_accelerator_adapter_v2_1_16 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_accelerator_adapter_v2_1_16
|
||||
axis_broadcaster_v1_1_25 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_broadcaster_v1_1_25
|
||||
axis_combiner_v1_1_24 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_combiner_v1_1_24
|
||||
axis_data_fifo_v1_1_27 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_data_fifo_v1_1_27
|
||||
axis_dwidth_converter_v1_1_25 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_dwidth_converter_v1_1_25
|
||||
axis_ila_intf_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_ila_intf_v1_0_0
|
||||
axis_interconnect_v1_1_20 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_interconnect_v1_1_20
|
||||
axis_subset_converter_v1_1_26 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_subset_converter_v1_1_26
|
||||
axis_vio_v1_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axis_vio_v1_0_6
|
||||
axi_apb_bridge_v3_0_17 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_apb_bridge_v3_0_17
|
||||
axi_bram_ctrl_v4_0_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_bram_ctrl_v4_0_14
|
||||
axi_sg_v4_1_15 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_sg_v4_1_15
|
||||
axi_cdma_v4_1_26 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_cdma_v4_1_26
|
||||
axi_clock_converter_v2_1_25 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_clock_converter_v2_1_25
|
||||
axi_data_fifo_v2_1_25 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_data_fifo_v2_1_25
|
||||
axi_register_slice_v2_1_26 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_register_slice_v2_1_26
|
||||
axi_crossbar_v2_1_27 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_crossbar_v2_1_27
|
||||
axi_dma_v7_1_27 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_dma_v7_1_27
|
||||
axi_protocol_converter_v2_1_26 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_protocol_converter_v2_1_26
|
||||
axi_dwidth_converter_v2_1_26 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_dwidth_converter_v2_1_26
|
||||
axi_emc_v3_0_26 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_emc_v3_0_26
|
||||
axi_epc_v2_0_29 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_epc_v2_0_29
|
||||
lib_bmg_v1_0_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lib_bmg_v1_0_14
|
||||
axi_ethernetlite_v3_0_25 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_ethernetlite_v3_0_25
|
||||
axi_ethernet_buffer_v2_0_24 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_ethernet_buffer_v2_0_24
|
||||
axi_fifo_mm_s_v4_2_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_fifo_mm_s_v4_2_8
|
||||
axi_firewall_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_firewall_v1_1_5
|
||||
axi_firewall_v1_2_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_firewall_v1_2_1
|
||||
interrupt_control_v3_1_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/interrupt_control_v3_1_4
|
||||
axi_gpio_v2_0_28 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_gpio_v2_0_28
|
||||
axi_hbicap_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_hbicap_v1_0_4
|
||||
axi_hwicap_v3_0_30 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_hwicap_v3_0_30
|
||||
axi_iic_v2_1_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_iic_v2_1_2
|
||||
axi_intc_v4_1_17 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_intc_v4_1_17
|
||||
axi_interconnect_v1_7_20 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_interconnect_v1_7_20
|
||||
axi_master_burst_v2_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_master_burst_v2_0_7
|
||||
axi_msg_v1_0_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_msg_v1_0_8
|
||||
axi_mcdma_v1_1_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_mcdma_v1_1_7
|
||||
axi_memory_init_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_memory_init_v1_0_7
|
||||
axi_mm2s_mapper_v1_1_25 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_mm2s_mapper_v1_1_25
|
||||
axi_mmu_v2_1_24 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_mmu_v2_1_24
|
||||
axi_pcie_v2_9_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_pcie_v2_9_7
|
||||
axi_protocol_checker_v2_0_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_protocol_checker_v2_0_12
|
||||
axi_quad_spi_v3_2_25 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_quad_spi_v3_2_25
|
||||
axi_sideband_util_v1_0_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_sideband_util_v1_0_10
|
||||
axi_tft_v2_0_25 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_tft_v2_0_25
|
||||
axi_timebase_wdt_v3_0_18 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_timebase_wdt_v3_0_18
|
||||
axi_timer_v2_0_28 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_timer_v2_0_28
|
||||
axi_traffic_gen_v3_0_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_traffic_gen_v3_0_12
|
||||
axi_uart16550_v2_0_28 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_uart16550_v2_0_28
|
||||
axi_uartlite_v2_0_30 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_uartlite_v2_0_30
|
||||
axi_usb2_device_v5_0_27 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_usb2_device_v5_0_27
|
||||
axi_utils_v2_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_utils_v2_0_6
|
||||
axi_vdma_v6_3_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_vdma_v6_3_14
|
||||
xbip_pipe_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_pipe_v3_0_6
|
||||
xbip_dsp48_addsub_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_dsp48_addsub_v3_0_6
|
||||
xbip_addsub_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_addsub_v3_0_6
|
||||
c_reg_fd_v12_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/c_reg_fd_v12_0_6
|
||||
c_addsub_v12_0_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/c_addsub_v12_0_14
|
||||
axi_vfifo_ctrl_v2_0_28 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_vfifo_ctrl_v2_0_28
|
||||
axi_vip_v1_1_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_vip_v1_1_12
|
||||
bs_switch_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/bs_switch_v1_0_0
|
||||
canfd_v3_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/canfd_v3_0_5
|
||||
can_v5_0_29 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/can_v5_0_29
|
||||
cic_compiler_v4_0_16 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/cic_compiler_v4_0_16
|
||||
xbip_bram18k_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_bram18k_v3_0_6
|
||||
mult_gen_v12_0_18 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mult_gen_v12_0_18
|
||||
cmpy_v6_0_21 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/cmpy_v6_0_21
|
||||
c_mux_bit_v12_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/c_mux_bit_v12_0_6
|
||||
c_shift_ram_v12_0_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/c_shift_ram_v12_0_14
|
||||
c_mux_bus_v12_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/c_mux_bus_v12_0_6
|
||||
c_gate_bit_v12_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/c_gate_bit_v12_0_6
|
||||
xbip_counter_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_counter_v3_0_6
|
||||
c_counter_binary_v12_0_15 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/c_counter_binary_v12_0_15
|
||||
c_compare_v12_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/c_compare_v12_0_6
|
||||
convolution_v9_0_16 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/convolution_v9_0_16
|
||||
cordic_v6_0_18 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/cordic_v6_0_18
|
||||
cpri_v8_11_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/cpri_v8_11_12
|
||||
xbip_dsp48_acc_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_dsp48_acc_v3_0_6
|
||||
xbip_accum_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_accum_v3_0_6
|
||||
c_accum_v12_0_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/c_accum_v12_0_14
|
||||
dbg_intf = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dbg_intf
|
||||
xbip_dsp48_multadd_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_dsp48_multadd_v3_0_6
|
||||
dds_compiler_v6_0_22 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dds_compiler_v6_0_22
|
||||
dft_v4_0_16 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dft_v4_0_16
|
||||
dft_v4_2_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dft_v4_2_3
|
||||
dfx_axi_shutdown_manager_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dfx_axi_shutdown_manager_v1_0_0
|
||||
dfx_bitstream_monitor_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dfx_bitstream_monitor_v1_0_1
|
||||
dfx_controller_v1_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dfx_controller_v1_0_3
|
||||
dfx_decoupler_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dfx_decoupler_v1_0_4
|
||||
displayport_v7_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/displayport_v7_0_0
|
||||
displayport_v9_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/displayport_v9_0_5
|
||||
xbip_dsp48_mult_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_dsp48_mult_v3_0_6
|
||||
floating_point_v7_0_20 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/floating_point_v7_0_20
|
||||
div_gen_v5_1_19 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/div_gen_v5_1_19
|
||||
dsp_macro_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/dsp_macro_v1_0_2
|
||||
ernic_v3_1_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ernic_v3_1_2
|
||||
etrnic_v1_1_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/etrnic_v1_1_5
|
||||
fc32_rs_fec_v1_0_21 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/fc32_rs_fec_v1_0_21
|
||||
fec_5g_common_v1_1_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/fec_5g_common_v1_1_1
|
||||
fir_compiler_v5_2_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/fir_compiler_v5_2_6
|
||||
fir_compiler_v7_2_18 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/fir_compiler_v7_2_18
|
||||
flexo_100g_rs_fec_v1_0_21 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/flexo_100g_rs_fec_v1_0_21
|
||||
floating_point_v7_1_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/floating_point_v7_1_14
|
||||
g709_rs_encoder_v2_2_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/g709_rs_encoder_v2_2_8
|
||||
rs_toolbox_v9_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/rs_toolbox_v9_0_9
|
||||
g709_rs_decoder_v2_2_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/g709_rs_decoder_v2_2_10
|
||||
g709_fec_v2_4_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/g709_fec_v2_4_5
|
||||
g975_efec_i4_v1_0_18 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/g975_efec_i4_v1_0_18
|
||||
g975_efec_i7_v2_0_18 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/g975_efec_i7_v2_0_18
|
||||
hw_trace = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/hw_trace
|
||||
icap_arb_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/icap_arb_v1_0_1
|
||||
ieee802d3_200g_rs_fec_v2_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ieee802d3_200g_rs_fec_v2_0_5
|
||||
ieee802d3_25g_rs_fec_v1_0_23 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ieee802d3_25g_rs_fec_v1_0_23
|
||||
ieee802d3_400g_rs_fec_v2_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ieee802d3_400g_rs_fec_v2_0_7
|
||||
ieee802d3_50g_rs_fec_v1_0_19 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ieee802d3_50g_rs_fec_v1_0_19
|
||||
ieee802d3_50g_rs_fec_v2_0_11 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ieee802d3_50g_rs_fec_v2_0_11
|
||||
ieee802d3_rs_fec_v2_0_15 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ieee802d3_rs_fec_v2_0_15
|
||||
ldpc_v2_0_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/ldpc_v2_0_10
|
||||
xfft_v7_2_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xfft_v7_2_13
|
||||
lte_fft_v2_0_22 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lte_fft_v2_0_22
|
||||
xfft_v9_1_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xfft_v9_1_8
|
||||
lte_fft_v2_1_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lte_fft_v2_1_6
|
||||
mailbox_v2_1_15 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mailbox_v2_1_15
|
||||
mdm_v3_2_23 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mdm_v3_2_23
|
||||
mem_tg_v1_0_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mem_tg_v1_0_8
|
||||
iomodule_v3_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/iomodule_v3_0
|
||||
lmb_bram_if_cntlr_v4_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lmb_bram_if_cntlr_v4_0
|
||||
lmb_v10_v3_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/lmb_v10_v3_0
|
||||
axi_lite_ipif_v3_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/axi_lite_ipif_v3_0
|
||||
mdm_v3_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/mdm_v3_2
|
||||
microblaze_mcs_v2_3_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/microblaze_mcs_v2_3_6
|
||||
perf_axi_tg_v1_0_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/perf_axi_tg_v1_0_8
|
||||
polar_v1_0_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/polar_v1_0_10
|
||||
polar_v1_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/polar_v1_1_0
|
||||
processing_system7_vip_v1_0_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/processing_system7_vip_v1_0_14
|
||||
proc_sys_reset_v5_0_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/proc_sys_reset_v5_0_13
|
||||
pr_decoupler_v1_0_10 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/pr_decoupler_v1_0_10
|
||||
qdriv_pl_phy_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/qdriv_pl_phy_v1_0_0
|
||||
quadsgmii_v3_5_8 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/quadsgmii_v3_5_8
|
||||
rs_decoder_v9_0_18 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/rs_decoder_v9_0_18
|
||||
rs_encoder_v9_0_17 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/rs_encoder_v9_0_17
|
||||
sd_fec_v1_1_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/sd_fec_v1_1_9
|
||||
shell_utils_addr_remap_v1_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/shell_utils_addr_remap_v1_0_5
|
||||
sid_v8_0_17 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/sid_v8_0_17
|
||||
soft_ecc_proxy_v1_0_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/soft_ecc_proxy_v1_0_1
|
||||
spdif_v2_0_26 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/spdif_v2_0_26
|
||||
srio_gen2_v4_1_14 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/srio_gen2_v4_1_14
|
||||
switch_core_top_v1_0_11 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/switch_core_top_v1_0_11
|
||||
tcc_decoder_3gppmm_v2_0_23 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tcc_decoder_3gppmm_v2_0_23
|
||||
tcc_encoder_3gpplte_v4_0_16 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tcc_encoder_3gpplte_v4_0_16
|
||||
tcc_encoder_3gpp_v5_0_18 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tcc_encoder_3gpp_v5_0_18
|
||||
tmr_comparator_v1_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tmr_comparator_v1_0_5
|
||||
tmr_sem_v1_0_22 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tmr_sem_v1_0_22
|
||||
tri_mode_ethernet_mac_v9_0_22 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tri_mode_ethernet_mac_v9_0_22
|
||||
tsn_temac_v1_0_7 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/tsn_temac_v1_0_7
|
||||
vby1hs_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/vby1hs_v1_0_2
|
||||
versal_cips_ps_vip_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/versal_cips_ps_vip_v1_0_4
|
||||
videoaxi4s_bridge_v1_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/videoaxi4s_bridge_v1_0_5
|
||||
viterbi_v9_1_13 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/viterbi_v9_1_13
|
||||
v_dual_splitter_v1_0_9 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_dual_splitter_v1_0_9
|
||||
v_frmbuf_rd_v2_3_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_frmbuf_rd_v2_3_1
|
||||
v_frmbuf_rd_v2_4_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_frmbuf_rd_v2_4_0
|
||||
v_frmbuf_wr_v2_3_1 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_frmbuf_wr_v2_3_1
|
||||
v_frmbuf_wr_v2_4_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_frmbuf_wr_v2_4_0
|
||||
v_hdmi_rx1_v1_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_hdmi_rx1_v1_0_3
|
||||
v_hdmi_tx1_v1_0_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_hdmi_tx1_v1_0_3
|
||||
v_mix_v5_2_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_mix_v5_2_3
|
||||
v_multi_scaler_v1_2_3 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_multi_scaler_v1_2_3
|
||||
v_vid_gt_bridge_v1_0_5 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_vid_gt_bridge_v1_0_5
|
||||
v_vid_sdi_tx_bridge_v2_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_vid_sdi_tx_bridge_v2_0_0
|
||||
v_warp_filter_v1_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_warp_filter_v1_1_0
|
||||
v_warp_init_v1_1_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/v_warp_init_v1_1_0
|
||||
xbip_dsp48_multacc_v3_0_6 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_dsp48_multacc_v3_0_6
|
||||
xbip_multadd_v3_0_17 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xbip_multadd_v3_0_17
|
||||
xdfe_common_v1_0_0 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xdfe_common_v1_0_0
|
||||
xdfe_cc_filter_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xdfe_cc_filter_v1_0_4
|
||||
xdfe_cc_mixer_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xdfe_cc_mixer_v1_0_4
|
||||
xdfe_equalizer_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xdfe_equalizer_v1_0_4
|
||||
xdfe_fft_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xdfe_fft_v1_0_4
|
||||
xdfe_nr_prach_v1_0_4 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xdfe_nr_prach_v1_0_4
|
||||
xsdbs_v1_0_2 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/xsdbs_v1_0_2
|
||||
zynq_ultra_ps_e_vip_v1_0_12 = C:/Users/yuhc2/AppData/Roaming/Xilinx/Vivado/modelsim_simlib/zynq_ultra_ps_e_vip_v1_0_12
|
||||
[vcom]
|
||||
; VHDL93 variable selects language version as the default.
|
||||
; Default is VHDL-2002.
|
||||
; Value of 0 or 1987 for VHDL-1987.
|
||||
; Value of 1 or 1993 for VHDL-1993.
|
||||
; Default or value of 2 or 2002 for VHDL-2002.
|
||||
; Default or value of 3 or 2008 for VHDL-2008.
|
||||
VHDL93 = 2002
|
||||
|
||||
; Show source line containing error. Default is off.
|
||||
; Show_source = 1
|
||||
|
||||
; Turn off unbound-component warnings. Default is on.
|
||||
; Show_Warning1 = 0
|
||||
|
||||
; Turn off process-without-a-wait-statement warnings. Default is on.
|
||||
; Show_Warning2 = 0
|
||||
|
||||
; Turn off null-range warnings. Default is on.
|
||||
; Show_Warning3 = 0
|
||||
|
||||
; Turn off no-space-in-time-literal warnings. Default is on.
|
||||
; Show_Warning4 = 0
|
||||
|
||||
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
|
||||
; Show_Warning5 = 0
|
||||
|
||||
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
|
||||
; Optimize_1164 = 0
|
||||
|
||||
; Turn on resolving of ambiguous function overloading in favor of the
|
||||
; "explicit" function declaration (not the one automatically created by
|
||||
; the compiler for each type declaration). Default is off.
|
||||
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
|
||||
; will match the behavior of synthesis tools.
|
||||
Explicit = 1
|
||||
|
||||
; Turn off acceleration of the VITAL packages. Default is to accelerate.
|
||||
; NoVital = 1
|
||||
|
||||
; Turn off VITAL compliance checking. Default is checking on.
|
||||
; NoVitalCheck = 1
|
||||
|
||||
; Ignore VITAL compliance checking errors. Default is to not ignore.
|
||||
; IgnoreVitalErrors = 1
|
||||
|
||||
; Turn off VITAL compliance checking warnings. Default is to show warnings.
|
||||
; Show_VitalChecksWarnings = 0
|
||||
|
||||
; Keep silent about case statement static warnings.
|
||||
; Default is to give a warning.
|
||||
; NoCaseStaticError = 1
|
||||
|
||||
; Keep silent about warnings caused by aggregates that are not locally static.
|
||||
; Default is to give a warning.
|
||||
; NoOthersStaticError = 1
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "Loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on some limited synthesis rule compliance checking. Checks only:
|
||||
; -- signals used (read) by a process must be in the sensitivity list
|
||||
; CheckSynthesis = 1
|
||||
|
||||
; Activate optimizations on expressions that do not involve signals,
|
||||
; waits, or function/procedure/task invocations. Default is off.
|
||||
; ScalarOpts = 1
|
||||
|
||||
; Require the user to specify a configuration for all bindings,
|
||||
; and do not generate a compile time default binding for the
|
||||
; component. This will result in an elaboration error of
|
||||
; 'component not bound' if the user fails to do so. Avoids the rare
|
||||
; issue of a false dependency upon the unused default binding.
|
||||
; RequireConfigForAllDefaultBinding = 1
|
||||
|
||||
; Inhibit range checking on subscripts of arrays. Range checking on
|
||||
; scalars defined with subtypes is inhibited by default.
|
||||
; NoIndexCheck = 1
|
||||
|
||||
; Inhibit range checks on all (implicit and explicit) assignments to
|
||||
; scalar objects defined with subtypes.
|
||||
; NoRangeCheck = 1
|
||||
|
||||
[vlog]
|
||||
|
||||
; Turn off inclusion of debugging info within design units.
|
||||
; Default is to include debugging info.
|
||||
; NoDebug = 1
|
||||
|
||||
; Turn off "loading..." messages. Default is messages on.
|
||||
; Quiet = 1
|
||||
|
||||
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
|
||||
; Default is off.
|
||||
; Hazard = 1
|
||||
|
||||
; Turn on converting regular Verilog identifiers to uppercase. Allows case
|
||||
; insensitivity for module names. Default is no conversion.
|
||||
; UpCase = 1
|
||||
|
||||
; Turn on incremental compilation of modules. Default is off.
|
||||
; Incremental = 1
|
||||
|
||||
; Turns on lint-style checking.
|
||||
; Show_Lint = 1
|
||||
|
||||
[vsim]
|
||||
; Simulator resolution
|
||||
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
|
||||
Resolution = fs
|
||||
|
||||
; User time unit for run commands
|
||||
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
|
||||
; unit specified for Resolution. For example, if Resolution is 100ps,
|
||||
; then UserTimeUnit defaults to ps.
|
||||
; Should generally be set to default.
|
||||
UserTimeUnit = default
|
||||
|
||||
; Default run length
|
||||
RunLength = 100
|
||||
|
||||
; Maximum iterations that can be run without advancing simulation time
|
||||
IterationLimit = 5000
|
||||
|
||||
; Directive to license manager:
|
||||
; vhdl Immediately reserve a VHDL license
|
||||
; vlog Immediately reserve a Verilog license
|
||||
; plus Immediately reserve a VHDL and Verilog license
|
||||
; nomgc Do not look for Mentor Graphics Licenses
|
||||
; nomti Do not look for Model Technology Licenses
|
||||
; noqueue Do not wait in the license queue when a license isn't available
|
||||
; viewsim Try for viewer license but accept simulator license(s) instead
|
||||
; of queuing for viewer license
|
||||
; License = plus
|
||||
|
||||
; Stop the simulator after a VHDL/Verilog assertion message
|
||||
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
|
||||
BreakOnAssertion = 3
|
||||
|
||||
; Assertion Message Format
|
||||
; %S - Severity Level
|
||||
; %R - Report Message
|
||||
; %T - Time of assertion
|
||||
; %D - Delta
|
||||
; %I - Instance or Region pathname (if available)
|
||||
; %% - print '%' character
|
||||
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
|
||||
|
||||
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
|
||||
; AssertFile = assert.log
|
||||
|
||||
; Default radix for all windows and commands...
|
||||
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
|
||||
DefaultRadix = symbolic
|
||||
|
||||
; VSIM Startup command
|
||||
; Startup = do startup.do
|
||||
|
||||
; File for saving command transcript
|
||||
TranscriptFile = transcript
|
||||
|
||||
; File for saving command history
|
||||
; CommandHistory = cmdhist.log
|
||||
|
||||
; Specify whether paths in simulator commands should be described
|
||||
; in VHDL or Verilog format.
|
||||
; For VHDL, PathSeparator = /
|
||||
; For Verilog, PathSeparator = .
|
||||
; Must not be the same character as DatasetSeparator.
|
||||
PathSeparator = /
|
||||
|
||||
; Specify the dataset separator for fully rooted contexts.
|
||||
; The default is ':'. For example, sim:/top
|
||||
; Must not be the same character as PathSeparator.
|
||||
DatasetSeparator = :
|
||||
|
||||
; Disable VHDL assertion messages
|
||||
; IgnoreNote = 1
|
||||
; IgnoreWarning = 1
|
||||
; IgnoreError = 1
|
||||
; IgnoreFailure = 1
|
||||
|
||||
; Default force kind. May be freeze, drive, deposit, or default
|
||||
; or in other terms, fixed, wired, or charged.
|
||||
; A value of "default" will use the signal kind to determine the
|
||||
; force kind, drive for resolved signals, freeze for unresolved signals
|
||||
; DefaultForceKind = freeze
|
||||
|
||||
; If zero, open files when elaborated; otherwise, open files on
|
||||
; first read or write. Default is 0.
|
||||
; DelayFileOpen = 1
|
||||
|
||||
; Control VHDL files opened for write.
|
||||
; 0 = Buffered, 1 = Unbuffered
|
||||
UnbufferedOutput = 0
|
||||
|
||||
; Control the number of VHDL files open concurrently.
|
||||
; This number should always be less than the current ulimit
|
||||
; setting for max file descriptors.
|
||||
; 0 = unlimited
|
||||
ConcurrentFileLimit = 40
|
||||
|
||||
; Control the number of hierarchical regions displayed as
|
||||
; part of a signal name shown in the Wave window.
|
||||
; A value of zero tells VSIM to display the full name.
|
||||
; The default is 0.
|
||||
; WaveSignalNameWidth = 0
|
||||
|
||||
; Turn off warnings from the std_logic_arith, std_logic_unsigned
|
||||
; and std_logic_signed packages.
|
||||
; StdArithNoWarnings = 1
|
||||
|
||||
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
|
||||
; NumericStdNoWarnings = 1
|
||||
|
||||
; Control the format of the (VHDL) FOR generate statement label
|
||||
; for each iteration. Do not quote it.
|
||||
; The format string here must contain the conversion codes %s and %d,
|
||||
; in that order, and no other conversion codes. The %s represents
|
||||
; the generate_label; the %d represents the generate parameter value
|
||||
; at a particular generate iteration (this is the position number if
|
||||
; the generate parameter is of an enumeration type). Embedded whitespace
|
||||
; is allowed (but discouraged); leading and trailing whitespace is ignored.
|
||||
; Application of the format must result in a unique scope name over all
|
||||
; such names in the design so that name lookup can function properly.
|
||||
; GenerateFormat = %s__%d
|
||||
|
||||
; Specify whether checkpoint files should be compressed.
|
||||
; The default is 1 (compressed).
|
||||
; CheckpointCompressMode = 0
|
||||
|
||||
; List of dynamically loaded objects for Verilog PLI applications
|
||||
; Veriuser = veriuser.sl
|
||||
|
||||
; Specify default options for the restart command. Options can be one
|
||||
; or more of: -force -nobreakpoint -nolist -nolog -nowave
|
||||
; DefaultRestartOptions = -force
|
||||
|
||||
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
|
||||
; (> 500 megabyte memory footprint). Default is disabled.
|
||||
; Specify number of megabytes to lock.
|
||||
; LockedMemory = 1000
|
||||
|
||||
; Turn on (1) or off (0) WLF file compression.
|
||||
; The default is 1 (compress WLF file).
|
||||
; WLFCompress = 0
|
||||
|
||||
; Specify whether to save all design hierarchy (1) in the WLF file
|
||||
; or only regions containing logged signals (0).
|
||||
; The default is 0 (save only regions with logged signals).
|
||||
; WLFSaveAllRegions = 1
|
||||
|
||||
; WLF file time limit. Limit WLF file by time, as closely as possible,
|
||||
; to the specified amount of simulation time. When the limit is exceeded
|
||||
; the earliest times get truncated from the file.
|
||||
; If both time and size limits are specified the most restrictive is used.
|
||||
; UserTimeUnits are used if time units are not specified.
|
||||
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
|
||||
; WLFTimeLimit = 0
|
||||
|
||||
; WLF file size limit. Limit WLF file size, as closely as possible,
|
||||
; to the specified number of megabytes. If both time and size limits
|
||||
; are specified then the most restrictive is used.
|
||||
; The default is 0 (no limit).
|
||||
; WLFSizeLimit = 1000
|
||||
|
||||
; Specify whether or not a WLF file should be deleted when the
|
||||
; simulation ends. A value of 1 will cause the WLF file to be deleted.
|
||||
; The default is 0 (do not delete WLF file when simulation ends).
|
||||
; WLFDeleteOnQuit = 1
|
||||
|
||||
; Automatic SDF compilation
|
||||
; Disables automatic compilation of SDF files in flows that support it.
|
||||
; Default is on, uncomment to turn off.
|
||||
; NoAutoSDFCompile = 1
|
||||
|
||||
[lmc]
|
||||
|
||||
[msg_system]
|
||||
; Change a message severity or suppress a message.
|
||||
; The format is: <msg directive> = <msg number>[,<msg number>...]
|
||||
; Examples:
|
||||
; note = 3009
|
||||
; warning = 3033
|
||||
; error = 3010,3016
|
||||
; fatal = 3016,3033
|
||||
; suppress = 3009,3016,3043
|
||||
; The command verror <msg number> can be used to get the complete
|
||||
; description of a message.
|
||||
|
||||
; Control transcripting of elaboration/runtime messages.
|
||||
; The default is to have messages appear in the transcript and
|
||||
; recorded in the wlf file (messages that are recorded in the
|
||||
; wlf file can be viewed in the MsgViewer). The other settings
|
||||
; are to send messages only to the transcript or only to the
|
||||
; wlf file. The valid values are
|
||||
; both {default}
|
||||
; tran {transcript only}
|
||||
; wlf {wlf file only}
|
||||
; msgmode = both
|
||||
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
echo off
|
||||
modelsim -do run.do
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
do compile.do
|
||||
|
||||
vsim -voptargs="+acc" -lib work tb_pulse_channel_random_polynomials
|
||||
|
||||
do waves_do/pp_polyrandom.do
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
run -all
|
||||
|
||||
# End
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
do compile.do
|
||||
|
||||
vsim -voptargs="+acc" -lib work qlaser_dacs_pulse_tb
|
||||
|
||||
do waves_do/pp_qlaser_wavetables.do
|
||||
|
||||
view wave
|
||||
view structure
|
||||
view signals
|
||||
|
||||
run -all
|
||||
|
||||
# End
|
||||
Binary file not shown.
|
|
@ -1,26 +0,0 @@
|
|||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /tb_pulse_channel_random_polynomials/clk
|
||||
add wave -noupdate /tb_pulse_channel_random_polynomials/degrees
|
||||
add wave -noupdate /tb_pulse_channel_random_polynomials/times
|
||||
add wave -noupdate /tb_pulse_channel_random_polynomials/direction
|
||||
add wave -noupdate -format Analog-Backstep -height 100 -max 10280.0 -radix decimal /tb_pulse_channel_random_polynomials/wave_values
|
||||
add wave -noupdate /tb_pulse_channel_random_polynomials/wave_values_next
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {20865000000 fs} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 100
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 fs} {42845964444 fs}
|
||||
|
|
@ -1,59 +0,0 @@
|
|||
onerror {resume}
|
||||
quietly virtual signal -install /qlaser_dacs_pulse_tb/u_dac_pulse { /qlaser_dacs_pulse_tb/u_dac_pulse/reg_pulse_time(31 downto 16)} reg_pulse_time_31_16
|
||||
quietly virtual signal -install /qlaser_dacs_pulse_tb/u_dac_pulse { /qlaser_dacs_pulse_tb/u_dac_pulse/reg_pulse_time(15 downto 0)} reg_pulse_time_15_0
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/clk
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/start
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/reset
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/busy
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/cnt_time
|
||||
add wave -noupdate -radix binary /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_addr
|
||||
add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_wdata
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_wr
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_sel
|
||||
add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_rdata
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_rdata_dv
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_addra
|
||||
add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_dina
|
||||
add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_douta
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_we
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/sm_state
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/pc
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_addrb
|
||||
add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_doutb
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/reg_pulse_time
|
||||
add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/reg_scale_gain
|
||||
add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/reg_scale_time
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/reg_wave_start_addr
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/reg_wave_length
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/reg_pulse_flattop
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_wea
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_addra
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_dina
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_douta
|
||||
add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_addrb
|
||||
add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_doutb
|
||||
add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/sm_wavedata
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/sm_wavedata_dv
|
||||
add wave -noupdate -format Analog-Step -height 74 -max 204.0 -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/axis_tdata
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/axis_tvalid
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/axis_tlast
|
||||
add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/axis_tready
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {62275000000 fs} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 163
|
||||
configure wave -valuecolwidth 99
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits fs
|
||||
update
|
||||
WaveRestoreZoom {61852729312 fs} {62817270688 fs}
|
||||
|
|
@ -1,34 +0,0 @@
|
|||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy
|
||||
add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wdata
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wr
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_sel
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {480433536 fs} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 172
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits fs
|
||||
update
|
||||
WaveRestoreZoom {0 fs} {1953088753 fs}
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time
|
||||
add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wdata
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wr
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_sel
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {277726970613 fs} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 99
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits fs
|
||||
update
|
||||
WaveRestoreZoom {277686713216 fs} {277803286784 fs}
|
||||
|
|
@ -1,66 +0,0 @@
|
|||
onerror {resume}
|
||||
quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time(31 downto 16)} reg_pulse_time_31_16
|
||||
quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time(15 downto 0)} reg_pulse_time_15_0
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/start
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time
|
||||
add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wdata
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wr
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_sel
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state_d1
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_scale_gain
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_scale_time
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_wave_start_addr
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_wave_length
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_wave_end_addr
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_wea
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_addra
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_dina
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_douta
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_addr
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_wave_top
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_wave_len
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_last_addr
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_addrb
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_doutb
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_wavedata
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_wavedata_dv
|
||||
add wave -noupdate -format Analog-Step -height 74 -max 70.0 -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tdata
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tvalid
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tlast
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tready
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/done_seq
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {62521930491 fs} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 163
|
||||
configure wave -valuecolwidth 99
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits fs
|
||||
update
|
||||
WaveRestoreZoom {62366292805 fs} {63694887423 fs}
|
||||
|
|
@ -1,422 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>bram_pulse_definition</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 4.465107 mW</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynquplus</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">bram_pulse_definition.mem</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">READ_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">zynquplus</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bram_pulse_definition</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">READ_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynquplus</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">bram_waveform.mem</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">2048</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">4096</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">2048</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">4096</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">READ_FIRST</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">zynquplus</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">bram_waveform</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">READ_FIRST</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">50</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">16</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">2048</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">16</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplus</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:zcu102:part0:3.4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu9eg</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvb1156</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">5</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../prj/zcu_pulse_channel.gen/sources_1/ip/bram_waveform</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1.2</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
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||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS.TUSER_WIDTH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_PORT"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.ASSOCIATED_RESET"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.PHASE">0.0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">4</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">512x72</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">510</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">509</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_SELECT_XPM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_data_to_stream</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Builtin_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">510</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">509</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynquplus</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART">xilinx.com:zcu102:part0:3.4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xczu9eg</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffvb1156</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">E</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../prj/zcu_pulse_channel.gen/sources_1/ip/fifo_data_to_stream</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_PROT" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_QOS" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_REGION" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.M_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_CACHE" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_LOCK" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_PROT" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_QOS" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_REGION" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.HAS_TREADY" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXIS.TDATA_NUM_BYTES" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.asymmetric_port_width" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"clk": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"srst": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"din": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"wr_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"rd_en": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"dout": [ { "direction": "out", "size_left": "15", "size_right": "0", "driver_value": "0" } ],
|
||||
"full": [ { "direction": "out", "driver_value": "0x0" } ],
|
||||
"empty": [ { "direction": "out", "driver_value": "0x1" } ],
|
||||
"wr_rst_busy": [ { "direction": "out", "driver_value": "0" } ],
|
||||
"rd_rst_busy": [ { "direction": "out", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"core_clk": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "clk" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_WRITE": {
|
||||
"vlnv": "xilinx.com:interface:fifo_write:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"FULL": [ { "physical_name": "full" } ],
|
||||
"WR_DATA": [ { "physical_name": "din" } ],
|
||||
"WR_EN": [ { "physical_name": "wr_en" } ]
|
||||
}
|
||||
},
|
||||
"FIFO_READ": {
|
||||
"vlnv": "xilinx.com:interface:fifo_read:1.0",
|
||||
"abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"port_maps": {
|
||||
"EMPTY": [ { "physical_name": "empty" } ],
|
||||
"RD_DATA": [ { "physical_name": "dout" } ],
|
||||
"RD_EN": [ { "physical_name": "rd_en" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
|
|
@ -1,73 +0,0 @@
|
|||
## 300MHz Clock from USER_SI570
|
||||
set_property PACKAGE_PIN AL7 [get_ports "p_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64
|
||||
set_property IOSTANDARD DIFF_SSTL12 [get_ports "p_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64
|
||||
set_property PACKAGE_PIN AL8 [get_ports "p_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64
|
||||
set_property IOSTANDARD DIFF_SSTL12 [get_ports "p_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64
|
||||
|
||||
## Buttons SW_C
|
||||
# set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports p_reset]
|
||||
|
||||
set_property PACKAGE_PIN AG13 [get_ports "p_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44
|
||||
## LEDs
|
||||
set_property PACKAGE_PIN AG14 [get_ports "p_leds_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44
|
||||
set_property PACKAGE_PIN AF13 [get_ports "p_leds_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44
|
||||
set_property PACKAGE_PIN AE13 [get_ports "p_leds_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44
|
||||
set_property PACKAGE_PIN AJ14 [get_ports "p_leds_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44
|
||||
set_property PACKAGE_PIN AJ15 [get_ports "p_leds_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44
|
||||
set_property PACKAGE_PIN AH13 [get_ports "p_leds_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_44
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44
|
||||
|
||||
# set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[0]}]
|
||||
# set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[1]}]
|
||||
# set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[2]}]
|
||||
|
||||
# set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[0]}]
|
||||
# set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[1]}]
|
||||
# set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[2]}]
|
||||
|
||||
|
||||
## Pmod Header J55
|
||||
set_property PACKAGE_PIN A20 [get_ports "p_dc0_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47
|
||||
set_property PACKAGE_PIN B20 [get_ports "p_dc0_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47
|
||||
# set_property PACKAGE_PIN A22 [get_ports "p_dc0_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47
|
||||
set_property PACKAGE_PIN A21 [get_ports "p_dc0_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47
|
||||
set_property PACKAGE_PIN B21 [get_ports "p_dc1_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47
|
||||
set_property PACKAGE_PIN C21 [get_ports "p_dc1_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47
|
||||
# set_property PACKAGE_PIN C22 [get_ports "p_dc1_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47
|
||||
# set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47
|
||||
set_property PACKAGE_PIN D21 [get_ports "p_dc1_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47
|
||||
|
||||
## Pmod Header J87
|
||||
set_property PACKAGE_PIN D20 [get_ports "p_dc2_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_dc2_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47
|
||||
set_property PACKAGE_PIN E20 [get_ports "p_dc2_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_dc2_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47
|
||||
set_property PACKAGE_PIN E22 [get_ports "p_dc2_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_dc2_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47
|
||||
|
||||
# UART
|
||||
set_property PACKAGE_PIN E13 [get_ports "p_serial_rxd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_serial_rxd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49
|
||||
set_property PACKAGE_PIN F13 [get_ports "p_serial_txd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_serial_txd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49
|
||||
|
||||
# UART Debug (unsure, maybe just indicator LEDs?)
|
||||
set_property PACKAGE_PIN D12 [get_ports "p_debug_out[0]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_debug_out[0]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49
|
||||
set_property PACKAGE_PIN E12 [get_ports "p_debug_out[1]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports "p_debug_out[1]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49
|
||||
|
||||
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
## 125MHz Clock from Ethernet PHY
|
||||
create_clock -period 3.333 -name sys_clk_pin -waveform {0.000 1.667} -add [get_ports p_clk_p]
|
||||
create_clock -period 3.333 -name sys_clk_pin -waveform {0.000 1.667} -add [get_ports p_clk_n]
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
##---------------------------------------------------------------------------------------
|
||||
## Filename : set_usercode.xdc
|
||||
##
|
||||
## Vivado onstraint file to set user version number into the bitfile
|
||||
##---------------------------------------------------------------------------------------
|
||||
|
||||
#----------------------------------------------------------------------------------------
|
||||
#-- Usercode major revisions
|
||||
#----------------------------------------------------------------------------------------
|
||||
#-- 0x0000_NNNN : Early debug and test. No PMODs,ZMODs, DACs etc
|
||||
#-- 0x1AC0_NNNN : DC PMODs, 4? single bit pulses. NNN incremented each bitfile
|
||||
#-- 0x1DC0_NNNN : DC PMODs DAC versions. NNN incremented each bitfile
|
||||
#-- 0x2AC0_NNNN : DC PMODs, AC ZMODs. 4 channel NNN incremented each bitfile
|
||||
#-- 0x3AC0_NNNN : DC PMODs, JESD AC (16ch Abaco board) NNN incremented each bitfile
|
||||
#
|
||||
#----------------------------------------------------------------------------------------
|
||||
#-- Usercode history
|
||||
#----------------------------------------------------------------------------------------
|
||||
#-- 0x1DC0_0001 : Original release
|
||||
#-- 0x1DC0_0002 : Modified double blink and added QSPI and SD into the PS1 block
|
||||
#-- 0x1DC0_0003 : SD pins on 1.8V bank. Add SD_CD on MIO47
|
||||
#-- 0x1DC0_0004 : SD clock dropped from 100MHz to 20Mhz
|
||||
#-- 0x1DC0_0005 : Restore internal reference enable for pmod DACs
|
||||
#-- 0x3AC0_0006 : Existing working codes ported to ZCU102
|
||||
#--
|
||||
#----------------------------------------------------------------------------------------
|
||||
# In VHDL package : constant C_QLASER_VERSION : std_logic_vector(31 downto 0)
|
||||
#----------------------------------------------------------------------------------------
|
||||
set_property BITSTREAM.CONFIG.USERID 32'h3AC00006 [current_design]
|
||||
|
|
@ -1,597 +0,0 @@
|
|||
#*****************************************************************************************
|
||||
# Vivado (TM) v2018.2 (64-bit)
|
||||
#
|
||||
# build_project.tcl: Tcl script for re-creating project 'qlaser_eclypse7'
|
||||
#
|
||||
# Generated by Vivado on Thu Feb 16 16:07:58 -0800 2023
|
||||
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
|
||||
#
|
||||
# This file contains the Vivado Tcl commands for re-creating the project to the state*
|
||||
# when this script was generated. In order to re-create the project, please source this
|
||||
# file in the Vivado Tcl Shell.
|
||||
#
|
||||
# * Note that the runs in the created project will be configured the same way as the
|
||||
# original project, however they will not be launched automatically. To regenerate the
|
||||
# run results please launch the synthesis/implementation runs as needed.
|
||||
#
|
||||
#*****************************************************************************************
|
||||
# NOTE: In order to use this script for source control purposes, please make sure that the
|
||||
# following files are added to the source control system:-
|
||||
#
|
||||
# 1. This project restoration tcl script (build_project.tcl) that was generated.
|
||||
#
|
||||
# 2. The following source(s) files that were local or imported into the original project.
|
||||
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
|
||||
#
|
||||
# "D:/Work/UW-Quantum/tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/ps1.bd"
|
||||
# "D:/Work/UW-Quantum/tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/hdl/ps1_wrapper.vhd"
|
||||
# "D:/Work/UW-Quantum/tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/ip/clkpll/clkpll.xci"
|
||||
#
|
||||
# 3. The following remote source files that were added to the original project:-
|
||||
#
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_pkg.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/blink.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/clkreset.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_cpu2uart.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_serial_pkg_100MHz.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_uart.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_uart2cpu.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/qlaser_cpuint_serial.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_dac_dc_package.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_spi.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_dacs_dc.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_dacs_pulse.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_version_pkg.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_misc.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_top.vhd"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/tools/xilinx/pinout.xdc"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/tools/xilinx/set_usercode.xdc"
|
||||
# "D:/Work/UW-Quantum/github/NANO_QLASER/tools/xilinx/qlaser_timing.xdc"
|
||||
#
|
||||
#*****************************************************************************************
|
||||
|
||||
# Set the reference directory for source file relative paths (by default the value is script directory path)
|
||||
set origin_dir "."
|
||||
|
||||
# Use origin directory path location variable, if specified in the tcl shell
|
||||
if { [info exists ::origin_dir_loc] } {
|
||||
set origin_dir $::origin_dir_loc
|
||||
}
|
||||
|
||||
# Set the project name
|
||||
set _xil_proj_name_ "qlaser_eclypse7"
|
||||
|
||||
# Use project name variable, if specified in the tcl shell
|
||||
if { [info exists ::user_project_name] } {
|
||||
set _xil_proj_name_ $::user_project_name
|
||||
}
|
||||
|
||||
variable script_file
|
||||
set script_file "build_project.tcl"
|
||||
|
||||
# Help information for this script
|
||||
proc help {} {
|
||||
variable script_file
|
||||
puts "\nDescription:"
|
||||
puts "Recreate a Vivado project from this script. The created project will be"
|
||||
puts "functionally equivalent to the original project for which this script was"
|
||||
puts "generated. The script contains commands for creating a project, filesets,"
|
||||
puts "runs, adding/importing sources and setting properties on various objects.\n"
|
||||
puts "Syntax:"
|
||||
puts "$script_file"
|
||||
puts "$script_file -tclargs \[--origin_dir <path>\]"
|
||||
puts "$script_file -tclargs \[--project_name <name>\]"
|
||||
puts "$script_file -tclargs \[--help\]\n"
|
||||
puts "Usage:"
|
||||
puts "Name Description"
|
||||
puts "-------------------------------------------------------------------------"
|
||||
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
|
||||
puts " origin_dir path value is \".\", otherwise, the value"
|
||||
puts " that was set with the \"-paths_relative_to\" switch"
|
||||
puts " when this script was generated.\n"
|
||||
puts "\[--project_name <name>\] Create project with the specified name. Default"
|
||||
puts " name is the name of the project from where this"
|
||||
puts " script was generated.\n"
|
||||
puts "\[--help\] Print help information for this script"
|
||||
puts "-------------------------------------------------------------------------\n"
|
||||
exit 0
|
||||
}
|
||||
|
||||
if { $::argc > 0 } {
|
||||
for {set i 0} {$i < $::argc} {incr i} {
|
||||
set option [string trim [lindex $::argv $i]]
|
||||
switch -regexp -- $option {
|
||||
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
|
||||
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
|
||||
"--help" { help }
|
||||
default {
|
||||
if { [regexp {^-} $option] } {
|
||||
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
|
||||
return 1
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
# Set the directory path for the original project from where this script was exported
|
||||
set orig_proj_dir "[file normalize "$origin_dir/../../../../tools/Vivado2018_2/qlaser_eclypse7"]"
|
||||
|
||||
# Create project
|
||||
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg484-1
|
||||
|
||||
# Set the directory path for the new project
|
||||
set proj_dir [get_property directory [current_project]]
|
||||
|
||||
# Reconstruct message rules
|
||||
# None
|
||||
|
||||
# Set project properties
|
||||
set obj [current_project]
|
||||
set_property -name "board_part" -value "digilentinc.com:eclypse-z7:part0:1.1" -objects $obj
|
||||
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
|
||||
set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj
|
||||
set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj
|
||||
set_property -name "dsa.board_id" -value "eclypse-z7" -objects $obj
|
||||
set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj
|
||||
set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj
|
||||
set_property -name "dsa.emu_dir" -value "emu" -objects $obj
|
||||
set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj
|
||||
set_property -name "dsa.flash_offset_address" -value "0" -objects $obj
|
||||
set_property -name "dsa.flash_size" -value "1024" -objects $obj
|
||||
set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj
|
||||
set_property -name "dsa.host_interface" -value "pcie" -objects $obj
|
||||
set_property -name "dsa.num_compute_units" -value "60" -objects $obj
|
||||
set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj
|
||||
set_property -name "dsa.uses_pr" -value "1" -objects $obj
|
||||
set_property -name "dsa.vendor" -value "xilinx" -objects $obj
|
||||
set_property -name "dsa.version" -value "0.0" -objects $obj
|
||||
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
|
||||
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
|
||||
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
|
||||
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
|
||||
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
|
||||
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
|
||||
set_property -name "simulator_language" -value "Mixed" -objects $obj
|
||||
set_property -name "target_language" -value "VHDL" -objects $obj
|
||||
set_property -name "webtalk.activehdl_export_sim" -value "6" -objects $obj
|
||||
set_property -name "webtalk.ies_export_sim" -value "6" -objects $obj
|
||||
set_property -name "webtalk.modelsim_export_sim" -value "6" -objects $obj
|
||||
set_property -name "webtalk.questa_export_sim" -value "6" -objects $obj
|
||||
set_property -name "webtalk.riviera_export_sim" -value "6" -objects $obj
|
||||
set_property -name "webtalk.vcs_export_sim" -value "6" -objects $obj
|
||||
set_property -name "webtalk.xsim_export_sim" -value "6" -objects $obj
|
||||
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
|
||||
|
||||
# Create 'sources_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sources_1] ""]} {
|
||||
create_fileset -srcset sources_1
|
||||
}
|
||||
|
||||
# Set IP repository paths
|
||||
set obj [get_filesets sources_1]
|
||||
set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../../../Common/IP_GJED"]" $obj
|
||||
|
||||
# Rebuild user ip_repo's index before adding any source files
|
||||
update_ip_catalog -rebuild
|
||||
|
||||
# Set 'sources_1' fileset object
|
||||
set obj [get_filesets sources_1]
|
||||
set files [list \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_pkg.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/blink.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/clkreset.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_cpu2uart.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_serial_pkg_100MHz.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_uart.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_uart2cpu.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/serial_io/qlaser_cpuint_serial.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_dac_dc_package.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_spi.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_dacs_dc.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_dacs_pulse.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_version_pkg.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_misc.vhd"] \
|
||||
[file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_top.vhd"] \
|
||||
]
|
||||
add_files -norecurse -fileset $obj $files
|
||||
|
||||
# Add local files from the original project (-no_copy_sources specified)
|
||||
set files [list \
|
||||
[file normalize "${origin_dir}/../../../../tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/ps1.bd" ]\
|
||||
[file normalize "${origin_dir}/../../../../tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/hdl/ps1_wrapper.vhd" ]\
|
||||
]
|
||||
set added_files [add_files -fileset sources_1 $files]
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
set file "$origin_dir/../../src/hdl/fpga/qlaser_pkg.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/fpga/blink.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/fpga/clkreset.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/serial_io/nc3_cpu2uart.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/serial_io/nc3_serial_pkg_100MHz.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/serial_io/nc3_uart.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/serial_io/nc3_uart2cpu.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/serial_io/qlaser_cpuint_serial.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/fpga/qlaser_dac_dc_package.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/fpga/qlaser_spi.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/fpga/qlaser_dacs_dc.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/fpga/qlaser_dacs_pulse.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/fpga/qlaser_version_pkg.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/fpga/qlaser_misc.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
set file "$origin_dir/../../src/hdl/fpga/qlaser_top.vhd"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
|
||||
# Set 'sources_1' fileset file properties for local files
|
||||
set file "ps1/ps1.bd"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
|
||||
set file "hdl/ps1_wrapper.vhd"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "VHDL" -objects $file_obj
|
||||
|
||||
|
||||
# Set 'sources_1' fileset properties
|
||||
set obj [get_filesets sources_1]
|
||||
set_property -name "top" -value "qlaser_top" -objects $obj
|
||||
|
||||
# Set 'sources_1' fileset object
|
||||
set obj [get_filesets sources_1]
|
||||
# Add local files from the original project (-no_copy_sources specified)
|
||||
set files [list \
|
||||
[file normalize "${origin_dir}/../../../../tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/ip/clkpll/clkpll.xci" ]\
|
||||
]
|
||||
set added_files [add_files -fileset sources_1 $files]
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
# None
|
||||
|
||||
# Set 'sources_1' fileset file properties for local files
|
||||
set file "clkpll/clkpll.xci"
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
|
||||
set_property -name "registered_with_manager" -value "1" -objects $file_obj
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
|
||||
}
|
||||
|
||||
|
||||
# Create 'constrs_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet constrs_1] ""]} {
|
||||
create_fileset -constrset constrs_1
|
||||
}
|
||||
|
||||
# Set 'constrs_1' fileset object
|
||||
set obj [get_filesets constrs_1]
|
||||
|
||||
# Add/Import constrs file and set constrs file properties
|
||||
set file "[file normalize "$origin_dir/pinout.xdc"]"
|
||||
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
||||
set file "$origin_dir/pinout.xdc"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "XDC" -objects $file_obj
|
||||
|
||||
# Add/Import constrs file and set constrs file properties
|
||||
set file "[file normalize "$origin_dir/set_usercode.xdc"]"
|
||||
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
||||
set file "$origin_dir/set_usercode.xdc"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "XDC" -objects $file_obj
|
||||
|
||||
# Add/Import constrs file and set constrs file properties
|
||||
set file "[file normalize "$origin_dir/qlaser_timing.xdc"]"
|
||||
set file_added [add_files -norecurse -fileset $obj [list $file]]
|
||||
set file "$origin_dir/qlaser_timing.xdc"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
|
||||
set_property -name "file_type" -value "XDC" -objects $file_obj
|
||||
|
||||
# Set 'constrs_1' fileset properties
|
||||
set obj [get_filesets constrs_1]
|
||||
|
||||
# Create 'sim_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sim_1] ""]} {
|
||||
create_fileset -simset sim_1
|
||||
}
|
||||
|
||||
# Set 'sim_1' fileset object
|
||||
set obj [get_filesets sim_1]
|
||||
# Empty (no sources present)
|
||||
|
||||
# Set 'sim_1' fileset properties
|
||||
set obj [get_filesets sim_1]
|
||||
set_property -name "sim_mode" -value "post-implementation" -objects $obj
|
||||
set_property -name "top" -value "qlaser_top" -objects $obj
|
||||
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
|
||||
|
||||
# Create 'synth_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet synth_1] ""]} {
|
||||
create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
|
||||
} else {
|
||||
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
|
||||
set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
|
||||
}
|
||||
set obj [get_runs synth_1]
|
||||
set_property set_report_strategy_name 1 $obj
|
||||
set_property report_strategy {Vivado Synthesis Default Reports} $obj
|
||||
set_property set_report_strategy_name 0 $obj
|
||||
# Create 'synth_1_synth_report_utilization_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
|
||||
create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
set obj [get_runs synth_1]
|
||||
set_property -name "needs_refresh" -value "1" -objects $obj
|
||||
set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
|
||||
|
||||
# set the current synth run
|
||||
current_run -synthesis [get_runs synth_1]
|
||||
|
||||
# Create 'impl_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet impl_1] ""]} {
|
||||
create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
|
||||
} else {
|
||||
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
|
||||
set_property flow "Vivado Implementation 2018" [get_runs impl_1]
|
||||
}
|
||||
set obj [get_runs impl_1]
|
||||
set_property set_report_strategy_name 1 $obj
|
||||
set_property report_strategy {Vivado Implementation Default Reports} $obj
|
||||
set_property set_report_strategy_name 0 $obj
|
||||
# Create 'impl_1_init_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_opt_report_drc_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
|
||||
create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_io_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_utilization_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_control_sets_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_place_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
set_property -name "is_enabled" -value "0" -objects $obj
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_drc_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_methodology_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_power_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_route_status_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_route_report_bus_skew_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
|
||||
create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
|
||||
create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
|
||||
if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
|
||||
create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
|
||||
}
|
||||
set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
|
||||
if { $obj != "" } {
|
||||
|
||||
}
|
||||
set obj [get_runs impl_1]
|
||||
set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
|
||||
set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
|
||||
set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
|
||||
|
||||
# set the current impl run
|
||||
current_run -implementation [get_runs impl_1]
|
||||
|
||||
puts "INFO: Project created:${_xil_proj_name_}"
|
||||
|
|
@ -1,890 +0,0 @@
|
|||
|
||||
################################################################
|
||||
# This is a generated script based on design: ps1
|
||||
#
|
||||
# Though there are limitations about the generated script,
|
||||
# the main purpose of this utility is to make learning
|
||||
# IP Integrator Tcl commands easier.
|
||||
################################################################
|
||||
|
||||
namespace eval _tcl {
|
||||
proc get_script_folder {} {
|
||||
set script_path [file normalize [info script]]
|
||||
set script_folder [file dirname $script_path]
|
||||
return $script_folder
|
||||
}
|
||||
}
|
||||
variable script_folder
|
||||
set script_folder [_tcl::get_script_folder]
|
||||
|
||||
################################################################
|
||||
# Check if script is running in correct Vivado version.
|
||||
################################################################
|
||||
set scripts_vivado_version 2018.2
|
||||
set current_vivado_version [version -short]
|
||||
|
||||
if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
|
||||
puts ""
|
||||
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
|
||||
|
||||
return 1
|
||||
}
|
||||
|
||||
################################################################
|
||||
# START
|
||||
################################################################
|
||||
|
||||
# To test this script, run the following commands from Vivado Tcl console:
|
||||
# source ps1_script.tcl
|
||||
|
||||
# If there is no project opened, this script will create a
|
||||
# project, but make sure you do not have an existing project
|
||||
# <./myproj/project_1.xpr> in the current working folder.
|
||||
|
||||
set list_projs [get_projects -quiet]
|
||||
if { $list_projs eq "" } {
|
||||
create_project project_1 myproj -part xc7z020clg484-1
|
||||
set_property BOARD_PART digilentinc.com:eclypse-z7:part0:1.1 [current_project]
|
||||
}
|
||||
|
||||
|
||||
# CHANGE DESIGN NAME HERE
|
||||
variable design_name
|
||||
set design_name ps1
|
||||
|
||||
# If you do not already have an existing IP Integrator design open,
|
||||
# you can create a design using the following command:
|
||||
# create_bd_design $design_name
|
||||
|
||||
# Creating design if needed
|
||||
set errMsg ""
|
||||
set nRet 0
|
||||
|
||||
set cur_design [current_bd_design -quiet]
|
||||
set list_cells [get_bd_cells -quiet]
|
||||
|
||||
if { ${design_name} eq "" } {
|
||||
# USE CASES:
|
||||
# 1) Design_name not set
|
||||
|
||||
set errMsg "Please set the variable <design_name> to a non-empty value."
|
||||
set nRet 1
|
||||
|
||||
} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
|
||||
# USE CASES:
|
||||
# 2): Current design opened AND is empty AND names same.
|
||||
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
|
||||
# 4): Current design opened AND is empty AND names diff; design_name exists in project.
|
||||
|
||||
if { $cur_design ne $design_name } {
|
||||
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
|
||||
set design_name [get_property NAME $cur_design]
|
||||
}
|
||||
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
|
||||
|
||||
} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
|
||||
# USE CASES:
|
||||
# 5) Current design opened AND has components AND same names.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 1
|
||||
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
|
||||
# USE CASES:
|
||||
# 6) Current opened design, has components, but diff names, design_name exists in project.
|
||||
# 7) No opened design, design_name exists in project.
|
||||
|
||||
set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
|
||||
set nRet 2
|
||||
|
||||
} else {
|
||||
# USE CASES:
|
||||
# 8) No opened design, design_name not in project.
|
||||
# 9) Current opened design, has components, but diff names, design_name not in project.
|
||||
|
||||
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
|
||||
|
||||
create_bd_design $design_name
|
||||
|
||||
common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
|
||||
current_bd_design $design_name
|
||||
|
||||
}
|
||||
|
||||
common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
|
||||
|
||||
if { $nRet != 0 } {
|
||||
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
|
||||
return $nRet
|
||||
}
|
||||
|
||||
set bCheckIPsPassed 1
|
||||
##################################################################
|
||||
# CHECK IPs
|
||||
##################################################################
|
||||
set bCheckIPs 1
|
||||
if { $bCheckIPs == 1 } {
|
||||
set list_check_ips "\
|
||||
xilinx.com:ip:axi_bram_ctrl:4.*\
|
||||
xilinx.com:ip:blk_mem_gen:8.*\
|
||||
xilinx.com:ip:smartconnect:1.*\
|
||||
xilinx.com:ip:processing_system7:5.*\
|
||||
xilinx.com:ip:proc_sys_reset:5.*\
|
||||
"
|
||||
|
||||
set list_ips_missing ""
|
||||
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
|
||||
|
||||
foreach ip_vlnv $list_check_ips {
|
||||
set ip_obj [get_ipdefs -all $ip_vlnv]
|
||||
if { $ip_obj eq "" } {
|
||||
lappend list_ips_missing $ip_vlnv
|
||||
}
|
||||
}
|
||||
|
||||
if { $list_ips_missing ne "" } {
|
||||
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
|
||||
set bCheckIPsPassed 0
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if { $bCheckIPsPassed != 1 } {
|
||||
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
|
||||
return 3
|
||||
}
|
||||
|
||||
##################################################################
|
||||
# DESIGN PROCs
|
||||
##################################################################
|
||||
|
||||
|
||||
|
||||
# Procedure to create entire design; Provide argument to make
|
||||
# procedure reusable. If parentCell is "", will use root.
|
||||
proc create_root_design { parentCell } {
|
||||
|
||||
variable script_folder
|
||||
variable design_name
|
||||
|
||||
if { $parentCell eq "" } {
|
||||
set parentCell [get_bd_cells /]
|
||||
}
|
||||
|
||||
# Get object for parentCell
|
||||
set parentObj [get_bd_cells $parentCell]
|
||||
if { $parentObj == "" } {
|
||||
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
|
||||
return
|
||||
}
|
||||
|
||||
# Make sure parentObj is hier blk
|
||||
set parentType [get_property TYPE $parentObj]
|
||||
if { $parentType ne "hier" } {
|
||||
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
|
||||
return
|
||||
}
|
||||
|
||||
# Save current instance; Restore later
|
||||
set oldCurInst [current_bd_instance .]
|
||||
|
||||
# Set parent object as current
|
||||
current_bd_instance $parentObj
|
||||
|
||||
|
||||
# Create interface ports
|
||||
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
|
||||
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
|
||||
|
||||
# Create ports
|
||||
set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ]
|
||||
set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ]
|
||||
set ext_reset_n [ create_bd_port -dir I -type rst ext_reset_n ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.POLARITY {ACTIVE_LOW} \
|
||||
] $ext_reset_n
|
||||
|
||||
# Create instance: axi_bram_ctrl, and set properties
|
||||
set axi_bram_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.* axi_bram_ctrl ]
|
||||
|
||||
# Create instance: axi_bram_ctrl_bram, and set properties
|
||||
set axi_bram_ctrl_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.* axi_bram_ctrl_bram ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.Memory_Type {True_Dual_Port_RAM} \
|
||||
] $axi_bram_ctrl_bram
|
||||
|
||||
# Create instance: axi_smc, and set properties
|
||||
set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.* axi_smc ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.NUM_SI {1} \
|
||||
] $axi_smc
|
||||
|
||||
# Create instance: processing_system7_0, and set properties
|
||||
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.* processing_system7_0 ]
|
||||
set_property -dict [ list \
|
||||
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
|
||||
CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
|
||||
CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
|
||||
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
|
||||
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
|
||||
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {20.000000} \
|
||||
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
|
||||
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
|
||||
CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
|
||||
CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
|
||||
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
|
||||
CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
|
||||
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \
|
||||
CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
|
||||
CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
|
||||
CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
|
||||
CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
|
||||
CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
|
||||
CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
|
||||
CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
|
||||
CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
|
||||
CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
|
||||
CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
|
||||
CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
|
||||
CONFIG.PCW_CLK0_FREQ {100000000} \
|
||||
CONFIG.PCW_CLK1_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK2_FREQ {10000000} \
|
||||
CONFIG.PCW_CLK3_FREQ {10000000} \
|
||||
CONFIG.PCW_CORE0_FIQ_INTR {0} \
|
||||
CONFIG.PCW_CORE0_IRQ_INTR {0} \
|
||||
CONFIG.PCW_CORE1_FIQ_INTR {0} \
|
||||
CONFIG.PCW_CORE1_IRQ_INTR {0} \
|
||||
CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
|
||||
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
|
||||
CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
|
||||
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
|
||||
CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
|
||||
CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
|
||||
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
|
||||
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
|
||||
CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
|
||||
CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
|
||||
CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
|
||||
CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
|
||||
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
|
||||
CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
|
||||
CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
|
||||
CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
|
||||
CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
|
||||
CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
|
||||
CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
|
||||
CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
|
||||
CONFIG.PCW_DM_WIDTH {4} \
|
||||
CONFIG.PCW_DQS_WIDTH {4} \
|
||||
CONFIG.PCW_DQ_WIDTH {32} \
|
||||
CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
|
||||
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
|
||||
CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
|
||||
CONFIG.PCW_ENET0_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
|
||||
CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
|
||||
CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
|
||||
CONFIG.PCW_ENET1_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_ENET_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
|
||||
CONFIG.PCW_EN_4K_TIMER {0} \
|
||||
CONFIG.PCW_EN_CAN0 {0} \
|
||||
CONFIG.PCW_EN_CAN1 {0} \
|
||||
CONFIG.PCW_EN_CLK0_PORT {1} \
|
||||
CONFIG.PCW_EN_CLK1_PORT {0} \
|
||||
CONFIG.PCW_EN_CLK2_PORT {0} \
|
||||
CONFIG.PCW_EN_CLK3_PORT {0} \
|
||||
CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
|
||||
CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
|
||||
CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
|
||||
CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
|
||||
CONFIG.PCW_EN_DDR {1} \
|
||||
CONFIG.PCW_EN_EMIO_CAN0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_CAN1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_ENET0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_ENET1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_GPIO {0} \
|
||||
CONFIG.PCW_EN_EMIO_I2C0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_I2C1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_PJTAG {0} \
|
||||
CONFIG.PCW_EN_EMIO_SDIO0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_SDIO1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_SPI0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_SPI1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
|
||||
CONFIG.PCW_EN_EMIO_TRACE {0} \
|
||||
CONFIG.PCW_EN_EMIO_TTC0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_TTC1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_UART0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_UART1 {0} \
|
||||
CONFIG.PCW_EN_EMIO_WDT {0} \
|
||||
CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
|
||||
CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
|
||||
CONFIG.PCW_EN_ENET0 {0} \
|
||||
CONFIG.PCW_EN_ENET1 {0} \
|
||||
CONFIG.PCW_EN_GPIO {0} \
|
||||
CONFIG.PCW_EN_I2C0 {0} \
|
||||
CONFIG.PCW_EN_I2C1 {0} \
|
||||
CONFIG.PCW_EN_MODEM_UART0 {0} \
|
||||
CONFIG.PCW_EN_MODEM_UART1 {0} \
|
||||
CONFIG.PCW_EN_PJTAG {0} \
|
||||
CONFIG.PCW_EN_PTP_ENET0 {0} \
|
||||
CONFIG.PCW_EN_PTP_ENET1 {0} \
|
||||
CONFIG.PCW_EN_QSPI {1} \
|
||||
CONFIG.PCW_EN_RST0_PORT {1} \
|
||||
CONFIG.PCW_EN_RST1_PORT {0} \
|
||||
CONFIG.PCW_EN_RST2_PORT {0} \
|
||||
CONFIG.PCW_EN_RST3_PORT {0} \
|
||||
CONFIG.PCW_EN_SDIO0 {1} \
|
||||
CONFIG.PCW_EN_SDIO1 {0} \
|
||||
CONFIG.PCW_EN_SMC {0} \
|
||||
CONFIG.PCW_EN_SPI0 {0} \
|
||||
CONFIG.PCW_EN_SPI1 {0} \
|
||||
CONFIG.PCW_EN_TRACE {0} \
|
||||
CONFIG.PCW_EN_TTC0 {0} \
|
||||
CONFIG.PCW_EN_TTC1 {0} \
|
||||
CONFIG.PCW_EN_UART0 {1} \
|
||||
CONFIG.PCW_EN_UART1 {0} \
|
||||
CONFIG.PCW_EN_USB0 {0} \
|
||||
CONFIG.PCW_EN_USB1 {0} \
|
||||
CONFIG.PCW_EN_WDT {0} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {4} \
|
||||
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {3} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
|
||||
CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
|
||||
CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
|
||||
CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
|
||||
CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
|
||||
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
|
||||
CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
|
||||
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
|
||||
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
|
||||
CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {1} \
|
||||
CONFIG.PCW_GP0_NUM_READ_THREADS {4} \
|
||||
CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \
|
||||
CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {1} \
|
||||
CONFIG.PCW_GP1_NUM_READ_THREADS {4} \
|
||||
CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \
|
||||
CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
|
||||
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
|
||||
CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
|
||||
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \
|
||||
CONFIG.PCW_GPIO_MIO_GPIO_IO {<Select>} \
|
||||
CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
|
||||
CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
|
||||
CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
|
||||
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
|
||||
CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
|
||||
CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
|
||||
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
|
||||
CONFIG.PCW_I2C_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
|
||||
CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
|
||||
CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
|
||||
CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
|
||||
CONFIG.PCW_IOPLL_CTRL_FBDIV {36} \
|
||||
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1200.000} \
|
||||
CONFIG.PCW_IRQ_F2P_INTR {0} \
|
||||
CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
|
||||
CONFIG.PCW_MIO_14_DIRECTION {in} \
|
||||
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_14_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_14_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_15_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_15_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_15_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_1_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_1_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_1_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_2_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_2_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_2_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_3_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_3_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_3_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_40_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_40_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_40_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_41_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_41_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_41_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_42_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_42_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_42_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_43_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_43_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_43_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_44_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_44_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_44_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_45_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_45_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_45_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_47_DIRECTION {in} \
|
||||
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_MIO_47_PULLUP {enabled} \
|
||||
CONFIG.PCW_MIO_47_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_4_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_4_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_4_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_5_DIRECTION {inout} \
|
||||
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_5_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_5_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_6_DIRECTION {out} \
|
||||
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_MIO_6_PULLUP {disabled} \
|
||||
CONFIG.PCW_MIO_6_SLEW {slow} \
|
||||
CONFIG.PCW_MIO_PRIMITIVE {54} \
|
||||
CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 0#UART 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#unassigned#SD 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \
|
||||
CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#rx#tx#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#clk#cmd#data[0]#data[1]#data[2]#data[3]#unassigned#cd#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \
|
||||
CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
|
||||
CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
|
||||
CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
|
||||
CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
|
||||
CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
|
||||
CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
|
||||
CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
|
||||
CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_AR {1} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_RC {11} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_REA {1} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_RR {1} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_WC {11} \
|
||||
CONFIG.PCW_NAND_CYCLES_T_WP {1} \
|
||||
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
|
||||
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_CS0_T_CEOE {1} \
|
||||
CONFIG.PCW_NOR_CS0_T_PC {1} \
|
||||
CONFIG.PCW_NOR_CS0_T_RC {11} \
|
||||
CONFIG.PCW_NOR_CS0_T_TR {1} \
|
||||
CONFIG.PCW_NOR_CS0_T_WC {11} \
|
||||
CONFIG.PCW_NOR_CS0_T_WP {1} \
|
||||
CONFIG.PCW_NOR_CS0_WE_TIME {0} \
|
||||
CONFIG.PCW_NOR_CS1_T_CEOE {1} \
|
||||
CONFIG.PCW_NOR_CS1_T_PC {1} \
|
||||
CONFIG.PCW_NOR_CS1_T_RC {11} \
|
||||
CONFIG.PCW_NOR_CS1_T_TR {1} \
|
||||
CONFIG.PCW_NOR_CS1_T_WC {11} \
|
||||
CONFIG.PCW_NOR_CS1_T_WP {1} \
|
||||
CONFIG.PCW_NOR_CS1_WE_TIME {0} \
|
||||
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
|
||||
CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
|
||||
CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
|
||||
CONFIG.PCW_P2F_CAN0_INTR {0} \
|
||||
CONFIG.PCW_P2F_CAN1_INTR {0} \
|
||||
CONFIG.PCW_P2F_CTI_INTR {0} \
|
||||
CONFIG.PCW_P2F_DMAC0_INTR {0} \
|
||||
CONFIG.PCW_P2F_DMAC1_INTR {0} \
|
||||
CONFIG.PCW_P2F_DMAC2_INTR {0} \
|
||||
CONFIG.PCW_P2F_DMAC3_INTR {0} \
|
||||
CONFIG.PCW_P2F_DMAC4_INTR {0} \
|
||||
CONFIG.PCW_P2F_DMAC5_INTR {0} \
|
||||
CONFIG.PCW_P2F_DMAC6_INTR {0} \
|
||||
CONFIG.PCW_P2F_DMAC7_INTR {0} \
|
||||
CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
|
||||
CONFIG.PCW_P2F_ENET0_INTR {0} \
|
||||
CONFIG.PCW_P2F_ENET1_INTR {0} \
|
||||
CONFIG.PCW_P2F_GPIO_INTR {0} \
|
||||
CONFIG.PCW_P2F_I2C0_INTR {0} \
|
||||
CONFIG.PCW_P2F_I2C1_INTR {0} \
|
||||
CONFIG.PCW_P2F_QSPI_INTR {0} \
|
||||
CONFIG.PCW_P2F_SDIO0_INTR {0} \
|
||||
CONFIG.PCW_P2F_SDIO1_INTR {0} \
|
||||
CONFIG.PCW_P2F_SMC_INTR {0} \
|
||||
CONFIG.PCW_P2F_SPI0_INTR {0} \
|
||||
CONFIG.PCW_P2F_SPI1_INTR {0} \
|
||||
CONFIG.PCW_P2F_UART0_INTR {0} \
|
||||
CONFIG.PCW_P2F_UART1_INTR {0} \
|
||||
CONFIG.PCW_P2F_USB0_INTR {0} \
|
||||
CONFIG.PCW_P2F_USB1_INTR {0} \
|
||||
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.063} \
|
||||
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.062} \
|
||||
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.065} \
|
||||
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.083} \
|
||||
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.007} \
|
||||
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.010} \
|
||||
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.006} \
|
||||
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.048} \
|
||||
CONFIG.PCW_PACKAGE_NAME {clg484} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {6} \
|
||||
CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \
|
||||
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
|
||||
CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
|
||||
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
|
||||
CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
|
||||
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {6} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
||||
CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
|
||||
CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
|
||||
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
|
||||
CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
|
||||
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
|
||||
CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
|
||||
CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
|
||||
CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
|
||||
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
|
||||
CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
|
||||
CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
|
||||
CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {60} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {20} \
|
||||
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
|
||||
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
|
||||
CONFIG.PCW_SMC_CYCLE_T0 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T1 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T2 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T3 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T4 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T5 {NA} \
|
||||
CONFIG.PCW_SMC_CYCLE_T6 {NA} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
|
||||
CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
|
||||
CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
|
||||
CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
|
||||
CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
|
||||
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
|
||||
CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
|
||||
CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
|
||||
CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
|
||||
CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
|
||||
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
|
||||
CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
|
||||
CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
|
||||
CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
|
||||
CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
|
||||
CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
|
||||
CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
|
||||
CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
|
||||
CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
|
||||
CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
|
||||
CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
|
||||
CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
|
||||
CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
|
||||
CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
|
||||
CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
|
||||
CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
|
||||
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
|
||||
CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
|
||||
CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
|
||||
CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
|
||||
CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
|
||||
CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
|
||||
CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
|
||||
CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
|
||||
CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
|
||||
CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
|
||||
CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
|
||||
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
|
||||
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
|
||||
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
|
||||
CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
|
||||
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
|
||||
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
|
||||
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
|
||||
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
|
||||
CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
|
||||
CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
|
||||
CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
|
||||
CONFIG.PCW_UART0_BAUD_RATE {115200} \
|
||||
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
|
||||
CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
|
||||
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
|
||||
CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
|
||||
CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
|
||||
CONFIG.PCW_UART1_BAUD_RATE {115200} \
|
||||
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
|
||||
CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
|
||||
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {12} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
||||
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
|
||||
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_AL {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BL {8} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.25} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.25} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.25} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.25} \
|
||||
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CL {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {61.0905} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {61.0905} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {61.0905} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {61.0905} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
|
||||
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {68.4725} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {71.086} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {66.794} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {108.7385} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {64.1705} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {63.686} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {68.46} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {105.4895} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
|
||||
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
|
||||
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333} \
|
||||
CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
|
||||
CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
|
||||
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
|
||||
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
|
||||
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
|
||||
CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
|
||||
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
|
||||
CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
|
||||
CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
|
||||
CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
|
||||
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
|
||||
CONFIG.PCW_USB0_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
|
||||
CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
|
||||
CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
|
||||
CONFIG.PCW_USB1_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_USB_RESET_ENABLE {0} \
|
||||
CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
|
||||
CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
|
||||
CONFIG.PCW_USE_AXI_NONSECURE {0} \
|
||||
CONFIG.PCW_USE_CORESIGHT {0} \
|
||||
CONFIG.PCW_USE_CROSS_TRIGGER {0} \
|
||||
CONFIG.PCW_USE_CR_FABRIC {1} \
|
||||
CONFIG.PCW_USE_DDR_BYPASS {0} \
|
||||
CONFIG.PCW_USE_DEBUG {0} \
|
||||
CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
|
||||
CONFIG.PCW_USE_DMA0 {0} \
|
||||
CONFIG.PCW_USE_DMA1 {0} \
|
||||
CONFIG.PCW_USE_DMA2 {0} \
|
||||
CONFIG.PCW_USE_DMA3 {0} \
|
||||
CONFIG.PCW_USE_EXPANDED_IOP {0} \
|
||||
CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
|
||||
CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
|
||||
CONFIG.PCW_USE_HIGH_OCM {0} \
|
||||
CONFIG.PCW_USE_M_AXI_GP0 {1} \
|
||||
CONFIG.PCW_USE_M_AXI_GP1 {0} \
|
||||
CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
|
||||
CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
|
||||
CONFIG.PCW_USE_S_AXI_ACP {0} \
|
||||
CONFIG.PCW_USE_S_AXI_GP0 {0} \
|
||||
CONFIG.PCW_USE_S_AXI_GP1 {0} \
|
||||
CONFIG.PCW_USE_S_AXI_HP0 {0} \
|
||||
CONFIG.PCW_USE_S_AXI_HP1 {0} \
|
||||
CONFIG.PCW_USE_S_AXI_HP2 {0} \
|
||||
CONFIG.PCW_USE_S_AXI_HP3 {0} \
|
||||
CONFIG.PCW_USE_TRACE {0} \
|
||||
CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
|
||||
CONFIG.PCW_VALUE_SILVERSION {3} \
|
||||
CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
|
||||
CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
|
||||
CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
|
||||
CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
|
||||
] $processing_system7_0
|
||||
|
||||
# Create instance: rst_ps7_0_100M, and set properties
|
||||
set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.* rst_ps7_0_100M ]
|
||||
|
||||
# Create interface connections
|
||||
connect_bd_intf_net -intf_net axi_bram_ctrl_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_bram/BRAM_PORTA]
|
||||
connect_bd_intf_net -intf_net axi_bram_ctrl_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl/BRAM_PORTB] [get_bd_intf_pins axi_bram_ctrl_bram/BRAM_PORTB]
|
||||
connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_bram_ctrl/S_AXI] [get_bd_intf_pins axi_smc/M00_AXI]
|
||||
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
|
||||
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
|
||||
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
|
||||
|
||||
# Create port connections
|
||||
connect_bd_net -net aux_reset_in_0_1 [get_bd_ports ext_reset_n] [get_bd_pins rst_ps7_0_100M/aux_reset_in]
|
||||
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins axi_bram_ctrl/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk]
|
||||
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
|
||||
connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins axi_bram_ctrl/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn]
|
||||
|
||||
# Create address segments
|
||||
create_bd_addr_seg -range 0x00020000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_bram_ctrl/S_AXI/Mem0] SEG_axi_bram_ctrl_Mem0
|
||||
|
||||
|
||||
# Restore current instance
|
||||
current_bd_instance $oldCurInst
|
||||
|
||||
save_bd_design
|
||||
}
|
||||
# End of create_root_design()
|
||||
|
||||
|
||||
##################################################################
|
||||
# MAIN FLOW
|
||||
##################################################################
|
||||
|
||||
create_root_design ""
|
||||
|
||||
|
||||
|
|
@ -1,793 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>clkpll</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_IN_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLKFB_OUT_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN1_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.CAN_DEBUG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK_IN2_D.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.PortWidth">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.INTR.SENSITIVITY">LEVEL_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESET.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXI_RESETN.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFBOUT_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">100.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">100.00000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">outclk_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.1111111111111111</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.1111111111111111</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.1111111111111111</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.1111111111111111</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.1111111111111111</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.1111111111111111</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">42.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MIN">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________125.000____________0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">36.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">9.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZE_CLOCKING_STRUCTURE_EN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">outclk_0__100.00000______0.000______50.0______237.312____249.865</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">refclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">125.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1600.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">800.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clkpll</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">80.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">237.312</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">249.865</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">outclk_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clkpll</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">36</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">5</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">8.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">refclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">125.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">zynq</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7z020</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">clg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">10</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">../../../../Qlaser.gen/sources_1/ip/clkpll</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLK_OUT1_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMARY_PORT" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
<xilinx:boundaryDescriptionInfo>
|
||||
<xilinx:boundaryDescription xilinx:boundaryDescriptionJSON="{
|
||||
"schema": "xilinx.com:schema:json_boundary:1.0",
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"reset": [ { "direction": "in", "driver_value": "0" } ],
|
||||
"refclk": [ { "direction": "in" } ],
|
||||
"outclk_0": [ { "direction": "out" } ],
|
||||
"locked": [ { "direction": "out" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"reset": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"RST": [ { "physical_name": "reset" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_IN1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_IN1": [ { "physical_name": "refclk" } ]
|
||||
}
|
||||
},
|
||||
"clock_CLK_OUT1": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK_OUT1": [ { "physical_name": "outclk_0" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
|
|
@ -1,119 +0,0 @@
|
|||
## 125MHz Clock from Ethernet PHY
|
||||
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports p_clk]
|
||||
|
||||
## Buttons
|
||||
set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports p_reset]
|
||||
#set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { p_trigger }]; #IO_L11N_T1_SRCC Sch=btn[1]
|
||||
|
||||
## RGB LEDs
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[0]}]
|
||||
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[1]}]
|
||||
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[2]}]
|
||||
|
||||
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[0]}]
|
||||
set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[1]}]
|
||||
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[2]}]
|
||||
|
||||
|
||||
## Pmod Header JA
|
||||
set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { p_debug_out[0] }]; #IO_0 Sch=ja1_fpga
|
||||
set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { p_debug_out[1] }]; #IO_25 Sch=ja2_fpga
|
||||
set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { p_serial_txd }]; #IO_L1N_T0_AD0N Sch=ja3_fpga
|
||||
set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { p_serial_rxd }]; #IO_L1P_T0_AD0P Sch=ja4_fpga
|
||||
set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { p_dc0_cs_n }]; #IO_L2N_T0_AD8N Sch=ja7_fpga
|
||||
set_property -dict { PACKAGE_PIN F17 IOSTANDARD LVCMOS33 } [get_ports { p_dc0_mosi }]; #IO_L2P_T0_AD8P Sch=ja8_fpga
|
||||
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L3N_T0_DQS_AD1N Sch=ja9_fpga
|
||||
set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { p_dc0_sclk }]; #IO_L3P_T0_DQS_AD1P Sch=ja10_fpga
|
||||
|
||||
## Pmod Header JB
|
||||
set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { p_dc2_cs_n }]; #IO_L4N_T0 Sch=jb1_fpga
|
||||
set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { p_dc2_mosi }]; #IO_L4P_T0 Sch=jb2_fpga
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L5N_T0_AD9N Sch=jb3_fpga
|
||||
set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { p_dc2_sclk }]; #IO_L5P_T0_AD9P Sch=jb4_fpga
|
||||
set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { p_dc1_cs_n }]; #IO_L6N_T0_VREF Sch=jb7_fpga
|
||||
set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { p_dc1_mosi }]; #IO_L6P_T0 Sch=jb8_fpga
|
||||
#set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L7N_T1_AD2N Sch=jb9_fpga
|
||||
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { p_dc1_sclk }]; #IO_L7P_T1_AD2P Sch=jb10_fpga
|
||||
|
||||
# PLACEHOLDER PIN ASSIGNMENTS FOR SPI3
|
||||
#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { p_dc3_cs_n }]; #IO_L4N_T0 Sch=jb1_fpga
|
||||
#set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { p_dc3_mosi }]; #IO_L4P_T0 Sch=jb2_fpga
|
||||
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L5N_T0_AD9N Sch=jb3_fpga
|
||||
#set_property -dict { PACKAGE_PIN G21 IOSTANDARD LVCMOS33 } [get_ports { p_dc3_sclk }]; #IO_L5P_T0_AD9P Sch=jb4_fpga
|
||||
|
||||
## Syzygy Port A
|
||||
#set_property -dict { PACKAGE_PIN N20 } [get_ports { syzygy_a_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n
|
||||
#set_property -dict { PACKAGE_PIN N19 } [get_ports { syzygy_a_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p
|
||||
#set_property -dict { PACKAGE_PIN T17 } [get_ports { syzygy_a_d_n[0] }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN T16 } [get_ports { syzygy_a_d_p[0] }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN T19 } [get_ports { syzygy_a_d_n[1] }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN R19 } [get_ports { syzygy_a_d_p[1] }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN T18 } [get_ports { syzygy_a_d_n[2] }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN R18 } [get_ports { syzygy_a_d_p[2] }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN P18 } [get_ports { syzygy_a_d_n[3] }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN P17 } [get_ports { syzygy_a_d_p[3] }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN R16 } [get_ports { syzygy_a_d_n[4] }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN P16 } [get_ports { syzygy_a_d_p[4] }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN P15 } [get_ports { syzygy_a_d_n[5] }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN N15 } [get_ports { syzygy_a_d_p[5] }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN K18 } [get_ports { syzygy_a_d_n[6] }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN J18 } [get_ports { syzygy_a_d_p[6] }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN K21 } [get_ports { syzygy_a_d_n[7] }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN J20 } [get_ports { syzygy_a_d_p[7] }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN M20 } [get_ports { syzygy_a_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n
|
||||
#set_property -dict { PACKAGE_PIN M19 } [get_ports { syzygy_a_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p
|
||||
#set_property -dict { PACKAGE_PIN L19 } [get_ports { syzygy_a_s[16] }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16]
|
||||
#set_property -dict { PACKAGE_PIN K20 } [get_ports { syzygy_a_s[17] }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17]
|
||||
#set_property -dict { PACKAGE_PIN L18 } [get_ports { syzygy_a_s[18] }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18]
|
||||
#set_property -dict { PACKAGE_PIN K19 } [get_ports { syzygy_a_s[19] }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19]
|
||||
#set_property -dict { PACKAGE_PIN L22 } [get_ports { syzygy_a_s[20] }]; #IO_L10N_T1 Sch=syzygy_a_s[20]
|
||||
#set_property -dict { PACKAGE_PIN J22 } [get_ports { syzygy_a_s[21] }]; #IO_L8N_T1 Sch=syzygy_a_s[21]
|
||||
#set_property -dict { PACKAGE_PIN L21 } [get_ports { syzygy_a_s[22] }]; #IO_L10P_T1 Sch=syzygy_a_s[22]
|
||||
#set_property -dict { PACKAGE_PIN J21 } [get_ports { syzygy_a_s[23] }]; #IO_L8P_T1 Sch=syzygy_a_s[23]
|
||||
#set_property -dict { PACKAGE_PIN N22 } [get_ports { syzygy_a_s[24] }]; #IO_L16P_T2 Sch=syzygy_a_s[24]
|
||||
#set_property -dict { PACKAGE_PIN P22 } [get_ports { syzygy_a_s[25] }]; #IO_L16N_T2 Sch=syzygy_a_s[25]
|
||||
#set_property -dict { PACKAGE_PIN M21 } [get_ports { syzygy_a_s[26] }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26]
|
||||
#set_property -dict { PACKAGE_PIN M22 } [get_ports { syzygy_a_s[27] }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27]
|
||||
|
||||
## Syzygy Port B
|
||||
#set_property -dict { PACKAGE_PIN Y16 } [get_ports { syzygy_b_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_b_c2p_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W16 } [get_ports { syzygy_b_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_b_c2p_clk_p
|
||||
#set_property -dict { PACKAGE_PIN Y15 } [get_ports { syzygy_b_d_n[0] }]; #IO_L21N_T3_DQS Sch=syzygy_b_d_n[0]
|
||||
#set_property -dict { PACKAGE_PIN W15 } [get_ports { syzygy_b_d_p[0] }]; #IO_L21P_T3_DQS Sch=syzygy_b_d_p[0]
|
||||
#set_property -dict { PACKAGE_PIN W13 } [get_ports { syzygy_b_d_n[1] }]; #IO_L20N_T3 Sch=syzygy_b_d_n[1]
|
||||
#set_property -dict { PACKAGE_PIN V13 } [get_ports { syzygy_b_d_p[1] }]; #IO_L20P_T3 Sch=syzygy_b_d_p[1]
|
||||
#set_property -dict { PACKAGE_PIN AA13 } [get_ports { syzygy_b_d_n[2] }]; #IO_L23N_T3 Sch=syzygy_b_d_n[2]
|
||||
#set_property -dict { PACKAGE_PIN Y13 } [get_ports { syzygy_b_d_p[2] }]; #IO_L23P_T3 Sch=syzygy_b_d_p[2]
|
||||
#set_property -dict { PACKAGE_PIN AB15 } [get_ports { syzygy_b_d_n[3] }]; #IO_L24N_T3 Sch=syzygy_b_d_n[3]
|
||||
#set_property -dict { PACKAGE_PIN AB14 } [get_ports { syzygy_b_d_p[3] }]; #IO_L24P_T3 Sch=syzygy_b_d_p[3]
|
||||
#set_property -dict { PACKAGE_PIN AA14 } [get_ports { syzygy_b_d_n[4] }]; #IO_L22N_T3 Sch=syzygy_b_d_n[4]
|
||||
#set_property -dict { PACKAGE_PIN Y14 } [get_ports { syzygy_b_d_p[4] }]; #IO_L22P_T3 Sch=syzygy_b_d_p[4]
|
||||
#set_property -dict { PACKAGE_PIN V15 } [get_ports { syzygy_b_d_n[5] }]; #IO_L19N_T3_VREF Sch=syzygy_b_d_n[5]
|
||||
#set_property -dict { PACKAGE_PIN V14 } [get_ports { syzygy_b_d_p[5] }]; #IO_L19P_T3 Sch=syzygy_b_d_p[5]
|
||||
#set_property -dict { PACKAGE_PIN AB22 } [get_ports { syzygy_b_d_n[6] }]; #IO_L7N_T1 Sch=syzygy_b_d_n[6]
|
||||
#set_property -dict { PACKAGE_PIN AA22 } [get_ports { syzygy_b_d_p[6] }]; #IO_L7P_T1 Sch=syzygy_b_d_p[6]
|
||||
#set_property -dict { PACKAGE_PIN Y21 } [get_ports { syzygy_b_d_n[7] }]; #IO_L9N_T1_DQS Sch=syzygy_b_d_n[7]
|
||||
#set_property -dict { PACKAGE_PIN Y20 } [get_ports { syzygy_b_d_p[7] }]; #IO_L9P_T1_DQS Sch=syzygy_b_d_p[7]
|
||||
#set_property -dict { PACKAGE_PIN W18 } [get_ports { syzygy_b_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_b_p2c_clk_n
|
||||
#set_property -dict { PACKAGE_PIN W17 } [get_ports { syzygy_b_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_b_p2c_clk_p
|
||||
#set_property -dict { PACKAGE_PIN AA18 } [get_ports { syzygy_b_s[16] }]; #IO_L12N_T1_MRCC Sch=syzygy_b_s[16]
|
||||
#set_property -dict { PACKAGE_PIN AA19 } [get_ports { syzygy_b_s[17] }]; #IO_L11N_T1_SRCC Sch=syzygy_b_s[17]
|
||||
#set_property -dict { PACKAGE_PIN Y18 } [get_ports { syzygy_b_s[18] }]; #IO_L12P_T1_MRCC Sch=syzygy_b_s[18]
|
||||
#set_property -dict { PACKAGE_PIN Y19 } [get_ports { syzygy_b_s[19] }]; #IO_L11P_T1_SRCC Sch=syzygy_b_s[19]
|
||||
#set_property -dict { PACKAGE_PIN AB20 } [get_ports { syzygy_b_s[20] }]; #IO_L10N_T1 Sch=syzygy_b_s[20]
|
||||
#set_property -dict { PACKAGE_PIN AB21 } [get_ports { syzygy_b_s[21] }]; #IO_L8N_T1 Sch=syzygy_b_s[21]
|
||||
#set_property -dict { PACKAGE_PIN AB19 } [get_ports { syzygy_b_s[22] }]; #IO_L10P_T1 Sch=syzygy_b_s[22]
|
||||
#set_property -dict { PACKAGE_PIN AA21 } [get_ports { syzygy_b_s[23] }]; #IO_L8P_T1 Sch=syzygy_b_s[23]
|
||||
#set_property -dict { PACKAGE_PIN U16 } [get_ports { syzygy_b_s[24] }]; #IO_L15N_T2_DQS Sch=syzygy_b_s[24]
|
||||
#set_property -dict { PACKAGE_PIN U15 } [get_ports { syzygy_b_s[25] }]; #IO_L15P_T2_DQS Sch=syzygy_b_s[25]
|
||||
#set_property -dict { PACKAGE_PIN V17 } [get_ports { syzygy_b_s[26] }]; #IO_L16N_T2 Sch=syzygy_b_s[26]
|
||||
#set_property -dict { PACKAGE_PIN U17 } [get_ports { syzygy_b_s[27] }]; #IO_L16P_T2 Sch=syzygy_b_s[27]
|
||||
|
||||
## Crypto SDA
|
||||
#set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_L16P_T2 Sch=crypto_sda
|
||||
|
||||
## Miscellaneous
|
||||
#set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[0] }]; #IO_L18N_T2_AD13N Sch=mcu_rsvd[1]
|
||||
#set_property -dict { PACKAGE_PIN B21 IOSTANDARD LVCMOS33 } [get_ports { mcu_rsvd[1] }]; #IO_L18P_T2_AD13P Sch=mcu_rsvd[2]
|
||||
|
||||
|
||||
|
|
@ -1,838 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<bd:repository xmlns:bd="http://www.xilinx.com/bd" bd:BoundaryCRC="0xA9403ED2E5915421" bd:device="xc7z020clg484-1" bd:isValidated="true" bd:synthFlowMode="Hierarchical" bd:tool_version="2018.2" bd:top="ps1" bd:version="1.00.a">
|
||||
|
||||
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>BlockDiagram</spirit:library>
|
||||
<spirit:name>ps1</spirit:name>
|
||||
<spirit:version>1.00.a</spirit:version>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>isTop</spirit:name>
|
||||
<spirit:value spirit:format="bool" spirit:resolve="immediate">true</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>FIXED_IO</spirit:name>
|
||||
<spirit:master/>
|
||||
<spirit:busType spirit:library="display_processing_system7" spirit:name="fixedio" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:library="display_processing_system7" spirit:name="fixedio_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAN_DEBUG</spirit:name>
|
||||
<spirit:value>false</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>DDR</spirit:name>
|
||||
<spirit:master/>
|
||||
<spirit:busType spirit:library="interface" spirit:name="ddrx" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:library="interface" spirit:name="ddrx_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAN_DEBUG</spirit:name>
|
||||
<spirit:value>false</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>TIMEPERIOD_PS</spirit:name>
|
||||
<spirit:value>1250</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>MEMORY_TYPE</spirit:name>
|
||||
<spirit:value>COMPONENTS</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_WIDTH</spirit:name>
|
||||
<spirit:value>8</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CS_ENABLED</spirit:name>
|
||||
<spirit:value>true</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>DATA_MASK_ENABLED</spirit:name>
|
||||
<spirit:value>true</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>SLOT</spirit:name>
|
||||
<spirit:value>Single</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>MEM_ADDR_MAP</spirit:name>
|
||||
<spirit:value>ROW_COLUMN_BANK</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>BURST_LENGTH</spirit:name>
|
||||
<spirit:value>8</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>AXI_ARBITRATION_SCHEME</spirit:name>
|
||||
<spirit:value>TDM</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAS_LATENCY</spirit:name>
|
||||
<spirit:value>11</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CAS_WRITE_LATENCY</spirit:name>
|
||||
<spirit:value>11</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>CLK.FCLK_CLK0</spirit:name>
|
||||
<spirit:displayName>Clk</spirit:displayName>
|
||||
<spirit:description>Clock</spirit:description>
|
||||
<spirit:busType spirit:library="signal" spirit:name="clock" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:library="signal" spirit:name="clock_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>CLK</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>FCLK_CLK0</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>FREQ_HZ</spirit:name>
|
||||
<spirit:value>100000000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="user_prop"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>PHASE</spirit:name>
|
||||
<spirit:value>0.000</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
<spirit:parameter>
|
||||
<spirit:name>CLK_DOMAIN</spirit:name>
|
||||
<spirit:value>ps1_processing_system7_0_0_FCLK_CLK0</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default_prop"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>RST.FCLK_RESET0_N</spirit:name>
|
||||
<spirit:displayName>Reset</spirit:displayName>
|
||||
<spirit:description>Reset</spirit:description>
|
||||
<spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>FCLK_RESET0_N</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value>ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="default"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>RST.EXT_RESET_N</spirit:name>
|
||||
<spirit:displayName>Reset</spirit:displayName>
|
||||
<spirit:description>Reset</spirit:description>
|
||||
<spirit:busType spirit:library="signal" spirit:name="reset" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:library="signal" spirit:name="reset_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
<spirit:logicalPort>
|
||||
<spirit:name>RST</spirit:name>
|
||||
</spirit:logicalPort>
|
||||
<spirit:physicalPort>
|
||||
<spirit:name>ext_reset_n</spirit:name>
|
||||
</spirit:physicalPort>
|
||||
</spirit:portMap>
|
||||
</spirit:portMaps>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>POLARITY</spirit:name>
|
||||
<spirit:value>ACTIVE_LOW</spirit:value>
|
||||
<spirit:vendorExtensions>
|
||||
<bd:configElementInfos>
|
||||
<bd:configElementInfo bd:valueSource="user"/>
|
||||
</bd:configElementInfos>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:model>
|
||||
<spirit:views>
|
||||
<spirit:view>
|
||||
<spirit:name>BlockDiagram</spirit:name>
|
||||
<spirit:envIdentifier>:vivado.xilinx.com:</spirit:envIdentifier>
|
||||
<spirit:hierarchyRef spirit:library="BlockDiagram" spirit:name="ps1_imp" spirit:vendor="xilinx.com" spirit:version="1.00.a"/>
|
||||
</spirit:view>
|
||||
</spirit:views>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:name>FCLK_CLK0</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>FCLK_RESET0_N</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:name>ext_reset_n</spirit:name>
|
||||
<spirit:wire>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:model>
|
||||
</spirit:component>
|
||||
|
||||
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>BlockDiagram</spirit:library>
|
||||
<spirit:name>ps1_imp</spirit:name>
|
||||
<spirit:version>1.00.a</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>axi_bram_ctrl</spirit:instanceName>
|
||||
<spirit:componentRef spirit:library="ip" spirit:name="axi_bram_ctrl" spirit:vendor="xilinx.com" spirit:version="4.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="bd:xciName">ps1_axi_bram_ctrl_0_0</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<bd:hdl_attributes/>
|
||||
</spirit:componentInstance>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>axi_bram_ctrl_bram</spirit:instanceName>
|
||||
<spirit:componentRef spirit:library="ip" spirit:name="blk_mem_gen" spirit:vendor="xilinx.com" spirit:version="8.4"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="bd:xciName">ps1_axi_bram_ctrl_bram_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="Memory_Type">True_Dual_Port_RAM</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>axi_smc</spirit:instanceName>
|
||||
<spirit:componentRef spirit:library="ip" spirit:name="smartconnect" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="bd:xciName">ps1_axi_smc_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="NUM_SI">1</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>processing_system7_0</spirit:instanceName>
|
||||
<spirit:componentRef spirit:library="ip" spirit:name="processing_system7" spirit:vendor="xilinx.com" spirit:version="5.5"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="bd:xciName">ps1_processing_system7_0_0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_DDR_RAM_BASEADDR">0x00100000</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PCW_DDR_RAM_HIGHADDR">0x3FFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UART0_BASEADDR">0xE0000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UART0_HIGHADDR">0xE0000FFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SDIO0_BASEADDR">0xE0100000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SDIO0_HIGHADDR">0xE0100FFF</spirit:configurableElementValue>
|
||||
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|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_FREQ_MHZ">533.333</spirit:configurableElementValue>
|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_BOARD_DELAY0">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_BOARD_DELAY1">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_BOARD_DELAY2">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_BOARD_DELAY3">0.25</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQS_0_LENGTH_MM">0</spirit:configurableElementValue>
|
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|
||||
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|
||||
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|
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<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_0_LENGTH_MM">0</spirit:configurableElementValue>
|
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|
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|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_3_LENGTH_MM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM">0</spirit:configurableElementValue>
|
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<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH">68.4725</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH">71.086</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH">66.794</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH">108.7385</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH">64.1705</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH">63.686</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH">68.46</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH">105.4895</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH">61.0905</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH">61.0905</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH">61.0905</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH">61.0905</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY">160</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0">-0.007</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1">-0.010</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2">-0.006</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3">-0.048</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PACKAGE_DDR_BOARD_DELAY0">0.063</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PACKAGE_DDR_BOARD_DELAY1">0.062</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PACKAGE_DDR_BOARD_DELAY2">0.065</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PACKAGE_DDR_BOARD_DELAY3">0.083</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_CPU_CPU_6X4X_MAX_RANGE">667</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_CRYSTAL_PERIPHERAL_FREQMHZ">33.333333</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_APU_PERIPHERAL_FREQMHZ">666.666666</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_DCI_PERIPHERAL_FREQMHZ">10.159</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_PERIPHERAL_FREQMHZ">200</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SDIO_PERIPHERAL_FREQMHZ">20</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UART_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PCAP_PERIPHERAL_FREQMHZ">200</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_FPGA0_PERIPHERAL_FREQMHZ">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_FPGA1_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_FPGA2_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_FPGA3_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_ACT_APU_PERIPHERAL_FREQMHZ">666.666687</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_ACT_DDR_FREQ_MHZ">533.333374</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PCW_ACT_DCI_PERIPHERAL_FREQMHZ">10.158730</spirit:configurableElementValue>
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||||
<spirit:configurableElementValue spirit:referenceId="PCW_ACT_QSPI_PERIPHERAL_FREQMHZ">200.000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_SMC_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_ENET0_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_ENET1_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_USB0_PERIPHERAL_FREQMHZ">60</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_USB1_PERIPHERAL_FREQMHZ">60</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_UART_PERIPHERAL_FREQMHZ">100.000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_SPI_PERIPHERAL_FREQMHZ">10.000000</spirit:configurableElementValue>
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||||
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|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_ACT_CAN0_PERIPHERAL_FREQMHZ">23.8095</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_CAN1_PERIPHERAL_FREQMHZ">23.8095</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_I2C_PERIPHERAL_FREQMHZ">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_ACT_WDT_PERIPHERAL_FREQMHZ">111.111115</spirit:configurableElementValue>
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||||
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<spirit:configurableElementValue spirit:referenceId="PCW_ACT_TPIU_PERIPHERAL_FREQMHZ">200.000000</spirit:configurableElementValue>
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_EMIO_TTC1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_EMIO_WDT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_EMIO_TRACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_AXI_NONSECURE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_M_AXI_GP0">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_M_AXI_GP1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_S_AXI_GP0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_S_AXI_GP1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_S_AXI_ACP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_S_AXI_HP0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_S_AXI_HP1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_S_AXI_HP2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_S_AXI_HP3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_DMA0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_DMA1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_DMA2">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_DMA3">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_TRACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_CROSS_TRIGGER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_DEBUG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_CR_FABRIC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_AXI_FABRIC_IDLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_DDR_BYPASS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_FABRIC_INTERRUPT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_PROC_EVENT_BUS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_EXPANDED_IOP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_HIGH_OCM">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_PS_SLCR_REGISTERS">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USE_CORESIGHT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_EMIO_SRAM_INT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_GP0_NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_GP0_NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_GP1_NUM_WRITE_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_GP1_NUM_READ_THREADS">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UART0_BAUD_RATE">115200</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_4K_TIMER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_M_AXI_GP0_ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_M_AXI_GP0_ENABLE_STATIC_REMAP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_M_AXI_GP0_SUPPORT_NARROW_BURST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_M_AXI_GP0_THREAD_ID_WIDTH">12</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_INCLUDE_ACP_TRANS_CHECK">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_S_AXI_HP0_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_S_AXI_HP1_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_S_AXI_HP2_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_S_AXI_HP3_DATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_DDR">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_SMC">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_QSPI">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CAN0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CAN1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_ENET0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_ENET1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_GPIO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_I2C0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_I2C1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_PJTAG">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_SDIO0">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_SDIO1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_SPI0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_SPI1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_UART0">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_UART1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_MODEM_UART0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_MODEM_UART1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_TTC0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_TTC1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_WDT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_TRACE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_USB0">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_USB1">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_DQ_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_DQS_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_DM_WIDTH">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_PRIMITIVE">54</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CLK0_PORT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CLK1_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CLK2_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CLK3_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_RST0_PORT">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_RST1_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_RST2_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_RST3_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CLKTRIG0_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CLKTRIG1_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CLKTRIG2_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_EN_CLKTRIG3_PORT">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_IRQ_F2P_MODE">DIRECT</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_VALUE_SILVERSION">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_GP0_EN_MODIFIABLE_TXN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_GP1_EN_MODIFIABLE_TXN">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_IMPORT_BOARD_PRESET">None</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PERIPHERAL_BOARD_PRESET">part0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PRESET_BANK0_VOLTAGE">LVCMOS 3.3V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PRESET_BANK1_VOLTAGE">LVCMOS 1.8V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_ENABLE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_ADV_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_MEMORY_TYPE">DDR 3 (Low Voltage)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_BUS_WIDTH">32 Bit</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_BL">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_HIGH_TEMP">Normal (0-85)</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_PARTNO">MT41J256M16 RE-125</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_TRAIN_READ_GATE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_TRAIN_DATA_EYE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_CLOCK_STOP_EN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_DDR_USE_INTERNAL_VREF">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_QSPI_IO">MIO 1 .. 6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_GRP_SINGLE_SS_ENABLE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_GRP_SINGLE_SS_IO">MIO 1 .. 6</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_GRP_SS1_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SINGLE_QSPI_DATA_MODE">x4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_GRP_IO1_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_GRP_FBCLK_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_INTERNAL_HIGHADDRESS">0xFCFFFFFF</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_ENET0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_ENET1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SD0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SD0_SD0_IO">MIO 40 .. 45</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SD0_GRP_CD_ENABLE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SD0_GRP_CD_IO">MIO 47</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SD0_GRP_WP_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SD0_GRP_POW_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SD1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UART0_PERIPHERAL_ENABLE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UART0_UART0_IO">MIO 14 .. 15</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UART0_GRP_FULL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UART1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SPI0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SPI1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_CAN0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_CAN1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TRACE_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TRACE_INTERNAL_WIDTH">2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_WDT_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TTC0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TTC1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PJTAG_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USB0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USB1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_I2C0_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_I2C1_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_GPIO_PERIPHERAL_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_GPIO_MIO_GPIO_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_GPIO_EMIO_GPIO_ENABLE">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_APU_CLK_RATIO_ENABLE">6:2:1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_CPU_PERIPHERAL_CLKSRC">ARM PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_DDR_PERIPHERAL_CLKSRC">DDR PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SMC_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_QSPI_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SDIO_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UART_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SPI_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_CAN_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_FCLK0_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_FCLK1_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_FCLK2_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_FCLK3_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_ENET0_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_ENET1_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_CAN0_PERIPHERAL_CLKSRC">External</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_CAN1_PERIPHERAL_CLKSRC">External</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TPIU_PERIPHERAL_CLKSRC">External</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TTC0_CLK0_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TTC0_CLK1_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TTC0_CLK2_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TTC1_CLK0_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TTC1_CLK1_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_TTC1_CLK2_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_WDT_PERIPHERAL_CLKSRC">CPU_1X</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_DCI_PERIPHERAL_CLKSRC">DDR PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PCAP_PERIPHERAL_CLKSRC">IO PLL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_USB_RESET_POLARITY">Active Low</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_ENET_RESET_POLARITY">Active Low</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_I2C_RESET_POLARITY">Active Low</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_1_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_1_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_1_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_2_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_2_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_3_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_3_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_4_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_4_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_5_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_5_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_6_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_6_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_14_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_14_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_14_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_15_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_15_IOTYPE">LVCMOS 3.3V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_15_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_40_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_40_IOTYPE">LVCMOS 1.8V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_40_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_41_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_41_IOTYPE">LVCMOS 1.8V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_41_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_42_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_42_IOTYPE">LVCMOS 1.8V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_42_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_43_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_43_IOTYPE">LVCMOS 1.8V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_43_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_44_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_44_IOTYPE">LVCMOS 1.8V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_44_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_45_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_45_IOTYPE">LVCMOS 1.8V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_45_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_47_PULLUP">enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_47_IOTYPE">LVCMOS 1.8V</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_47_SLEW">slow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_UIPARAM_GENERATE_SUMMARY">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_TREE_PERIPHERALS">unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 0#UART 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#unassigned#SD 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_MIO_TREE_SIGNALS">unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#rx#tx#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#clk#cmd#data[0]#data[1]#data[2]#data[3]#unassigned#cd#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PS7_SI_REV">PRODUCTION</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_FPGA_FCLK0_ENABLE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS0_T_TR">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS0_T_PC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS0_T_WP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS0_T_CEOE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS0_T_WC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS0_T_RC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS0_WE_TIME">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS1_T_TR">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS1_T_PC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS1_T_WP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS1_T_CEOE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS1_T_WC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS1_T_RC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_SRAM_CS1_WE_TIME">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS0_T_TR">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS0_T_PC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS0_T_WP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS0_T_CEOE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS0_T_WC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS0_T_RC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS0_WE_TIME">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS1_T_TR">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS1_T_PC">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS1_T_WP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS1_T_CEOE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS1_T_WC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS1_T_RC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NOR_CS1_WE_TIME">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NAND_CYCLES_T_RR">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NAND_CYCLES_T_AR">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NAND_CYCLES_T_CLR">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NAND_CYCLES_T_WP">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NAND_CYCLES_T_REA">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NAND_CYCLES_T_WC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_NAND_CYCLES_T_RC">11</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SMC_CYCLE_T0">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SMC_CYCLE_T1">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SMC_CYCLE_T2">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SMC_CYCLE_T3">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SMC_CYCLE_T4">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SMC_CYCLE_T5">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_SMC_CYCLE_T6">NA</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PACKAGE_NAME">clg484</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PCW_PLL_BYPASSMODE_ENABLE">0</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<bd:hdl_attributes/>
|
||||
</spirit:componentInstance>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>rst_ps7_0_100M</spirit:instanceName>
|
||||
<spirit:componentRef spirit:library="ip" spirit:name="proc_sys_reset" spirit:vendor="xilinx.com" spirit:version="5.0"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="bd:xciName">ps1_rst_ps7_0_100M_0</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
<spirit:interconnections>
|
||||
<spirit:interconnection>
|
||||
<spirit:name>axi_bram_ctrl_BRAM_PORTA</spirit:name>
|
||||
<spirit:activeInterface spirit:busRef="BRAM_PORTA" spirit:componentRef="axi_bram_ctrl_bram"/>
|
||||
<spirit:activeInterface spirit:busRef="BRAM_PORTA" spirit:componentRef="axi_bram_ctrl"/>
|
||||
</spirit:interconnection>
|
||||
<spirit:interconnection>
|
||||
<spirit:name>axi_bram_ctrl_BRAM_PORTB</spirit:name>
|
||||
<spirit:activeInterface spirit:busRef="BRAM_PORTB" spirit:componentRef="axi_bram_ctrl_bram"/>
|
||||
<spirit:activeInterface spirit:busRef="BRAM_PORTB" spirit:componentRef="axi_bram_ctrl"/>
|
||||
</spirit:interconnection>
|
||||
<spirit:interconnection>
|
||||
<spirit:name>processing_system7_0_M_AXI_GP0</spirit:name>
|
||||
<spirit:activeInterface spirit:busRef="M_AXI_GP0" spirit:componentRef="processing_system7_0"/>
|
||||
<spirit:activeInterface spirit:busRef="S00_AXI" spirit:componentRef="axi_smc"/>
|
||||
</spirit:interconnection>
|
||||
<spirit:interconnection>
|
||||
<spirit:name>axi_smc_M00_AXI</spirit:name>
|
||||
<spirit:activeInterface spirit:busRef="M00_AXI" spirit:componentRef="axi_smc"/>
|
||||
<spirit:activeInterface spirit:busRef="S_AXI" spirit:componentRef="axi_bram_ctrl"/>
|
||||
</spirit:interconnection>
|
||||
</spirit:interconnections>
|
||||
<spirit:adHocConnections>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>processing_system7_0_FCLK_CLK0</spirit:name>
|
||||
<spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="FCLK_CLK0"/>
|
||||
<spirit:externalPortReference spirit:portRef="FCLK_CLK0"/>
|
||||
<spirit:internalPortReference spirit:componentRef="axi_bram_ctrl" spirit:portRef="s_axi_aclk"/>
|
||||
<spirit:internalPortReference spirit:componentRef="axi_smc" spirit:portRef="aclk"/>
|
||||
<spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="M_AXI_GP0_ACLK"/>
|
||||
<spirit:internalPortReference spirit:componentRef="rst_ps7_0_100M" spirit:portRef="slowest_sync_clk"/>
|
||||
</spirit:adHocConnection>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>processing_system7_0_FCLK_RESET0_N</spirit:name>
|
||||
<spirit:internalPortReference spirit:componentRef="processing_system7_0" spirit:portRef="FCLK_RESET0_N"/>
|
||||
<spirit:externalPortReference spirit:portRef="FCLK_RESET0_N"/>
|
||||
<spirit:internalPortReference spirit:componentRef="rst_ps7_0_100M" spirit:portRef="ext_reset_in"/>
|
||||
</spirit:adHocConnection>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>rst_ps7_0_100M_peripheral_aresetn</spirit:name>
|
||||
<spirit:internalPortReference spirit:componentRef="rst_ps7_0_100M" spirit:portRef="peripheral_aresetn"/>
|
||||
<spirit:internalPortReference spirit:componentRef="axi_bram_ctrl" spirit:portRef="s_axi_aresetn"/>
|
||||
<spirit:internalPortReference spirit:componentRef="axi_smc" spirit:portRef="aresetn"/>
|
||||
</spirit:adHocConnection>
|
||||
<spirit:adHocConnection>
|
||||
<spirit:name>aux_reset_in_0_1</spirit:name>
|
||||
<spirit:externalPortReference spirit:portRef="ext_reset_n"/>
|
||||
<spirit:internalPortReference spirit:componentRef="rst_ps7_0_100M" spirit:portRef="aux_reset_in"/>
|
||||
</spirit:adHocConnection>
|
||||
</spirit:adHocConnections>
|
||||
<spirit:hierConnections>
|
||||
<spirit:hierConnection spirit:interfaceRef="FIXED_IO/processing_system7_0_FIXED_IO">
|
||||
<spirit:activeInterface spirit:busRef="FIXED_IO" spirit:componentRef="processing_system7_0"/>
|
||||
</spirit:hierConnection>
|
||||
<spirit:hierConnection spirit:interfaceRef="DDR/processing_system7_0_DDR">
|
||||
<spirit:activeInterface spirit:busRef="DDR" spirit:componentRef="processing_system7_0"/>
|
||||
</spirit:hierConnection>
|
||||
</spirit:hierConnections>
|
||||
</spirit:design>
|
||||
|
||||
<spirit:component xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>Addressing/processing_system7_0</spirit:library>
|
||||
<spirit:name>processing_system7</spirit:name>
|
||||
<spirit:version>5.5</spirit:version>
|
||||
<spirit:busInterfaces>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>M_AXI_GP0</spirit:name>
|
||||
<spirit:master>
|
||||
<spirit:addressSpaceRef spirit:addressSpaceRef="Data"/>
|
||||
<spirit:baseAddress spirit:maximum="0x7FFFFFFF" spirit:minimum="0x40000000">0x40000000</spirit:baseAddress>
|
||||
</spirit:master>
|
||||
<spirit:busType spirit:library="interface" spirit:name="aximm" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:library="interface" spirit:name="aximm_rtl" spirit:vendor="xilinx.com" spirit:version="1.0"/>
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>master_id</spirit:name>
|
||||
<spirit:value>0</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:busInterface>
|
||||
</spirit:busInterfaces>
|
||||
<spirit:addressSpaces>
|
||||
<spirit:addressSpace>
|
||||
<spirit:name>Data</spirit:name>
|
||||
<spirit:range>4G</spirit:range>
|
||||
<spirit:width>32</spirit:width>
|
||||
<spirit:segments>
|
||||
<spirit:segment>
|
||||
<spirit:name>SEG_axi_bram_ctrl_Mem0</spirit:name>
|
||||
<spirit:displayName>/axi_bram_ctrl/S_AXI/Mem0</spirit:displayName>
|
||||
<spirit:addressOffset>0x40000000</spirit:addressOffset>
|
||||
<spirit:range>128K</spirit:range>
|
||||
</spirit:segment>
|
||||
</spirit:segments>
|
||||
</spirit:addressSpace>
|
||||
</spirit:addressSpaces>
|
||||
</spirit:component>
|
||||
|
||||
</bd:repository>
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
## 125MHz Clock from Ethernet PHY
|
||||
create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports p_clk]
|
||||
|
||||
|
|
@ -1,28 +0,0 @@
|
|||
##---------------------------------------------------------------------------------------
|
||||
## Filename : set_usercode.xdc
|
||||
##
|
||||
## Vivado onstraint file to set user version number into the bitfile
|
||||
##---------------------------------------------------------------------------------------
|
||||
|
||||
#----------------------------------------------------------------------------------------
|
||||
#-- Usercode major revisions
|
||||
#----------------------------------------------------------------------------------------
|
||||
#-- 0x0000_NNNN : Early debug and test. No PMODs,ZMODs, DACs etc
|
||||
#-- 0x1AC0_NNNN : DC PMODs, 4? single bit pulses. NNN incremented each bitfile
|
||||
#-- 0x1DC0_NNNN : DC PMODs DAC versions. NNN incremented each bitfile
|
||||
#-- 0x2AC0_NNNN : DC PMODs, AC ZMODs. 4 channel NNN incremented each bitfile
|
||||
#-- 0x3AC0_NNNN : DC PMODs, JESD AC (16ch Abaco board) NNN incremented each bitfile
|
||||
#
|
||||
#----------------------------------------------------------------------------------------
|
||||
#-- Usercode history
|
||||
#----------------------------------------------------------------------------------------
|
||||
#-- 0x1DC0_0001 : Original release
|
||||
#-- 0x1DC0_0002 : Modified double blink and added QSPI and SD into the PS1 block
|
||||
#-- 0x1DC0_0003 : SD pins on 1.8V bank. Add SD_CD on MIO47
|
||||
#-- 0x1DC0_0004 : SD clock dropped from 100MHz to 20Mhz
|
||||
#-- 0x1DC0_0005 : Restore internal reference enable for pmod DACs
|
||||
#--
|
||||
#----------------------------------------------------------------------------------------
|
||||
# In VHDL package : constant C_QLASER_VERSION : std_logic_vector(31 downto 0)
|
||||
#----------------------------------------------------------------------------------------
|
||||
set_property BITSTREAM.CONFIG.USERID 32'h1DC00005 [current_design]
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue