diff --git a/tools/build_src/build.tcl b/tools/build_src/build.tcl index c8e689a..37cff22 100644 --- a/tools/build_src/build.tcl +++ b/tools/build_src/build.tcl @@ -11,6 +11,7 @@ add_files {..\..\src\hdl\pkg\iopakb.vhd} read_ip {..\xilinx-zcu\bram_pulseposition\bram_pulseposition.xci} read_ip {..\xilinx-zcu\bram_waveform\bram_waveform.xci} read_ip {..\xilinx-zcu\fifo_data_to_stream\fifo_data_to_stream.xci} +read_ip {..\xilinx-zcu\bram_pulse_definition\bram_pulse_definition.xci} # upgrade_ip [get_ips -filter {SCOPE !~ "*.bd"}] generate_target all [get_ips -filter {SCOPE !~ "*.bd"}] diff --git a/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci b/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci new file mode 100644 index 0000000..eff3023 --- /dev/null +++ b/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci @@ -0,0 +1,419 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bram_pulse_definition + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 10 + 10 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 4.238151 mW + zynquplus + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + bram_pulse_definition.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 1024 + 1024 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1024 + 1024 + WRITE_FIRST + WRITE_FIRST + 32 + 32 + zynquplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + bram_pulse_definition + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 1024 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + zynquplus + xilinx.com:zcu102:part0:3.4 + + xczu9eg + ffvb1156 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + ../../../../zcu_pulse_channel.gen/sources_1/ip/bram_pulse_definition + + . + 2022.1.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/xilinx-zcu/bram_waveform/bram_waveform.xci b/tools/xilinx-zcu/bram_waveform/bram_waveform.xci index cb1d3fb..b81605f 100644 --- a/tools/xilinx-zcu/bram_waveform/bram_waveform.xci +++ b/tools/xilinx-zcu/bram_waveform/bram_waveform.xci @@ -91,8 +91,8 @@ 0 0.0 0 - 9 - 10 + 11 + 12 1 4 0 @@ -100,7 +100,7 @@ 9 0 0 - 1 + 2 NONE 0 0 @@ -114,7 +114,7 @@ 0 0 0 - Estimated Power for IP : 3.643151 mW + Estimated Power for IP : 6.91608 mW zynquplus 0 1 @@ -139,8 +139,8 @@ 2 0 1 - 512 - 1024 + 2048 + 4096 1 1 32 @@ -159,8 +159,8 @@ 0 1 1 - 512 - 1024 + 2048 + 4096 WRITE_FIRST WRITE_FIRST 32 @@ -230,7 +230,7 @@ false false false - 512 + 2048 32 16 No_ECC @@ -318,13 +318,13 @@ "clka": [ { "direction": "in", "driver_value": "0" } ], "ena": [ { "direction": "in", "driver_value": "0" } ], "wea": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "addra": [ { "direction": "in", "size_left": "8", "size_right": "0", "driver_value": "0" } ], + "addra": [ { "direction": "in", "size_left": "10", "size_right": "0", "driver_value": "0" } ], "dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], "douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], "clkb": [ { "direction": "in", "driver_value": "0" } ], "enb": [ { "direction": "in", "driver_value": "0" } ], "web": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], - "addrb": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0" } ], + "addrb": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0" } ], "dinb": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], "doutb": [ { "direction": "out", "size_left": "15", "size_right": "0" } ] },