Update qlaser_dacs_pulse_channel.vhdl
This commit is contained in:
parent
9664983050
commit
bab8f1c0d8
|
@ -286,10 +286,10 @@ begin
|
||||||
-- Output waveform from RAM , and increment the address
|
-- Output waveform from RAM , and increment the address
|
||||||
-- TODO: apply scaling factor to the address and then to the output
|
-- TODO: apply scaling factor to the address and then to the output
|
||||||
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1);
|
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1);
|
||||||
sm_wavedata <= ram_waveform_doutb;
|
|
||||||
sm_wavedata_dv <= '1';
|
|
||||||
|
|
||||||
end if;
|
end if;
|
||||||
|
sm_wavedata <= ram_waveform_doutb;
|
||||||
|
sm_wavedata_dv <= '1';
|
||||||
|
|
||||||
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
||||||
-- Hold the last address and output its data
|
-- Hold the last address and output its data
|
||||||
-- decrement from this address when finished waiting
|
-- decrement from this address when finished waiting
|
||||||
|
@ -299,33 +299,35 @@ begin
|
||||||
sm_state <= S_WAVE_DOWN;
|
sm_state <= S_WAVE_DOWN;
|
||||||
else
|
else
|
||||||
cnt_wave_top <= std_logic_vector(unsigned(cnt_wave_top) + 1);
|
cnt_wave_top <= std_logic_vector(unsigned(cnt_wave_top) + 1);
|
||||||
sm_wavedata <= ram_waveform_doutb;
|
|
||||||
sm_wavedata_dv <= '1';
|
|
||||||
end if;
|
end if;
|
||||||
|
sm_wavedata <= ram_waveform_doutb;
|
||||||
|
sm_wavedata_dv <= '1';
|
||||||
|
|
||||||
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
||||||
-- Output the falling edge of a waveform
|
-- Output the falling edge of a waveform
|
||||||
-- Hold the start address when complete
|
-- Hold the start address when complete
|
||||||
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
||||||
when S_WAVE_DOWN =>
|
when S_WAVE_DOWN =>
|
||||||
|
|
||||||
-- End of waveform?
|
-- End of waveform?
|
||||||
if (ram_waveform_addrb = v_addr_start) then
|
if (ram_waveform_addrb = v_addr_start) then
|
||||||
|
|
||||||
-- If the end of the pulse table is reached then go to idle
|
-- If the end of the pulse table is reached then go to idle
|
||||||
if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_NUM_PULSE-1,4))) then
|
if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_NUM_PULSE-1,4))) then
|
||||||
ram_pulse_addrb <= (others=>'0');
|
ram_pulse_addrb <= (others=>'0');
|
||||||
sm_state <= S_IDLE;
|
sm_state <= S_IDLE;
|
||||||
|
|
||||||
else -- increment pulse address for the next waveform
|
else -- increment pulse address for the next waveform
|
||||||
ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
|
ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
|
||||||
sm_state <= S_WAIT;
|
sm_state <= S_WAIT;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- Output waveform from RAM with decremented address
|
||||||
|
else
|
||||||
|
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - 1);
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
-- Output waveform from RAM with decremented address
|
|
||||||
else
|
|
||||||
ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - 1);
|
|
||||||
sm_wavedata <= ram_waveform_doutb;
|
sm_wavedata <= ram_waveform_doutb;
|
||||||
sm_wavedata_dv <= '1';
|
sm_wavedata_dv <= '1';
|
||||||
end if;
|
|
||||||
|
|
||||||
------------------------------------------------------------------------
|
------------------------------------------------------------------------
|
||||||
-- Default
|
-- Default
|
||||||
|
|
Loading…
Reference in New Issue