diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..cd814dc --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "digital-ide.dont-show-again.propose.issue": true +} \ No newline at end of file diff --git a/README.md b/README.md index eb8bf3e..6be4c66 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,26 @@ -# QLASER_V_EYHC +# QLASER_PULSE_CHANNEL -## Do NOT "merge" any branches. Each branch is a separate thing!!!! +RAM tables for a single QLaser pulse channel. There are two tables, one defined the pulse shape and envelope, and another stores the waveform data. + +Do NOT "merge" any branches in this repository. The branches are used to keep track of the different versions of the project. + +## Build and Run + +First, make sure Vivado is in PATH. Then, run the following commands to build the project: +```bash +vivado -mode tcl -source tools/build_src/build.tcl +``` +The build project will be in `prj` directory. If you modified the IP core, you need to close Vivado and run the above commands again. + +## Simulate in ModelSim + +Make sure you have ModelSim in PATH. Also make sure you already compiled the project and Xilinx libraries in Vivado. Make sure the `modelsim.ini` file is in `tools/sim` directory Then, run the following commands to simulate the project: +```bash +cd tools/sim +modelsim -do run.do +``` +#### Compile only (no simulation) +```bash +cd tools/sim +vsim -c -quiet -do compile.do +``` diff --git a/documents/JESD_FPGA_Clocking.vsd b/documents/JESD_FPGA_Clocking.vsd new file mode 100644 index 0000000..09c721a Binary files /dev/null and b/documents/JESD_FPGA_Clocking.vsd differ diff --git a/documents/Laser-Control-Board-Usage.vsd b/documents/Laser-Control-Board-Usage.vsd new file mode 100644 index 0000000..fdb40fa Binary files /dev/null and b/documents/Laser-Control-Board-Usage.vsd differ diff --git a/src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl b/src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl new file mode 100644 index 0000000..c2da0b1 --- /dev/null +++ b/src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl @@ -0,0 +1,1123 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2022.1.2 (win64) Build 3605665 Fri Aug 5 22:53:37 MDT 2022 +-- Date : Sun Feb 25 19:37:04 2024 +-- Host : STATIONX2 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- e:/github/PulseChannel/prj/zcu_pulse_channel.gen/sources_1/ip/bram_pulse_definition/bram_pulse_definition_sim_netlist.vhdl +-- Design : bram_pulse_definition +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xczu9eg-ffvb1156-2-e +-- -------------------------------------------------------------------------------- +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2022.1.2" +`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=128) +`protect key_block +rwYdhNNJ53nPphbLvD77j21Oeonbq6Z0erAiqk1RpPXb0zp7pHBtqKJw2C5LzglScReglQK59vz1 +e9nFqqqDUxPf09eNrABSjjyDdXG5nvsvptpVnGf3CRCuzW+BAOmx1NfRIwF2CnQO14BklTUJNi44 +Dn7FcUkW0a4jUsV5mW0= + +`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=256) +`protect key_block +ECFh14XLZtdbJi0fMKhe373qBJ/VQeNvJfLsF29/k8lNiDltxMI/hw4N8eayMNU19NYT80nndeu4 +b4GE5EogbeMZIyu4Qcr4BB27Zuf9xbMlyuLyuRxoP6fL/eDsdEfc77rluuayTPUvFb07ZGq8myXt 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+OLabgpXndYSwomcue39WrTHQ37CHn5b7DXwDjErgyNcMHcqBhZMvP1SdyQKzSxoH9f+z37MtCQWd +HUi1YvatVaNh7lM169qBqMmw/h7M5pvlwI9TSrZvdM1T8dKnu27nS8LO3Z+wN9uMmES3uu1Hn6/p +288uxEhHkrg5FEB6fghID3l3aXvYNV2Xh3bluLZKROKGY2BNSwI6B/hI/mvH7IwiDobkjfYpiXdO +j9+WfSFlrMkJVEqercdHqQtNVS1SVbaUlJffDWtAbDkr+IRm+7HGHqlNmuhmO7sXE/Z8Ki/25fnr +rjcjfqrBECHrNTAF58rZvdRgXN6IpwfUNIC3sfyrya9i4e+TJN9/W0wd117Dq14o0DLDK5ZeGg8+ +UkZt4gjtQqKLYgsuuRifjwSVqZ89qsq5VbC+2ziwz/1enBNsZ25eC1kkH+kgrdh94H1kUIcShbcr +onQkeSSDhK3VEyeY/AEoM31wQ+VBHgWvYvb5afhxVtR0avNvcw== +`protect end_protected +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity bram_pulse_definition is + port ( + clka : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 9 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); + clkb : in STD_LOGIC; + web : in STD_LOGIC_VECTOR ( 0 to 0 ); + addrb : in STD_LOGIC_VECTOR ( 9 downto 0 ); + dinb : in STD_LOGIC_VECTOR ( 31 downto 0 ); + doutb : out STD_LOGIC_VECTOR ( 31 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of bram_pulse_definition : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of bram_pulse_definition : entity is "bram_pulse_definition,blk_mem_gen_v8_4_5,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of bram_pulse_definition : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of bram_pulse_definition : entity is "blk_mem_gen_v8_4_5,Vivado 2022.1.2"; +end bram_pulse_definition; + +architecture STRUCTURE of bram_pulse_definition is + signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; + signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute C_ADDRA_WIDTH : integer; + attribute C_ADDRA_WIDTH of U0 : label is 10; + attribute C_ADDRB_WIDTH : integer; + attribute C_ADDRB_WIDTH of U0 : label is 10; + attribute C_ALGORITHM : integer; + attribute C_ALGORITHM of U0 : label is 1; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of U0 : label is 4; + attribute C_AXI_SLAVE_TYPE : integer; + attribute C_AXI_SLAVE_TYPE of U0 : label is 0; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of U0 : label is 1; + attribute C_BYTE_SIZE : integer; + attribute C_BYTE_SIZE of U0 : label is 9; + attribute C_COMMON_CLK : integer; + attribute C_COMMON_CLK of U0 : label is 1; + attribute C_COUNT_18K_BRAM : string; + attribute C_COUNT_18K_BRAM of U0 : label is "0"; + attribute C_COUNT_36K_BRAM : string; + attribute C_COUNT_36K_BRAM of U0 : label is "1"; + attribute C_CTRL_ECC_ALGO : string; + attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; + attribute C_DEFAULT_DATA : string; + attribute C_DEFAULT_DATA of U0 : label is "0"; + attribute C_DISABLE_WARN_BHV_COLL : integer; + attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; + attribute C_DISABLE_WARN_BHV_RANGE : integer; + attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; + attribute C_ELABORATION_DIR : string; + attribute C_ELABORATION_DIR of U0 : label is "./"; + attribute C_ENABLE_32BIT_ADDRESS : integer; + attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; + attribute C_EN_DEEPSLEEP_PIN : integer; + attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; + attribute C_EN_ECC_PIPE : integer; + attribute C_EN_ECC_PIPE of U0 : label is 0; + attribute C_EN_RDADDRA_CHG : integer; + attribute C_EN_RDADDRA_CHG of U0 : label is 0; + attribute C_EN_RDADDRB_CHG : integer; + attribute C_EN_RDADDRB_CHG of U0 : label is 0; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of U0 : label is 0; + attribute C_EN_SHUTDOWN_PIN : integer; + attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; + attribute C_EN_SLEEP_PIN : integer; + attribute C_EN_SLEEP_PIN of U0 : label is 0; + attribute C_EST_POWER_SUMMARY : string; + attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.465107 mW"; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "zynquplus"; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of U0 : label is 0; + attribute C_HAS_ENA : integer; + attribute C_HAS_ENA of U0 : label is 0; + attribute C_HAS_ENB : integer; + attribute C_HAS_ENB of U0 : label is 0; + attribute C_HAS_INJECTERR : integer; + attribute C_HAS_INJECTERR of U0 : label is 0; + attribute C_HAS_MEM_OUTPUT_REGS_A : integer; + attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; + attribute C_HAS_MEM_OUTPUT_REGS_B : integer; + attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; + attribute C_HAS_MUX_OUTPUT_REGS_A : integer; + attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; + attribute C_HAS_MUX_OUTPUT_REGS_B : integer; + attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; + attribute C_HAS_REGCEA : integer; + attribute C_HAS_REGCEA of U0 : label is 0; + attribute C_HAS_REGCEB : integer; + attribute C_HAS_REGCEB of U0 : label is 0; + attribute C_HAS_RSTA : integer; + attribute C_HAS_RSTA of U0 : label is 0; + attribute C_HAS_RSTB : integer; + attribute C_HAS_RSTB of U0 : label is 0; + attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; + attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; + attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; + attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; + attribute C_INITA_VAL : string; + attribute C_INITA_VAL of U0 : label is "0"; + attribute C_INITB_VAL : string; + attribute C_INITB_VAL of U0 : label is "0"; + attribute C_INIT_FILE : string; + attribute C_INIT_FILE of U0 : label is "bram_pulse_definition.mem"; + attribute C_INIT_FILE_NAME : string; + attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded"; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of U0 : label is 0; + attribute C_LOAD_INIT_FILE : integer; + attribute C_LOAD_INIT_FILE of U0 : label is 0; + attribute C_MEM_TYPE : integer; + attribute C_MEM_TYPE of U0 : label is 2; + attribute C_MUX_PIPELINE_STAGES : integer; + attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; + attribute C_PRIM_TYPE : integer; + attribute C_PRIM_TYPE of U0 : label is 1; + attribute C_READ_DEPTH_A : integer; + attribute C_READ_DEPTH_A of U0 : label is 1024; + attribute C_READ_DEPTH_B : integer; + attribute C_READ_DEPTH_B of U0 : label is 1024; + attribute C_READ_LATENCY_A : integer; + attribute C_READ_LATENCY_A of U0 : label is 1; + attribute C_READ_LATENCY_B : integer; + attribute C_READ_LATENCY_B of U0 : label is 1; + attribute C_READ_WIDTH_A : integer; + attribute C_READ_WIDTH_A of U0 : label is 32; + attribute C_READ_WIDTH_B : integer; + attribute C_READ_WIDTH_B of U0 : label is 32; + attribute C_RSTRAM_A : integer; + attribute C_RSTRAM_A of U0 : label is 0; + attribute C_RSTRAM_B : integer; + attribute C_RSTRAM_B of U0 : label is 0; + attribute C_RST_PRIORITY_A : string; + attribute C_RST_PRIORITY_A of U0 : label is "CE"; + attribute C_RST_PRIORITY_B : string; + attribute C_RST_PRIORITY_B of U0 : label is "CE"; + attribute C_SIM_COLLISION_CHECK : string; + attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; + attribute C_USE_BRAM_BLOCK : integer; + attribute C_USE_BRAM_BLOCK of U0 : label is 0; + attribute C_USE_BYTE_WEA : integer; + attribute C_USE_BYTE_WEA of U0 : label is 0; + attribute C_USE_BYTE_WEB : integer; + attribute C_USE_BYTE_WEB of U0 : label is 0; + attribute C_USE_DEFAULT_DATA : integer; + attribute C_USE_DEFAULT_DATA of U0 : label is 0; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of U0 : label is 0; + attribute C_USE_SOFTECC : integer; + attribute C_USE_SOFTECC of U0 : label is 0; + attribute C_USE_URAM : integer; + attribute C_USE_URAM of U0 : label is 0; + attribute C_WEA_WIDTH : integer; + attribute C_WEA_WIDTH of U0 : label is 1; + attribute C_WEB_WIDTH : integer; + attribute C_WEB_WIDTH of U0 : label is 1; + attribute C_WRITE_DEPTH_A : integer; + attribute C_WRITE_DEPTH_A of U0 : label is 1024; + attribute C_WRITE_DEPTH_B : integer; + attribute C_WRITE_DEPTH_B of U0 : label is 1024; + attribute C_WRITE_MODE_A : string; + attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST"; + attribute C_WRITE_MODE_B : string; + attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST"; + attribute C_WRITE_WIDTH_A : integer; + attribute C_WRITE_WIDTH_A of U0 : label is 32; + attribute C_WRITE_WIDTH_B : integer; + attribute C_WRITE_WIDTH_B of U0 : label is 32; + attribute C_XDEVICEFAMILY : string; + attribute C_XDEVICEFAMILY of U0 : label is "zynquplus"; + attribute downgradeipidentifiedwarnings of U0 : label is "yes"; + attribute is_du_within_envelope : string; + attribute is_du_within_envelope of U0 : label is "true"; + attribute x_interface_info : string; + attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; + attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; + attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; + attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; + attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; + attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; + attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN"; + attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; + attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; + attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; + attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE"; +begin +U0: entity work.bram_pulse_definition_blk_mem_gen_v8_4_5 + port map ( + addra(9 downto 0) => addra(9 downto 0), + addrb(9 downto 0) => addrb(9 downto 0), + clka => clka, + clkb => '0', + dbiterr => NLW_U0_dbiterr_UNCONNECTED, + deepsleep => '0', + dina(31 downto 0) => dina(31 downto 0), + dinb(31 downto 0) => dinb(31 downto 0), + douta(31 downto 0) => douta(31 downto 0), + doutb(31 downto 0) => doutb(31 downto 0), + eccpipece => '0', + ena => '0', + enb => '0', + injectdbiterr => '0', + injectsbiterr => '0', + rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0), + regcea => '0', + regceb => '0', + rsta => '0', + rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, + rstb => '0', + rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, + s_aclk => '0', + s_aresetn => '0', + s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_arburst(1 downto 0) => B"00", + s_axi_arid(3 downto 0) => B"0000", + s_axi_arlen(7 downto 0) => B"00000000", + s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, + s_axi_arsize(2 downto 0) => B"000", + s_axi_arvalid => '0', + s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_awburst(1 downto 0) => B"00", + s_axi_awid(3 downto 0) => B"0000", + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, + s_axi_awsize(2 downto 0) => B"000", + s_axi_awvalid => '0', + s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), + s_axi_bready => '0', + s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, + s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, + s_axi_injectdbiterr => '0', + s_axi_injectsbiterr => '0', + s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0), + s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0), + s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), + s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, + s_axi_rready => '0', + s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), + s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, + s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, + s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000", + s_axi_wlast => '0', + s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, + s_axi_wstrb(0) => '0', + s_axi_wvalid => '0', + sbiterr => NLW_U0_sbiterr_UNCONNECTED, + shutdown => '0', + sleep => '0', + wea(0) => wea(0), + web(0) => web(0) + ); +end STRUCTURE; diff --git a/src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl b/src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl new file mode 100644 index 0000000..52fc4dd --- /dev/null +++ b/src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl @@ -0,0 +1,3540 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2022.1.2 (win64) Build 3605665 Fri Aug 5 22:53:37 MDT 2022 +-- Date : Sun Feb 25 19:35:04 2024 +-- Host : STATIONX2 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- e:/github/PulseChannel/prj/zcu_pulse_channel.gen/sources_1/ip/bram_pulseposition/bram_pulseposition_sim_netlist.vhdl +-- Design : bram_pulseposition +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. 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+ attribute x_core_info : string; + attribute x_core_info of bram_pulseposition : entity is "dist_mem_gen_v8_0_13,Vivado 2022.1.2"; +end bram_pulseposition; + +architecture STRUCTURE of bram_pulseposition is + signal NLW_U0_qdpo_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 0 ); + signal NLW_U0_qspo_UNCONNECTED : STD_LOGIC_VECTOR ( 95 downto 0 ); + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "zynquplus"; + attribute C_HAS_CLK : integer; + attribute C_HAS_CLK of U0 : label is 1; + attribute C_HAS_D : integer; + attribute C_HAS_D of U0 : label is 1; + attribute C_HAS_WE : integer; + attribute C_HAS_WE of U0 : label is 1; + attribute C_MEM_TYPE : integer; + attribute C_MEM_TYPE of U0 : label is 2; + attribute c_addr_width : integer; + attribute c_addr_width of U0 : label is 4; + attribute c_default_data : string; + attribute c_default_data of U0 : label is "0"; + attribute c_depth : integer; + attribute c_depth of U0 : label is 16; + attribute c_elaboration_dir : string; + attribute c_elaboration_dir of U0 : label is "./"; + attribute c_has_dpo : integer; + attribute c_has_dpo of U0 : label is 1; + attribute c_has_dpra : integer; + attribute c_has_dpra of U0 : label is 1; + attribute c_has_i_ce : integer; + attribute c_has_i_ce of U0 : label is 0; + attribute c_has_qdpo : integer; + attribute c_has_qdpo of U0 : label is 0; + attribute c_has_qdpo_ce : integer; + attribute c_has_qdpo_ce of U0 : label is 0; + attribute c_has_qdpo_clk : integer; + attribute c_has_qdpo_clk of U0 : label is 0; + attribute c_has_qdpo_rst : integer; + attribute c_has_qdpo_rst of U0 : label is 0; + attribute c_has_qdpo_srst : integer; + attribute c_has_qdpo_srst of U0 : label is 0; + attribute c_has_qspo : integer; + attribute c_has_qspo of U0 : label is 0; + attribute c_has_qspo_ce : integer; + attribute c_has_qspo_ce of U0 : label is 0; + attribute c_has_qspo_rst : integer; + attribute c_has_qspo_rst of U0 : label is 0; + attribute c_has_qspo_srst : integer; + attribute c_has_qspo_srst of U0 : label is 0; + attribute c_has_spo : integer; + attribute c_has_spo of U0 : label is 1; + attribute c_mem_init_file : string; + attribute c_mem_init_file of U0 : label is "no_coe_file_loaded"; + attribute c_parser_type : integer; + attribute c_parser_type of U0 : label is 1; + attribute c_pipeline_stages : integer; + attribute c_pipeline_stages of U0 : label is 0; + attribute c_qce_joined : integer; + attribute c_qce_joined of U0 : label is 0; + attribute c_qualify_we : integer; + attribute c_qualify_we of U0 : label is 0; + attribute c_read_mif : integer; + attribute c_read_mif of U0 : label is 0; + attribute c_reg_a_d_inputs : integer; + attribute c_reg_a_d_inputs of U0 : label is 0; + attribute c_reg_dpra_input : integer; + attribute c_reg_dpra_input of U0 : label is 0; + attribute c_sync_enable : integer; + attribute c_sync_enable of U0 : label is 1; + attribute c_width : integer; + attribute c_width of U0 : label is 96; + attribute is_du_within_envelope : string; + attribute is_du_within_envelope of U0 : label is "true"; +begin +U0: entity work.bram_pulseposition_dist_mem_gen_v8_0_13 + port map ( + a(3 downto 0) => a(3 downto 0), + clk => clk, + d(95 downto 0) => d(95 downto 0), + dpo(95 downto 0) => dpo(95 downto 0), + dpra(3 downto 0) => dpra(3 downto 0), + i_ce => '1', + qdpo(95 downto 0) => NLW_U0_qdpo_UNCONNECTED(95 downto 0), + qdpo_ce => '1', + qdpo_clk => '0', + qdpo_rst => '0', + qdpo_srst => '0', + qspo(95 downto 0) => NLW_U0_qspo_UNCONNECTED(95 downto 0), + qspo_ce => '1', + qspo_rst => '0', + qspo_srst => '0', + spo(95 downto 0) => spo(95 downto 0), + we => we + ); +end STRUCTURE; diff --git a/src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl b/src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl new file mode 100644 index 0000000..f4eb062 --- /dev/null +++ b/src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl @@ -0,0 +1,1503 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2022.1.2 (win64) Build 3605665 Fri Aug 5 22:53:37 MDT 2022 +-- Date : Sun Feb 25 19:35:45 2024 +-- Host : STATIONX2 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- e:/github/PulseChannel/prj/zcu_pulse_channel.gen/sources_1/ip/bram_waveform/bram_waveform_sim_netlist.vhdl +-- Design : bram_waveform +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xczu9eg-ffvb1156-2-e +-- -------------------------------------------------------------------------------- +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2022.1.2" +`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=128) +`protect key_block +rwYdhNNJ53nPphbLvD77j21Oeonbq6Z0erAiqk1RpPXb0zp7pHBtqKJw2C5LzglScReglQK59vz1 +e9nFqqqDUxPf09eNrABSjjyDdXG5nvsvptpVnGf3CRCuzW+BAOmx1NfRIwF2CnQO14BklTUJNi44 +Dn7FcUkW0a4jUsV5mW0= + +`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=256) +`protect key_block +ECFh14XLZtdbJi0fMKhe373qBJ/VQeNvJfLsF29/k8lNiDltxMI/hw4N8eayMNU19NYT80nndeu4 +b4GE5EogbeMZIyu4Qcr4BB27Zuf9xbMlyuLyuRxoP6fL/eDsdEfc77rluuayTPUvFb07ZGq8myXt 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+4Zeon62oM4dcB3pjdE9A77pNGhwdwb2JPeLzpg3licvoEGJ5rDsYsoqr3s0UhA1RoWg/44V1I0Ih +3vHQQ0nxge60WfFHjumPxdQ3R6NdcWjNYuPbpSJ4a2BZJgqsoF9hmEHE8oZI4294rC6WAqDNrhZj +8QXBDt3lrnE64nFi4dDQTPXhPnRtR6s3qCLRX+mpiyKny1UIb0iQPW8GilzmYP4NwwqniXWbVRdx +`protect end_protected +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity bram_waveform is + port ( + clka : in STD_LOGIC; + wea : in STD_LOGIC_VECTOR ( 0 to 0 ); + addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); + dina : in STD_LOGIC_VECTOR ( 31 downto 0 ); + douta : out STD_LOGIC_VECTOR ( 31 downto 0 ); + clkb : in STD_LOGIC; + web : in STD_LOGIC_VECTOR ( 0 to 0 ); + addrb : in STD_LOGIC_VECTOR ( 11 downto 0 ); + dinb : in STD_LOGIC_VECTOR ( 15 downto 0 ); + doutb : out STD_LOGIC_VECTOR ( 15 downto 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of bram_waveform : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of bram_waveform : entity is "bram_waveform,blk_mem_gen_v8_4_5,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of bram_waveform : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of bram_waveform : entity is "blk_mem_gen_v8_4_5,Vivado 2022.1.2"; +end bram_waveform; + +architecture STRUCTURE of bram_waveform is + signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; + signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); + signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute C_ADDRA_WIDTH : integer; + attribute C_ADDRA_WIDTH of U0 : label is 11; + attribute C_ADDRB_WIDTH : integer; + attribute C_ADDRB_WIDTH of U0 : label is 12; + attribute C_ALGORITHM : integer; + attribute C_ALGORITHM of U0 : label is 1; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of U0 : label is 4; + attribute C_AXI_SLAVE_TYPE : integer; + attribute C_AXI_SLAVE_TYPE of U0 : label is 0; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of U0 : label is 1; + attribute C_BYTE_SIZE : integer; + attribute C_BYTE_SIZE of U0 : label is 9; + attribute C_COMMON_CLK : integer; + attribute C_COMMON_CLK of U0 : label is 1; + attribute C_COUNT_18K_BRAM : string; + attribute C_COUNT_18K_BRAM of U0 : label is "0"; + attribute C_COUNT_36K_BRAM : string; + attribute C_COUNT_36K_BRAM of U0 : label is "2"; + attribute C_CTRL_ECC_ALGO : string; + attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; + attribute C_DEFAULT_DATA : string; + attribute C_DEFAULT_DATA of U0 : label is "0"; + attribute C_DISABLE_WARN_BHV_COLL : integer; + attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; + attribute C_DISABLE_WARN_BHV_RANGE : integer; + attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; + attribute C_ELABORATION_DIR : string; + attribute C_ELABORATION_DIR of U0 : label is "./"; + attribute C_ENABLE_32BIT_ADDRESS : integer; + attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; + attribute C_EN_DEEPSLEEP_PIN : integer; + attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; + attribute C_EN_ECC_PIPE : integer; + attribute C_EN_ECC_PIPE of U0 : label is 0; + attribute C_EN_RDADDRA_CHG : integer; + attribute C_EN_RDADDRA_CHG of U0 : label is 0; + attribute C_EN_RDADDRB_CHG : integer; + attribute C_EN_RDADDRB_CHG of U0 : label is 0; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of U0 : label is 0; + attribute C_EN_SHUTDOWN_PIN : integer; + attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; + attribute C_EN_SLEEP_PIN : integer; + attribute C_EN_SLEEP_PIN of U0 : label is 0; + attribute C_EST_POWER_SUMMARY : string; + attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 7.369992 mW"; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "zynquplus"; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of U0 : label is 0; + attribute C_HAS_ENA : integer; + attribute C_HAS_ENA of U0 : label is 0; + attribute C_HAS_ENB : integer; + attribute C_HAS_ENB of U0 : label is 0; + attribute C_HAS_INJECTERR : integer; + attribute C_HAS_INJECTERR of U0 : label is 0; + attribute C_HAS_MEM_OUTPUT_REGS_A : integer; + attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; + attribute C_HAS_MEM_OUTPUT_REGS_B : integer; + attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; + attribute C_HAS_MUX_OUTPUT_REGS_A : integer; + attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; + attribute C_HAS_MUX_OUTPUT_REGS_B : integer; + attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; + attribute C_HAS_REGCEA : integer; + attribute C_HAS_REGCEA of U0 : label is 0; + attribute C_HAS_REGCEB : integer; + attribute C_HAS_REGCEB of U0 : label is 0; + attribute C_HAS_RSTA : integer; + attribute C_HAS_RSTA of U0 : label is 0; + attribute C_HAS_RSTB : integer; + attribute C_HAS_RSTB of U0 : label is 0; + attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; + attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; + attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; + attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; + attribute C_INITA_VAL : string; + attribute C_INITA_VAL of U0 : label is "0"; + attribute C_INITB_VAL : string; + attribute C_INITB_VAL of U0 : label is "0"; + attribute C_INIT_FILE : string; + attribute C_INIT_FILE of U0 : label is "bram_waveform.mem"; + attribute C_INIT_FILE_NAME : string; + attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded"; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of U0 : label is 0; + attribute C_LOAD_INIT_FILE : integer; + attribute C_LOAD_INIT_FILE of U0 : label is 0; + attribute C_MEM_TYPE : integer; + attribute C_MEM_TYPE of U0 : label is 2; + attribute C_MUX_PIPELINE_STAGES : integer; + attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; + attribute C_PRIM_TYPE : integer; + attribute C_PRIM_TYPE of U0 : label is 1; + attribute C_READ_DEPTH_A : integer; + attribute C_READ_DEPTH_A of U0 : label is 2048; + attribute C_READ_DEPTH_B : integer; + attribute C_READ_DEPTH_B of U0 : label is 4096; + attribute C_READ_LATENCY_A : integer; + attribute C_READ_LATENCY_A of U0 : label is 1; + attribute C_READ_LATENCY_B : integer; + attribute C_READ_LATENCY_B of U0 : label is 1; + attribute C_READ_WIDTH_A : integer; + attribute C_READ_WIDTH_A of U0 : label is 32; + attribute C_READ_WIDTH_B : integer; + attribute C_READ_WIDTH_B of U0 : label is 16; + attribute C_RSTRAM_A : integer; + attribute C_RSTRAM_A of U0 : label is 0; + attribute C_RSTRAM_B : integer; + attribute C_RSTRAM_B of U0 : label is 0; + attribute C_RST_PRIORITY_A : string; + attribute C_RST_PRIORITY_A of U0 : label is "CE"; + attribute C_RST_PRIORITY_B : string; + attribute C_RST_PRIORITY_B of U0 : label is "CE"; + attribute C_SIM_COLLISION_CHECK : string; + attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; + attribute C_USE_BRAM_BLOCK : integer; + attribute C_USE_BRAM_BLOCK of U0 : label is 0; + attribute C_USE_BYTE_WEA : integer; + attribute C_USE_BYTE_WEA of U0 : label is 0; + attribute C_USE_BYTE_WEB : integer; + attribute C_USE_BYTE_WEB of U0 : label is 0; + attribute C_USE_DEFAULT_DATA : integer; + attribute C_USE_DEFAULT_DATA of U0 : label is 0; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of U0 : label is 0; + attribute C_USE_SOFTECC : integer; + attribute C_USE_SOFTECC of U0 : label is 0; + attribute C_USE_URAM : integer; + attribute C_USE_URAM of U0 : label is 0; + attribute C_WEA_WIDTH : integer; + attribute C_WEA_WIDTH of U0 : label is 1; + attribute C_WEB_WIDTH : integer; + attribute C_WEB_WIDTH of U0 : label is 1; + attribute C_WRITE_DEPTH_A : integer; + attribute C_WRITE_DEPTH_A of U0 : label is 2048; + attribute C_WRITE_DEPTH_B : integer; + attribute C_WRITE_DEPTH_B of U0 : label is 4096; + attribute C_WRITE_MODE_A : string; + attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST"; + attribute C_WRITE_MODE_B : string; + attribute C_WRITE_MODE_B of U0 : label is "READ_FIRST"; + attribute C_WRITE_WIDTH_A : integer; + attribute C_WRITE_WIDTH_A of U0 : label is 32; + attribute C_WRITE_WIDTH_B : integer; + attribute C_WRITE_WIDTH_B of U0 : label is 16; + attribute C_XDEVICEFAMILY : string; + attribute C_XDEVICEFAMILY of U0 : label is "zynquplus"; + attribute downgradeipidentifiedwarnings of U0 : label is "yes"; + attribute is_du_within_envelope : string; + attribute is_du_within_envelope of U0 : label is "true"; + attribute x_interface_info : string; + attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; + attribute x_interface_info of clkb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; + attribute x_interface_parameter of clkb : signal is "XIL_INTERFACENAME BRAM_PORTB, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1"; + attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; + attribute x_interface_info of addrb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; + attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; + attribute x_interface_info of dinb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN"; + attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; + attribute x_interface_info of doutb : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; + attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; + attribute x_interface_info of web : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTB WE"; +begin +U0: entity work.bram_waveform_blk_mem_gen_v8_4_5 + port map ( + addra(10 downto 0) => addra(10 downto 0), + addrb(11 downto 0) => addrb(11 downto 0), + clka => clka, + clkb => '0', + dbiterr => NLW_U0_dbiterr_UNCONNECTED, + deepsleep => '0', + dina(31 downto 0) => dina(31 downto 0), + dinb(15 downto 0) => dinb(15 downto 0), + douta(31 downto 0) => douta(31 downto 0), + doutb(15 downto 0) => doutb(15 downto 0), + eccpipece => '0', + ena => '0', + enb => '0', + injectdbiterr => '0', + injectsbiterr => '0', + rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0), + regcea => '0', + regceb => '0', + rsta => '0', + rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, + rstb => '0', + rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, + s_aclk => '0', + s_aresetn => '0', + s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_arburst(1 downto 0) => B"00", + s_axi_arid(3 downto 0) => B"0000", + s_axi_arlen(7 downto 0) => B"00000000", + s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, + s_axi_arsize(2 downto 0) => B"000", + s_axi_arvalid => '0', + s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_awburst(1 downto 0) => B"00", + s_axi_awid(3 downto 0) => B"0000", + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, + s_axi_awsize(2 downto 0) => B"000", + s_axi_awvalid => '0', + s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), + s_axi_bready => '0', + s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, + s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, + s_axi_injectdbiterr => '0', + s_axi_injectsbiterr => '0', + s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0), + s_axi_rdata(15 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(15 downto 0), + s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), + s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, + s_axi_rready => '0', + s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), + s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, + s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, + s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000", + s_axi_wlast => '0', + s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, + s_axi_wstrb(0) => '0', + s_axi_wvalid => '0', + sbiterr => NLW_U0_sbiterr_UNCONNECTED, + shutdown => '0', + sleep => '0', + wea(0) => wea(0), + web(0) => web(0) + ); +end STRUCTURE; diff --git a/src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl b/src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl new file mode 100644 index 0000000..7b0a8c6 --- /dev/null +++ b/src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl @@ -0,0 +1,2207 @@ +-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2022.1.2 (win64) Build 3605665 Fri Aug 5 22:53:37 MDT 2022 +-- Date : Sun Feb 25 19:36:22 2024 +-- Host : STATIONX2 running 64-bit major release (build 9200) +-- Command : write_vhdl -force -mode funcsim +-- e:/github/PulseChannel/prj/zcu_pulse_channel.gen/sources_1/ip/fifo_data_to_stream/fifo_data_to_stream_sim_netlist.vhdl +-- Design : fifo_data_to_stream +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xczu9eg-ffvb1156-2-e +-- -------------------------------------------------------------------------------- +`protect begin_protected +`protect version = 1 +`protect encrypt_agent = "XILINX" +`protect encrypt_agent_info = "Xilinx Encryption Tool 2022.1.2" +`protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=128) +`protect key_block +BPCTeWzWQR1Yr4NUhz9wjArBJcKSr225+dWtUl60ahf41vMv2w2wtnVldO7D/JfqKVM6SOr7vcE6 +uskIj4JfXQ2fpmAMCOmxS8/6iwA/BP18jtjBpOoGMy3NhUAEFt+mVp6dA2eq4srdV4jMhb6/I/gb +kNoplPsr9nL4GSPzl5k= + +`protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=256) +`protect key_block +1vvkeKFTWNRaeDgIqh3MubasZ3Hr8zKOYsXwzpIzvSMDkYxMjRl2EoMt/mTRcmvnxBoY6E/qnnwb ++xT5TrGA1RL6wvd5UiOjHdSc8bs6xcX8TsyiUVJVvKrvXVoq8Y7mPIr+uSuY9WdIJqyJ1ZsC8QrX +/hbbl0SBDpW1FvrHTdJN4mEiwKDr3gUH8u60RdV8g4ylawrEdpPQCpMMoH1LNp/PcZw9Z1nOzot8 +4PbMoPsUxrbSg8s0G+BgBD4g72Z+H2mCWpeJlwH1NG+2F5tb3nVmVG3wPB7JvYcTQDdBKhh6Sg49 +VC8X6ykkmUmj2YC1wKD9oKvRn+AU36PtP8Rt0Q== + +`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=128) +`protect key_block +eNq+I/lLvlmQ5jyI+7OqLNtmHUReTGI1lVXcWpVTvYdaQ+9wQIOA09QiTqm4rdJ/0Wq1r8BVWv1a +yrrXBaoilbU/SX2aJn569SAo60MVh8ofge3JVUJgyNkZZpA/ltm5UQcsuFQhjXfRG8nF1CryCNJb +fb33VREa0GHzqzCpo9U= + +`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=256) +`protect key_block +FHT8VOlK3qQyuZtp7l7GWPuxUNkawQhb7k8mhEzmHldkGfkqKpbC5K4RKv+plkE3ICbBfw/tDs6k +8RpzTDrASok7fHtKIiWMRgpWOGu6AVyA4unPb1Ed9iT+FXPs0NC1OH5x7Ec2MnUqykdmBXSmHYny +Km072qMbC3lL5Xgzby5nv/urRSn5Hmf1s5i0hjVyctgAa2k3Oh+OcdmSf9wrWm0zkiaxgPo7G3za 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+`protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=256) +`protect key_block +zaw+x9uVa4VRGjRrYX66D/C+Ot+IJHGmstAMVehc9jee5UcEGmhyaGS1jUySFlLTbzQcJ9FWMupc +fZubLAdoRN8YxNq3iOciKmpB1SCnx3V2J1w1DqS90DjzCEs3foabHSwiPL3ZmSKVBAaHVdPfqe5W +0xzHOdnHhG+y8IyCuZCfOFjoOm91LWRiPE2zSGB9UayTmoin+l5HFX+9159tGmlg7AxoW5h5XxxL +DHZqE1ZB+HXNdqv7FD4lTtRv+uCZm9GWM+BkBdrxeZQ5uFsnL8Sm5Gd9SEQZ3KLbwfhcXpoqilrB +cdvt5xt/lqzmPp8AHiQYi3Z6WoH/O6UYi+6PIA== + +`protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa" +`protect encoding = (enctype="BASE64", line_length=76, bytes=256) +`protect key_block +LfSq+TCZ017XZJ7TxY3o+n/leLAE95+dvwRL7Ew/B+XW2ecA6cA94XmC1d8r+0Co652ZA5fm/rQZ +M58ZC8o2ack2Wm2aBxcOSxYHu0QQF4MVqkQ3tHhzhsEbOAEOKmbnn4822Ow8sgxHMTm07duF9xrq +s/sFQcrH5isFE6kdlFN6RQwf6mTo6qyOo+r0NY/Cqf/F3TFR+BVTkv+GuyfhKi97sbTBQWJZLVs5 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++IEej/EuYmXzDORfy30399uH7LfgKof27cnozZ0P4pHzg/8TmdbBXTazx6GBcwx3tK68lrU1/qio +2Dn9bdndA0UI2iV9rd4PsOWYBf6kubuRiGtL/whofZCkZmGyLMDQkwpyyUQFjuG4G8DWQqr4HYSy +UPl5P6YgFJNDYP+11x6lniZIGi7cS9LNYcDgCot64wTxRVBIXCcbFKELJFICwRO9Cd3qSz8Irndi +LXJwVxffMGcxlweEs7lPMAtpFICYHPWclMKSZAqflZg86CmYZoScTZ5k2FeVsJfCj9lbuqRo4O4W +eV/l+byChr64h6za9UO4zvaNaai2Fn5ALyrLVf0MrNTxBUNfhhnPhLjyazH3LIISed5z+j7Wnn24 +osCzfLoIzro4PlX/QCPRNNwUfRoQyc3jxLmnPkSMgWu3znD6Zm9pofwqnkmciLKllg2mZelvCAxp +C9CecxDmgq8qk0nLd3cruV9VFTRGRGedpIruUeOuwEnfRMk7SiCDlAXI2UPYXvakev5Goc6VvrB8 +DeR6uAXlvgVlGATZ2X/uQq3q2u8WmvH9/inAKOEpYU+jE310oXPpQZEtaigwjT+oIQa8OquWaYP8 +5BvIJmqYKM6xid2YA4AVF7QoncPfwHjxoevhFz4l+0zXb7NEX82uiXExmvzgJsZmZaDiG7LOFjUy +BeGSnd22rhtADBDhWuBl+OobK2fIE75SVtegpnBfarXH4AaQLf3Wd/GAGU0BGpFBw8jvqTOJ+e1C +mWEzsrPXjmZfnTAnkaMBs0ISzmr2TvQJAhOUYbUpZJ8f3fF7HdkNxTZn4rgvZDAyMm+rE18mEVNE +cKq/l7ncXDSzGF3+yMGCHAZW2v+aqWu4xz3Wwsa06SAmNEYejb4YwGGLmqwp2Y1+SX8jFh9BDIDF +C53Y/SdCzFOqcbwDT/uzopa2wGl6zFupCApXuD1I6GecT4LQzs9fNdZ9GgpV58zmkjpj1P6QOSbI +g0DjM7iq7X8+IdzYcknL5TB6srdVkjVwfsfqXz7iG0GinTtqtDVKpHx0+dqJocgOIAJoFHEzYzMi +UmFiWxGvZ+dm36B9bWQ4JX0R+P+H6Q+CoOsMqHQlZC9CHMlRvsblWb9IVp60xLRJb8EqMViYDiHy +7GSrZlLByQFcibbiLa+OqNvkcfstSKRC5EVgzlhcjlpmtw/D6Ed8/ul+pGrqxrk/6ewjvpS9dAwc +2ue7svCM7PZeGv5F7TOWIG46XQVj6xqko/sReHJqh0LRx/iAWE9U7RL7E3YL4uM0r8nffH1k36jH +zp3JASI+FR6Gq8imTZNJaBTAsyavPrW5t2OdoCPqp8gKP5bHMcbi+2cfkjod6JRR4cP0pTUERa7h +DSXBgoqNb3l7nvrSttDdTzaFQz5H0BM0X5p+VKLzgX52ZtZfk1tgRrneF3y520HMlvMxQFcgu81e +FX2m6oLA34xkQ96yHoSLlsksB0znszhF +`protect end_protected +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity fifo_data_to_stream is + port ( + clk : in STD_LOGIC; + srst : in STD_LOGIC; + din : in STD_LOGIC_VECTOR ( 31 downto 0 ); + wr_en : in STD_LOGIC; + rd_en : in STD_LOGIC; + dout : out STD_LOGIC_VECTOR ( 15 downto 0 ); + full : out STD_LOGIC; + empty : out STD_LOGIC; + wr_rst_busy : out STD_LOGIC; + rd_rst_busy : out STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of fifo_data_to_stream : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of fifo_data_to_stream : entity is "fifo_data_to_stream,fifo_generator_v13_2_7,{}"; + attribute downgradeipidentifiedwarnings : string; + attribute downgradeipidentifiedwarnings of fifo_data_to_stream : entity is "yes"; + attribute x_core_info : string; + attribute x_core_info of fifo_data_to_stream : entity is "fifo_generator_v13_2_7,Vivado 2022.1.2"; +end fifo_data_to_stream; + +architecture STRUCTURE of fifo_data_to_stream is + signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC; + signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC; + signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC; + signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC; + signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC; + signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; + signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC; + signal NLW_U0_valid_UNCONNECTED : STD_LOGIC; + signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC; + signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); + signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 ); + signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); + signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); + signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 ); + attribute C_ADD_NGC_CONSTRAINT : integer; + attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0; + attribute C_APPLICATION_TYPE_AXIS : integer; + attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0; + attribute C_APPLICATION_TYPE_RACH : integer; + attribute C_APPLICATION_TYPE_RACH of U0 : label is 0; + attribute C_APPLICATION_TYPE_RDCH : integer; + attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0; + attribute C_APPLICATION_TYPE_WACH : integer; + attribute C_APPLICATION_TYPE_WACH of U0 : label is 0; + attribute C_APPLICATION_TYPE_WDCH : integer; + attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0; + attribute C_APPLICATION_TYPE_WRCH : integer; + attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0; + attribute C_AXIS_TDATA_WIDTH : integer; + attribute C_AXIS_TDATA_WIDTH of U0 : label is 8; + attribute C_AXIS_TDEST_WIDTH : integer; + attribute C_AXIS_TDEST_WIDTH of U0 : label is 1; + attribute C_AXIS_TID_WIDTH : integer; + attribute C_AXIS_TID_WIDTH of U0 : label is 1; + attribute C_AXIS_TKEEP_WIDTH : integer; + attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1; + attribute C_AXIS_TSTRB_WIDTH : integer; + attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1; + attribute C_AXIS_TUSER_WIDTH : integer; + attribute C_AXIS_TUSER_WIDTH of U0 : label is 4; + attribute C_AXIS_TYPE : integer; + attribute C_AXIS_TYPE of U0 : label is 0; + attribute C_AXI_ADDR_WIDTH : integer; + attribute C_AXI_ADDR_WIDTH of U0 : label is 32; + attribute C_AXI_ARUSER_WIDTH : integer; + attribute C_AXI_ARUSER_WIDTH of U0 : label is 1; + attribute C_AXI_AWUSER_WIDTH : integer; + attribute C_AXI_AWUSER_WIDTH of U0 : label is 1; + attribute C_AXI_BUSER_WIDTH : integer; + attribute C_AXI_BUSER_WIDTH of U0 : label is 1; + attribute C_AXI_DATA_WIDTH : integer; + attribute C_AXI_DATA_WIDTH of U0 : label is 64; + attribute C_AXI_ID_WIDTH : integer; + attribute C_AXI_ID_WIDTH of U0 : label is 1; + attribute C_AXI_LEN_WIDTH : integer; + attribute C_AXI_LEN_WIDTH of U0 : label is 8; + attribute C_AXI_LOCK_WIDTH : integer; + attribute C_AXI_LOCK_WIDTH of U0 : label is 1; + attribute C_AXI_RUSER_WIDTH : integer; + attribute C_AXI_RUSER_WIDTH of U0 : label is 1; + attribute C_AXI_TYPE : integer; + attribute C_AXI_TYPE of U0 : label is 1; + attribute C_AXI_WUSER_WIDTH : integer; + attribute C_AXI_WUSER_WIDTH of U0 : label is 1; + attribute C_COMMON_CLOCK : integer; + attribute C_COMMON_CLOCK of U0 : label is 1; + attribute C_COUNT_TYPE : integer; + attribute C_COUNT_TYPE of U0 : label is 0; + attribute C_DATA_COUNT_WIDTH : integer; + attribute C_DATA_COUNT_WIDTH of U0 : label is 9; + attribute C_DEFAULT_VALUE : string; + attribute C_DEFAULT_VALUE of U0 : label is "BlankString"; + attribute C_DIN_WIDTH : integer; + attribute C_DIN_WIDTH of U0 : label is 32; + attribute C_DIN_WIDTH_AXIS : integer; + attribute C_DIN_WIDTH_AXIS of U0 : label is 1; + attribute C_DIN_WIDTH_RACH : integer; + attribute C_DIN_WIDTH_RACH of U0 : label is 32; + attribute C_DIN_WIDTH_RDCH : integer; + attribute C_DIN_WIDTH_RDCH of U0 : label is 64; + attribute C_DIN_WIDTH_WACH : integer; + attribute C_DIN_WIDTH_WACH of U0 : label is 1; + attribute C_DIN_WIDTH_WDCH : integer; + attribute C_DIN_WIDTH_WDCH of U0 : label is 64; + attribute C_DIN_WIDTH_WRCH : integer; + attribute C_DIN_WIDTH_WRCH of U0 : label is 2; + attribute C_DOUT_RST_VAL : string; + attribute C_DOUT_RST_VAL of U0 : label is "0"; + attribute C_DOUT_WIDTH : integer; + attribute C_DOUT_WIDTH of U0 : label is 16; + attribute C_ENABLE_RLOCS : integer; + attribute C_ENABLE_RLOCS of U0 : label is 0; + attribute C_ENABLE_RST_SYNC : integer; + attribute C_ENABLE_RST_SYNC of U0 : label is 1; + attribute C_EN_SAFETY_CKT : integer; + attribute C_EN_SAFETY_CKT of U0 : label is 0; + attribute C_ERROR_INJECTION_TYPE : integer; + attribute C_ERROR_INJECTION_TYPE of U0 : label is 0; + attribute C_ERROR_INJECTION_TYPE_AXIS : integer; + attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0; + attribute C_ERROR_INJECTION_TYPE_RACH : integer; + attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0; + attribute C_ERROR_INJECTION_TYPE_RDCH : integer; + attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0; + attribute C_ERROR_INJECTION_TYPE_WACH : integer; + attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0; + attribute C_ERROR_INJECTION_TYPE_WDCH : integer; + attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0; + attribute C_ERROR_INJECTION_TYPE_WRCH : integer; + attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0; + attribute C_FAMILY : string; + attribute C_FAMILY of U0 : label is "zynquplus"; + attribute C_FULL_FLAGS_RST_VAL : integer; + attribute C_FULL_FLAGS_RST_VAL of U0 : label is 0; + attribute C_HAS_ALMOST_EMPTY : integer; + attribute C_HAS_ALMOST_EMPTY of U0 : label is 0; + attribute C_HAS_ALMOST_FULL : integer; + attribute C_HAS_ALMOST_FULL of U0 : label is 0; + attribute C_HAS_AXIS_TDATA : integer; + attribute C_HAS_AXIS_TDATA of U0 : label is 1; + attribute C_HAS_AXIS_TDEST : integer; + attribute C_HAS_AXIS_TDEST of U0 : label is 0; + attribute C_HAS_AXIS_TID : integer; + attribute C_HAS_AXIS_TID of U0 : label is 0; + attribute C_HAS_AXIS_TKEEP : integer; + attribute C_HAS_AXIS_TKEEP of U0 : label is 0; + attribute C_HAS_AXIS_TLAST : integer; + attribute C_HAS_AXIS_TLAST of U0 : label is 0; + attribute C_HAS_AXIS_TREADY : integer; + attribute C_HAS_AXIS_TREADY of U0 : label is 1; + attribute C_HAS_AXIS_TSTRB : integer; + attribute C_HAS_AXIS_TSTRB of U0 : label is 0; + attribute C_HAS_AXIS_TUSER : integer; + attribute C_HAS_AXIS_TUSER of U0 : label is 1; + attribute C_HAS_AXI_ARUSER : integer; + attribute C_HAS_AXI_ARUSER of U0 : label is 0; + attribute C_HAS_AXI_AWUSER : integer; + attribute C_HAS_AXI_AWUSER of U0 : label is 0; + attribute C_HAS_AXI_BUSER : integer; + attribute C_HAS_AXI_BUSER of U0 : label is 0; + attribute C_HAS_AXI_ID : integer; + attribute C_HAS_AXI_ID of U0 : label is 0; + attribute C_HAS_AXI_RD_CHANNEL : integer; + attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1; + attribute C_HAS_AXI_RUSER : integer; + attribute C_HAS_AXI_RUSER of U0 : label is 0; + attribute C_HAS_AXI_WR_CHANNEL : integer; + attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1; + attribute C_HAS_AXI_WUSER : integer; + attribute C_HAS_AXI_WUSER of U0 : label is 0; + attribute C_HAS_BACKUP : integer; + attribute C_HAS_BACKUP of U0 : label is 0; + attribute C_HAS_DATA_COUNT : integer; + attribute C_HAS_DATA_COUNT of U0 : label is 0; + attribute C_HAS_DATA_COUNTS_AXIS : integer; + attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0; + attribute C_HAS_DATA_COUNTS_RACH : integer; + attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0; + attribute C_HAS_DATA_COUNTS_RDCH : integer; + attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0; + attribute C_HAS_DATA_COUNTS_WACH : integer; + attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0; + attribute C_HAS_DATA_COUNTS_WDCH : integer; + attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0; + attribute C_HAS_DATA_COUNTS_WRCH : integer; + attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0; + attribute C_HAS_INT_CLK : integer; + attribute C_HAS_INT_CLK of U0 : label is 0; + attribute C_HAS_MASTER_CE : integer; + attribute C_HAS_MASTER_CE of U0 : label is 0; + attribute C_HAS_MEMINIT_FILE : integer; + attribute C_HAS_MEMINIT_FILE of U0 : label is 0; + attribute C_HAS_OVERFLOW : integer; + attribute C_HAS_OVERFLOW of U0 : label is 0; + attribute C_HAS_PROG_FLAGS_AXIS : integer; + attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0; + attribute C_HAS_PROG_FLAGS_RACH : integer; + attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0; + attribute C_HAS_PROG_FLAGS_RDCH : integer; + attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0; + attribute C_HAS_PROG_FLAGS_WACH : integer; + attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0; + attribute C_HAS_PROG_FLAGS_WDCH : integer; + attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0; + attribute C_HAS_PROG_FLAGS_WRCH : integer; + attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0; + attribute C_HAS_RD_DATA_COUNT : integer; + attribute C_HAS_RD_DATA_COUNT of U0 : label is 0; + attribute C_HAS_RD_RST : integer; + attribute C_HAS_RD_RST of U0 : label is 0; + attribute C_HAS_RST : integer; + attribute C_HAS_RST of U0 : label is 0; + attribute C_HAS_SLAVE_CE : integer; + attribute C_HAS_SLAVE_CE of U0 : label is 0; + attribute C_HAS_SRST : integer; + attribute C_HAS_SRST of U0 : label is 1; + attribute C_HAS_UNDERFLOW : integer; + attribute C_HAS_UNDERFLOW of U0 : label is 0; + attribute C_HAS_VALID : integer; + attribute C_HAS_VALID of U0 : label is 0; + attribute C_HAS_WR_ACK : integer; + attribute C_HAS_WR_ACK of U0 : label is 0; + attribute C_HAS_WR_DATA_COUNT : integer; + attribute C_HAS_WR_DATA_COUNT of U0 : label is 0; + attribute C_HAS_WR_RST : integer; + attribute C_HAS_WR_RST of U0 : label is 0; + attribute C_IMPLEMENTATION_TYPE : integer; + attribute C_IMPLEMENTATION_TYPE of U0 : label is 6; + attribute C_IMPLEMENTATION_TYPE_AXIS : integer; + attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1; + attribute C_IMPLEMENTATION_TYPE_RACH : integer; + attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1; + attribute C_IMPLEMENTATION_TYPE_RDCH : integer; + attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1; + attribute C_IMPLEMENTATION_TYPE_WACH : integer; + attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1; + attribute C_IMPLEMENTATION_TYPE_WDCH : integer; + attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1; + attribute C_IMPLEMENTATION_TYPE_WRCH : integer; + attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1; + attribute C_INIT_WR_PNTR_VAL : integer; + attribute C_INIT_WR_PNTR_VAL of U0 : label is 0; + attribute C_INTERFACE_TYPE : integer; + attribute C_INTERFACE_TYPE of U0 : label is 0; + attribute C_MEMORY_TYPE : integer; + attribute C_MEMORY_TYPE of U0 : label is 4; + attribute C_MIF_FILE_NAME : string; + attribute C_MIF_FILE_NAME of U0 : label is "BlankString"; + attribute C_MSGON_VAL : integer; + attribute C_MSGON_VAL of U0 : label is 1; + attribute C_OPTIMIZATION_MODE : integer; + attribute C_OPTIMIZATION_MODE of U0 : label is 0; + attribute C_OVERFLOW_LOW : integer; + attribute C_OVERFLOW_LOW of U0 : label is 0; + attribute C_POWER_SAVING_MODE : integer; + attribute C_POWER_SAVING_MODE of U0 : label is 0; + attribute C_PRELOAD_LATENCY : integer; + attribute C_PRELOAD_LATENCY of U0 : label is 2; + attribute C_PRELOAD_REGS : integer; + attribute C_PRELOAD_REGS of U0 : label is 1; + attribute C_PRIM_FIFO_TYPE : string; + attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_AXIS : string; + attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18"; + attribute C_PRIM_FIFO_TYPE_RACH : string; + attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_RDCH : string; + attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "512x72"; + attribute C_PRIM_FIFO_TYPE_WACH : string; + attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36"; + attribute C_PRIM_FIFO_TYPE_WDCH : string; + attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "512x72"; + attribute C_PRIM_FIFO_TYPE_WRCH : string; + attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36"; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer; + attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3; + attribute C_PROG_EMPTY_TYPE : integer; + attribute C_PROG_EMPTY_TYPE of U0 : label is 0; + attribute C_PROG_EMPTY_TYPE_AXIS : integer; + attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0; + attribute C_PROG_EMPTY_TYPE_RACH : integer; + attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0; + attribute C_PROG_EMPTY_TYPE_RDCH : integer; + attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0; + attribute C_PROG_EMPTY_TYPE_WACH : integer; + attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0; + attribute C_PROG_EMPTY_TYPE_WDCH : integer; + attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0; + attribute C_PROG_EMPTY_TYPE_WRCH : integer; + attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0; + attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 510; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer; + attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023; + attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer; + attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 509; + attribute C_PROG_FULL_TYPE : integer; + attribute C_PROG_FULL_TYPE of U0 : label is 0; + attribute C_PROG_FULL_TYPE_AXIS : integer; + attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0; + attribute C_PROG_FULL_TYPE_RACH : integer; + attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0; + attribute C_PROG_FULL_TYPE_RDCH : integer; + attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0; + attribute C_PROG_FULL_TYPE_WACH : integer; + attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0; + attribute C_PROG_FULL_TYPE_WDCH : integer; + attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0; + attribute C_PROG_FULL_TYPE_WRCH : integer; + attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0; + attribute C_RACH_TYPE : integer; + attribute C_RACH_TYPE of U0 : label is 0; + attribute C_RDCH_TYPE : integer; + attribute C_RDCH_TYPE of U0 : label is 0; + attribute C_RD_DATA_COUNT_WIDTH : integer; + attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 10; + attribute C_RD_DEPTH : integer; + attribute C_RD_DEPTH of U0 : label is 1024; + attribute C_RD_FREQ : integer; + attribute C_RD_FREQ of U0 : label is 1; + attribute C_RD_PNTR_WIDTH : integer; + attribute C_RD_PNTR_WIDTH of U0 : label is 10; + attribute C_REG_SLICE_MODE_AXIS : integer; + attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0; + attribute C_REG_SLICE_MODE_RACH : integer; + attribute C_REG_SLICE_MODE_RACH of U0 : label is 0; + attribute C_REG_SLICE_MODE_RDCH : integer; + attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0; + attribute C_REG_SLICE_MODE_WACH : integer; + attribute C_REG_SLICE_MODE_WACH of U0 : label is 0; + attribute C_REG_SLICE_MODE_WDCH : integer; + attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0; + attribute C_REG_SLICE_MODE_WRCH : integer; + attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0; + attribute C_SELECT_XPM : integer; + attribute C_SELECT_XPM of U0 : label is 0; + attribute C_SYNCHRONIZER_STAGE : integer; + attribute C_SYNCHRONIZER_STAGE of U0 : label is 2; + attribute C_UNDERFLOW_LOW : integer; + attribute C_UNDERFLOW_LOW of U0 : label is 0; + attribute C_USE_COMMON_OVERFLOW : integer; + attribute C_USE_COMMON_OVERFLOW of U0 : label is 0; + attribute C_USE_COMMON_UNDERFLOW : integer; + attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0; + attribute C_USE_DEFAULT_SETTINGS : integer; + attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0; + attribute C_USE_DOUT_RST : integer; + attribute C_USE_DOUT_RST of U0 : label is 1; + attribute C_USE_ECC : integer; + attribute C_USE_ECC of U0 : label is 0; + attribute C_USE_ECC_AXIS : integer; + attribute C_USE_ECC_AXIS of U0 : label is 0; + attribute C_USE_ECC_RACH : integer; + attribute C_USE_ECC_RACH of U0 : label is 0; + attribute C_USE_ECC_RDCH : integer; + attribute C_USE_ECC_RDCH of U0 : label is 0; + attribute C_USE_ECC_WACH : integer; + attribute C_USE_ECC_WACH of U0 : label is 0; + attribute C_USE_ECC_WDCH : integer; + attribute C_USE_ECC_WDCH of U0 : label is 0; + attribute C_USE_ECC_WRCH : integer; + attribute C_USE_ECC_WRCH of U0 : label is 0; + attribute C_USE_EMBEDDED_REG : integer; + attribute C_USE_EMBEDDED_REG of U0 : label is 1; + attribute C_USE_FIFO16_FLAGS : integer; + attribute C_USE_FIFO16_FLAGS of U0 : label is 0; + attribute C_USE_FWFT_DATA_COUNT : integer; + attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0; + attribute C_USE_PIPELINE_REG : integer; + attribute C_USE_PIPELINE_REG of U0 : label is 0; + attribute C_VALID_LOW : integer; + attribute C_VALID_LOW of U0 : label is 0; + attribute C_WACH_TYPE : integer; + attribute C_WACH_TYPE of U0 : label is 0; + attribute C_WDCH_TYPE : integer; + attribute C_WDCH_TYPE of U0 : label is 0; + attribute C_WRCH_TYPE : integer; + attribute C_WRCH_TYPE of U0 : label is 0; + attribute C_WR_ACK_LOW : integer; + attribute C_WR_ACK_LOW of U0 : label is 0; + attribute C_WR_DATA_COUNT_WIDTH : integer; + attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 9; + attribute C_WR_DEPTH : integer; + attribute C_WR_DEPTH of U0 : label is 512; + attribute C_WR_DEPTH_AXIS : integer; + attribute C_WR_DEPTH_AXIS of U0 : label is 1024; + attribute C_WR_DEPTH_RACH : integer; + attribute C_WR_DEPTH_RACH of U0 : label is 16; + attribute C_WR_DEPTH_RDCH : integer; + attribute C_WR_DEPTH_RDCH of U0 : label is 1024; + attribute C_WR_DEPTH_WACH : integer; + attribute C_WR_DEPTH_WACH of U0 : label is 16; + attribute C_WR_DEPTH_WDCH : integer; + attribute C_WR_DEPTH_WDCH of U0 : label is 1024; + attribute C_WR_DEPTH_WRCH : integer; + attribute C_WR_DEPTH_WRCH of U0 : label is 16; + attribute C_WR_FREQ : integer; + attribute C_WR_FREQ of U0 : label is 1; + attribute C_WR_PNTR_WIDTH : integer; + attribute C_WR_PNTR_WIDTH of U0 : label is 9; + attribute C_WR_PNTR_WIDTH_AXIS : integer; + attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10; + attribute C_WR_PNTR_WIDTH_RACH : integer; + attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4; + attribute C_WR_PNTR_WIDTH_RDCH : integer; + attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10; + attribute C_WR_PNTR_WIDTH_WACH : integer; + attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4; + attribute C_WR_PNTR_WIDTH_WDCH : integer; + attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10; + attribute C_WR_PNTR_WIDTH_WRCH : integer; + attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4; + attribute C_WR_RESPONSE_LATENCY : integer; + attribute C_WR_RESPONSE_LATENCY of U0 : label is 1; + attribute is_du_within_envelope : string; + attribute is_du_within_envelope of U0 : label is "true"; + attribute x_interface_info : string; + attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 core_clk CLK"; + attribute x_interface_parameter : string; + attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME core_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + attribute x_interface_info of empty : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY"; + attribute x_interface_info of full : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL"; + attribute x_interface_info of rd_en : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN"; + attribute x_interface_info of wr_en : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN"; + attribute x_interface_info of din : signal is "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA"; + attribute x_interface_info of dout : signal is "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA"; +begin +U0: entity work.fifo_data_to_stream_fifo_generator_v13_2_7 + port map ( + almost_empty => NLW_U0_almost_empty_UNCONNECTED, + almost_full => NLW_U0_almost_full_UNCONNECTED, + axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0), + axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED, + axi_ar_injectdbiterr => '0', + axi_ar_injectsbiterr => '0', + axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED, + axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED, + axi_ar_prog_empty_thresh(3 downto 0) => B"0000", + axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED, + axi_ar_prog_full_thresh(3 downto 0) => B"0000", + axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0), + axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED, + axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED, + axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0), + axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0), + axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED, + axi_aw_injectdbiterr => '0', + axi_aw_injectsbiterr => '0', + axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED, + axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED, + axi_aw_prog_empty_thresh(3 downto 0) => B"0000", + axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED, + axi_aw_prog_full_thresh(3 downto 0) => B"0000", + axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0), + axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED, + axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED, + axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0), + axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0), + axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED, + axi_b_injectdbiterr => '0', + axi_b_injectsbiterr => '0', + axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED, + axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED, + axi_b_prog_empty_thresh(3 downto 0) => B"0000", + axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED, + axi_b_prog_full_thresh(3 downto 0) => B"0000", + axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0), + axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED, + axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED, + axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0), + axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0), + axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED, + axi_r_injectdbiterr => '0', + axi_r_injectsbiterr => '0', + axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED, + axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED, + axi_r_prog_empty_thresh(9 downto 0) => B"0000000000", + axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED, + axi_r_prog_full_thresh(9 downto 0) => B"0000000000", + axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0), + axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED, + axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED, + axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0), + axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0), + axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED, + axi_w_injectdbiterr => '0', + axi_w_injectsbiterr => '0', + axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED, + axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED, + axi_w_prog_empty_thresh(9 downto 0) => B"0000000000", + axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED, + axi_w_prog_full_thresh(9 downto 0) => B"0000000000", + axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0), + axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED, + axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED, + axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0), + axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0), + axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED, + axis_injectdbiterr => '0', + axis_injectsbiterr => '0', + axis_overflow => NLW_U0_axis_overflow_UNCONNECTED, + axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED, + axis_prog_empty_thresh(9 downto 0) => B"0000000000", + axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED, + axis_prog_full_thresh(9 downto 0) => B"0000000000", + axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0), + axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED, + axis_underflow => NLW_U0_axis_underflow_UNCONNECTED, + axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0), + backup => '0', + backup_marker => '0', + clk => clk, + data_count(8 downto 0) => NLW_U0_data_count_UNCONNECTED(8 downto 0), + dbiterr => NLW_U0_dbiterr_UNCONNECTED, + din(31 downto 0) => din(31 downto 0), + dout(15 downto 0) => dout(15 downto 0), + empty => empty, + full => full, + injectdbiterr => '0', + injectsbiterr => '0', + int_clk => '0', + m_aclk => '0', + m_aclk_en => '0', + m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0), + m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0), + m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0), + m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0), + m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0), + m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0), + m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0), + m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0), + m_axi_arready => '0', + m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0), + m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0), + m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0), + m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED, + m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0), + m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0), + m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0), + m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0), + m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0), + m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0), + m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0), + m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0), + m_axi_awready => '0', + m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0), + m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0), + m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0), + m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED, + m_axi_bid(0) => '0', + m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED, + m_axi_bresp(1 downto 0) => B"00", + m_axi_buser(0) => '0', + m_axi_bvalid => '0', + m_axi_rdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + m_axi_rid(0) => '0', + m_axi_rlast => '0', + m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED, + m_axi_rresp(1 downto 0) => B"00", + m_axi_ruser(0) => '0', + m_axi_rvalid => '0', + m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0), + m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0), + m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED, + m_axi_wready => '0', + m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0), + m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0), + m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED, + m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0), + m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0), + m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0), + m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0), + m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED, + m_axis_tready => '0', + m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0), + m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0), + m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED, + overflow => NLW_U0_overflow_UNCONNECTED, + prog_empty => NLW_U0_prog_empty_UNCONNECTED, + prog_empty_thresh(9 downto 0) => B"0000000000", + prog_empty_thresh_assert(9 downto 0) => B"0000000000", + prog_empty_thresh_negate(9 downto 0) => B"0000000000", + prog_full => NLW_U0_prog_full_UNCONNECTED, + prog_full_thresh(8 downto 0) => B"000000000", + prog_full_thresh_assert(8 downto 0) => B"000000000", + prog_full_thresh_negate(8 downto 0) => B"000000000", + rd_clk => '0', + rd_data_count(9 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(9 downto 0), + rd_en => rd_en, + rd_rst => '0', + rd_rst_busy => rd_rst_busy, + rst => '0', + s_aclk => '0', + s_aclk_en => '0', + s_aresetn => '0', + s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_arburst(1 downto 0) => B"00", + s_axi_arcache(3 downto 0) => B"0000", + s_axi_arid(0) => '0', + s_axi_arlen(7 downto 0) => B"00000000", + s_axi_arlock(0) => '0', + s_axi_arprot(2 downto 0) => B"000", + s_axi_arqos(3 downto 0) => B"0000", + s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, + s_axi_arregion(3 downto 0) => B"0000", + s_axi_arsize(2 downto 0) => B"000", + s_axi_aruser(0) => '0', + s_axi_arvalid => '0', + s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", + s_axi_awburst(1 downto 0) => B"00", + s_axi_awcache(3 downto 0) => B"0000", + s_axi_awid(0) => '0', + s_axi_awlen(7 downto 0) => B"00000000", + s_axi_awlock(0) => '0', + s_axi_awprot(2 downto 0) => B"000", + s_axi_awqos(3 downto 0) => B"0000", + s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, + s_axi_awregion(3 downto 0) => B"0000", + s_axi_awsize(2 downto 0) => B"000", + s_axi_awuser(0) => '0', + s_axi_awvalid => '0', + s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0), + s_axi_bready => '0', + s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), + s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0), + s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, + s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0), + s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0), + s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, + s_axi_rready => '0', + s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), + s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0), + s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, + s_axi_wdata(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + s_axi_wid(0) => '0', + s_axi_wlast => '0', + s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, + s_axi_wstrb(7 downto 0) => B"00000000", + s_axi_wuser(0) => '0', + s_axi_wvalid => '0', + s_axis_tdata(7 downto 0) => B"00000000", + s_axis_tdest(0) => '0', + s_axis_tid(0) => '0', + s_axis_tkeep(0) => '0', + s_axis_tlast => '0', + s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED, + s_axis_tstrb(0) => '0', + s_axis_tuser(3 downto 0) => B"0000", + s_axis_tvalid => '0', + sbiterr => NLW_U0_sbiterr_UNCONNECTED, + sleep => '0', + srst => srst, + underflow => NLW_U0_underflow_UNCONNECTED, + valid => NLW_U0_valid_UNCONNECTED, + wr_ack => NLW_U0_wr_ack_UNCONNECTED, + wr_clk => '0', + wr_data_count(8 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(8 downto 0), + wr_en => wr_en, + wr_rst => '0', + wr_rst_busy => wr_rst_busy + ); +end STRUCTURE; diff --git a/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl b/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl new file mode 100644 index 0000000..d15badf --- /dev/null +++ b/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl @@ -0,0 +1,550 @@ +--------------------------------------------------------------- +-- File : qlaser_dacs_pulse_channel.vhd +-- Description : Single channel of pulse output +---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.qlaser_pkg.all; +use work.qlaser_dacs_pulse_channel_pkg.all; + +entity qlaser_dacs_pulse_channel is +port ( + reset : in std_logic; + clk : in std_logic; + + enable : in std_logic; -- Set when DAC interface is running + start : in std_logic; -- Set when pulse generation sequence begins (trigger) + cnt_time : in std_logic_vector(23 downto 0); -- Time since trigger. + + busy : out std_logic; -- Status signal + done_seq : in std_logic; -- Status signal to terminate sequence + -- TODO: Add another status signal to indicate any errors? + + -- CPU interface + cpu_addr : in std_logic_vector(11 downto 0); -- Address input + cpu_wdata : in std_logic_vector(31 downto 0); -- Data input + cpu_wr : in std_logic; -- Write enable + cpu_sel : in std_logic; -- Block select + cpu_rdata : out std_logic_vector(31 downto 0); -- Data output + cpu_rdata_dv : out std_logic; -- Acknowledge output + + -- AXI-stream output + axis_tready : in std_logic; -- axi_stream ready from downstream module + axis_tdata : out std_logic_vector(15 downto 0); -- axi stream output data + axis_tvalid : out std_logic; -- axi_stream output data valid + axis_tlast : out std_logic -- axi_stream output set on last data +); +end entity; + +--------------------------------------------------------------------------- +-- Single channel pulse generator with two RAMs +--------------------------------------------------------------------------- +architecture channel of qlaser_dacs_pulse_channel is + +-- Signal declarations for pulse RAM +signal ram_pulse_we : std_logic_vector( 0 downto 0); -- Write enable for pulse RAM +signal ram_pulse_addra : std_logic_vector( 9 downto 0); -- Address for pulse RAM +signal ram_pulse_dina : std_logic_vector(31 downto 0); -- Data for pulse RAM +signal ram_pulse_douta : std_logic_vector(31 downto 0); -- Data out from pulse RAM +signal ram_pulse_addrb : std_logic_vector( 9 downto 0); -- Address for pulse RAM +signal ram_pulse_doutb : std_logic_vector(31 downto 0); -- Data out from pulse RAM + +-- Signal declarations for waveform RAM +signal ram_waveform_wea : std_logic_vector( 0 downto 0); -- Write enable for waveform RAM +signal ram_waveform_addra : std_logic_vector(10 downto 0); -- Address for waveform RAM +signal ram_waveform_dina : std_logic_vector(31 downto 0); -- Data for waveform RAM +signal ram_waveform_douta : std_logic_vector(31 downto 0); -- Data out from waveform RAM +signal ram_waveform_addrb : std_logic_vector(19 downto 0); -- Address for waveform RAM +signal ram_waveform_doutb : std_logic_vector(15 downto 0); -- Data out from waveform RAM + +-- State variable type declaration for main state machine +type t_sm_state is ( + S_RESET, -- Wait for 'enable'. Stay here until JESD interface is up and running, + S_IDLE, -- Wait for 'start' + S_WAIT, -- Wait for cnt_time, external input, to match pulse position RAM output + S_LOAD, -- Load the pulse channel RAM addresses and start the waveform output + S_HOLD, -- Hold the last pulse definition address and output its data + S_WAVE_UP, -- Output the rising edge of a waveform + S_WAVE_FLAT,-- Output the flat top part of a waveform + S_WAVE_DOWN -- Output the falling edge of a waveform +); +signal sm_state : t_sm_state; +signal sm_wavedata : std_logic_vector(15 downto 0); -- Waveform RAM data +signal sm_wavedata_dv : std_logic; -- Signal to indicate that waveform RAM data is valid +signal sm_busy : std_logic; -- Signal to indicate that s.m. is not idle +signal cnt_wave_len : unsigned(C_BITS_ADDR_LENGTH - 1 downto 0); -- Counter used for incremnet/decrement wave table addresses +signal cnt_wave_top : unsigned(C_BITS_ADDR_TOP - 1 downto 0); -- Counter for the flat top of the waveform +signal cnt_addr : unsigned(C_BITS_ADDR_START - 1 downto 0); -- Counter to keep track of address increments +signal wave_last_addr : std_logic_vector(C_BITS_ADDR_FULL - 1 downto 0); -- Last address of the waveform table + +-- Misc signals +signal cpu_rdata_dv_e1 : std_logic; +signal cpu_rdata_dv_e2 : std_logic; +signal cpu_rdata_ramsel_d1 : std_logic; +signal cpu_rdata_ramsel_d2 : std_logic; + +signal pc : std_logic_vector(C_BITS_ADDR_PULSE - 1 downto 0); -- pulse counter, used to count the number of pulses generated + +---------------------------------------------------------------- +-- Assign values from the pulse definition ram to regfiles (?) with the following: +-- 1. Start time 24 bits. [23:0] +-- 2. Wave start addr 12 bit at [11:0] +-- Wave length 10-bit at [25:16] +-- 3. Scale factors 16, 16. [31:16] [15:0] +-- 4. Flat-top 17-bit. [16:0] +---------------------------------------------------------------- +signal reg_pulse_time : std_logic_vector(31 downto 0); -- first register which stores the pulse's start time +signal reg_wave_start_addr : std_logic_vector(C_BITS_ADDR_START - 1 downto 0); -- the start address of the wavetable +signal reg_wave_length : unsigned(C_BITS_ADDR_LENGTH - 1 downto 0); -- the length of the wavetable +signal reg_wave_end_addr : unsigned(C_BITS_ADDR_FULL - 1 downto 0); -- the end address of the wavetable +signal reg_scale_gain : unsigned(C_BITS_TIME_FACTOR - 1 downto 0); -- scale factor for the gain, amplitude +signal reg_scale_time : unsigned(C_BITS_TIME_FACTOR - 1 downto 0); -- scale factor for the time, length +signal reg_pulse_flattop : unsigned(C_BITS_ADDR_TOP - 1 downto 0); -- fourth register which stores the pulse's flat top value + +-- Pipeline delays +signal sm_state_d1 : t_sm_state; +signal start_d1 : std_logic; +signal enable_d1 : std_logic; + +-- error signal +signal err_addr_of : std_logic; + + +begin + + ---------------------------------------------------------------- + -- Pulse Definition Block RAM. + -- Synch write, Synch read + -- Port A is for CPU read/write. 1024x32-bit + -- Port B is for pulse time data output. 1024x32-bit + ---------------------------------------------------------------- + u_ram_pulse : entity work.bram_pulse_definition + port map( + -- Port A CPU Bus + clka => clk, -- input std_logic + wea => ram_pulse_we, -- input slv( 0 to 0 ) + addra => ram_pulse_addra, -- input slv( 9 downto 0 ) + dina => ram_pulse_dina, -- input slv( 31 downto 0 ) + douta => ram_pulse_douta, -- output slv( 31 downto 0 ), + -- Port B waveform input + clkb => clk, + web => (others=>'0'), + addrb => ram_pulse_addrb, -- input slv( 9 downto 0 ) + dinb => (others=>'0'), + doutb => ram_pulse_doutb -- output slv( 31 downto 0 ) + ); + + + ---------------------------------------------------------------- + -- Waveform table Block RAM. + -- Synch write, Synch read + -- Port A is for CPU read/write. 2048x32-bit + -- Port B is for waveform data. 4096x16-bit + ---------------------------------------------------------------- + u_ram_waveform : entity work.bram_waveform + port map ( + -- Port A CPU Bus + clka => clk , -- input std_logic + wea => ram_waveform_wea , -- input slv(0 downto 0) + addra => ram_waveform_addra , -- input slv(10 downto 0) + dina => ram_waveform_dina , -- input slv(31 downto 0) + douta => ram_waveform_douta , -- output slv(31 downto 0) + + -- Port B waveform output + clkb => clk , -- input std_logic + web => (others=>'0') , -- input slv(0 downto 0) + addrb => ram_waveform_addrb(19 downto 8) , -- input slv(11 downto 0) + dinb => (others=>'0') , -- input slv(15 downto 0) + doutb => ram_waveform_doutb -- output slv(15 downto 0) + ); + + ---------------------------------------------------------------- + -- CPU Read/Write RAM + -- MSB of cpu_addr is used to select one of the two RAMs + -- to read/write, and the remainder are a 9-bit or 4-bit RAM address. + ---------------------------------------------------------------- + pr_ram_rw : process (reset, clk) + begin + if (reset = '1') then + + ram_pulse_addra <= (others=>'0'); + ram_pulse_dina <= (others=>'0'); + ram_pulse_we <= (others=>'0'); + + ram_waveform_wea <= (others=>'0'); + ram_waveform_addra <= (others=>'0'); + ram_waveform_dina <= (others=>'0'); + + cpu_rdata <= (others=>'0'); + cpu_rdata_dv <= '0'; + cpu_rdata_dv_e1 <= '0'; + cpu_rdata_dv_e2 <= '0'; + cpu_rdata_ramsel_d1 <= '0'; + cpu_rdata_ramsel_d2 <= '0'; + + elsif rising_edge(clk) then + + + ------------------------------------------------- + -- CPU writing RAM + ------------------------------------------------- + if (cpu_wr = '1') and (cpu_sel = '1') then + + -- 0 for pulse definition, 1 for waveform table + if (cpu_addr(C_RAM_SELECT) = '1') then + + ram_pulse_addra <= (others=>'0'); + ram_pulse_dina <= (others=>'0'); + ram_pulse_we <= (others=>'0'); + + ram_waveform_wea(0) <= '1'; + ram_waveform_addra <= cpu_addr(10 downto 0); + ram_waveform_dina <= cpu_wdata; + + else + + ram_pulse_addra <= cpu_addr(9 downto 0); + ram_pulse_dina <= cpu_wdata; + ram_pulse_we(0) <= '1'; + ram_waveform_wea <= (others=>'0'); + ram_waveform_addra <= (others=>'0'); + ram_waveform_dina <= (others=>'0'); + + end if; + + cpu_rdata_dv_e1 <= '0'; + cpu_rdata_dv_e2 <= '0'; + cpu_rdata_ramsel_d1 <= '0'; + cpu_rdata_ramsel_d2 <= '0'; + + + ------------------------------------------------- + -- CPU read + ------------------------------------------------- + elsif (cpu_wr = '0') and (cpu_sel = '1') then + + if (cpu_addr(C_RAM_SELECT) = '1') then -- Waveform + ram_pulse_addra <= (others=>'0'); + ram_waveform_addra <= cpu_addr(10 downto 0); + else -- Pulse + ram_pulse_addra <= cpu_addr(9 downto 0); + ram_waveform_addra <= (others=>'0'); + end if; + + ram_pulse_we <= (others=>'0'); + ram_waveform_wea(0) <= '0'; + + cpu_rdata_dv_e2 <= '1'; -- DV for cycle, when RAM output occurs + cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle + cpu_rdata_ramsel_d1 <= cpu_addr(C_RAM_SELECT); -- Save the select bit one cycle later + cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1; + + else + ram_pulse_addra <= (others=>'0'); + ram_pulse_we <= (others=>'0'); + ram_waveform_addra <= (others=>'0'); + ram_waveform_wea(0) <= '0'; + + cpu_rdata_dv_e2 <= '0'; + cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle + cpu_rdata_ramsel_d1 <= '0'; + cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1; + + end if; + + ------------------------------------------------- + -- Output the delayed RAM data + -- This adds a pipeline delay to the cpu_rdata_dv to account for + -- the delay in reading data from the RAM + ------------------------------------------------- + if (cpu_rdata_dv_e1 = '1') then + + cpu_rdata_dv <= '1'; + + -- Select source of output data + if (cpu_rdata_ramsel_d2 = '1') then -- Output is from waveform table + cpu_rdata <= ram_waveform_douta; + + elsif (cpu_rdata_ramsel_d2 = '0') then + cpu_rdata <= ram_pulse_douta; + end if; + + else + cpu_rdata <= (others=>'0'); + cpu_rdata_dv <= '0'; + end if; + + end if; + + end process; + + ---------------------------------------------------------------- + -- State machine: + -- Compares cnt_time input against current output from pulse position RAM. + -- When values match iti incremnts the pulse postion RAM address to + -- retrieve the next pulse position and also starts reading the + -- entire waveform table, one value every clock cycle, until it reaches the end. + -- Once the pulse is complete it waits for the next cnt_time match. + -- Repeat until all pulse position RAM times have triggered a pulse output + -- or until the maximum counter time has been reached. + ---------------------------------------------------------------- + pr_sm : process (reset, clk) + -- Temp variables for waveform output + variable v_ram_waveform_doutb_multiplied : std_logic_vector(C_BITS_GAIN_FACTOR + 15 downto 0); + variable v_ram_waveform_addrb_scaled : std_logic_vector(C_BITS_ADDR_START + 15 downto 0); + variable v_ram_waveform_addrb_raw : unsigned(C_BITS_ADDR_START - 1 downto 0); + begin + if (reset = '1') then + + sm_state <= S_IDLE; -- TODO: Eric: Should this be S_RESET since we reset the JEDS interface as well? + ram_pulse_addrb <= (others=>'0'); + ram_waveform_addrb <= (others=>'0'); + cnt_addr <= (others=>'0'); + wave_last_addr <= (others=>'0'); + + sm_wavedata <= (others=>'0'); + sm_wavedata_dv <= '0'; + sm_busy <= '0'; + reg_wave_start_addr <= (others=>'0'); + reg_wave_length <= (others=>'0'); + reg_scale_gain <= (others=>'0'); + reg_scale_time <= (others=>'0'); + reg_wave_end_addr <= (others=>'0'); + reg_pulse_time <= (others=>'0'); + reg_pulse_flattop <= (others=>'0'); + + + pc <= (others=>'0'); + cnt_wave_len <= (others=>'0'); + cnt_wave_top <= (others=>'0'); + elsif rising_edge(clk) then + + + -- Pipeline delays to use for rising edge detection + enable_d1 <= enable; + start_d1 <= start; + sm_state_d1 <= sm_state; + + -- Default + sm_wavedata <= (others=>'0'); + sm_wavedata_dv <= '0'; + + + + ------------------------------------------------------------------------ + -- Main state machine + ------------------------------------------------------------------------ + case sm_state is + + ------------------------------------------------------------------------ + -- Wait for rising edge of enable + -- This is set when the JESD interface is aligned and functional. + -- Send a zero value to initialize the DAC then go to idle. + ------------------------------------------------------------------------ + when S_RESET => + + if (enable = '1') and (enable_d1 = '0') then + sm_wavedata <= (others=>'0'); + sm_wavedata_dv <= '1'; + sm_state <= S_IDLE; + end if; + sm_busy <= '0'; + + ------------------------------------------------------------------------ + -- Wait for rising edge of 'start'. + -- No data output. + ------------------------------------------------------------------------ + when S_IDLE => + + if (start = '1') and (start_d1 = '0') then + sm_state <= S_LOAD; + sm_busy <= '1'; + else + sm_busy <= '0'; + end if; + + ------------------------------------------------------------------------ + -- Load four addresses from pulse definition RAM into four 32 bits regesters + ------------------------------------------------------------------------ + when S_LOAD => + -- TODO: FromEric: does is needed here? or should be inside the if-else loops + -- Load the pulse channel RAM addresses and start the waveform output + sm_busy <= '1'; + if (sm_state_d1 = S_WAVE_DOWN) then -- output the last pulse definition address for one more clock cycle + v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain); + sm_wavedata <= v_ram_waveform_doutb_multiplied(30 downto 15); + -- ram_waveform_addrb <= (others=>'0'); -- reset the address for the next waveform + sm_wavedata_dv <= '1'; + end if; + -- Pipline the pulse definition address + if (unsigned(ram_pulse_addrb) mod 4 = 0) then + ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 1); + sm_state <= S_LOAD; + -- first quarter of the pulse definition, no register is loaded + + elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then + ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 2); + sm_state <= S_LOAD; + -- second quarter of the pulse definition, the start time is loaded + reg_pulse_time <= ram_pulse_doutb; + + + elsif (unsigned(ram_pulse_addrb) mod 4 = 2) then + ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 3); + sm_state <= S_LOAD; + -- third quarter of the pulse definition, the length and start address of the wavetable are loaded + reg_wave_start_addr <= ram_pulse_doutb(C_BITS_ADDR_START - 1 downto 0); + reg_wave_length <= unsigned(ram_pulse_doutb(25 downto 16)); -- TODO: make this a constant + + elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then + sm_state <= S_WAIT; -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state + -- hold the last pulse definition address as it will be used in the next state + pc <= std_logic_vector(unsigned(pc) + C_PC_INCR); -- incremnet the pulse counter and start waiting to output the wave + -- forth quarter of the pulse definition, the scale factors are loaded + reg_scale_gain <= unsigned(ram_pulse_doutb(31 downto 16)); + reg_scale_time <= unsigned(ram_pulse_doutb(15 downto 0)); + reg_wave_end_addr <= resize(unsigned(reg_wave_start_addr) + reg_wave_length, 20) sll 8; -- get the supposed last value of the wavetable + + end if; + + ------------------------------------------------------------------------ + -- Wait for cnt_time, external input, to match pulse position RAM output + -- Return to idle state if max time is reached. Output waveform value zero. + ------------------------------------------------------------------------ + when S_WAIT => + -- read the last word of the pulse definition, the flat top value + reg_pulse_flattop <= unsigned(ram_pulse_doutb(C_BITS_ADDR_TOP - 1 downto 0)); + -- Start to output wave and increment pulse position RAM address + if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then + sm_state <= S_WAVE_UP; + + ram_waveform_addrb <= reg_wave_start_addr & std_logic_vector(to_unsigned(0, 8)); -- set the wavetable's address to the starting address defined from the pulse ram + -- cnt_addr <= unsigned(reg_wave_start_addr); + -- reset the wave lenth counter + cnt_wave_len <= (others=>'0'); + elsif (cnt_time = X"FFFFFF") or (done_seq = '1') then + sm_state <= S_IDLE; + end if; + + + ------------------------------------------------------------------------ + -- Output the raising edge of a waveform + -- Hold the last address when complete + ------------------------------------------------------------------------ + when S_WAVE_UP => + -- Check if is end of rise of the waveform, next address >= end address. if so pad the address pointer to the end address and move to next state + -- TODO: convert the numbers below to constaint. right now just make sure I'm not confused + if (unsigned(ram_waveform_addrb) + reg_scale_time >= reg_wave_end_addr) then + -- ram_waveform_addrb <= std_logic_vector(reg_wave_end_addr); -- pad the address pointer to the end address + if (sm_state_d1 = S_WAVE_UP) then + ram_waveform_addrb <= std_logic_vector(reg_wave_end_addr); -- pad the address pointer to the end address + end if; + wave_last_addr <= std_logic_vector(unsigned(ram_waveform_addrb)); -- hold the last address of the wavetable + -- skip the flat top state if the flat top value is zero + if (reg_pulse_flattop = 0) then + sm_state <= S_WAVE_DOWN; + -- reset the counter for the next transition + cnt_wave_len <= (others=>'0'); + else + sm_state <= S_WAVE_FLAT; + -- reset the counter for the next transition + cnt_wave_len <= (others=>'0'); + cnt_wave_top <= (others=>'0'); + end if; + else + cnt_wave_len <= cnt_wave_len + 1; + cnt_addr <= cnt_addr + 1; + ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + reg_scale_time); + wave_last_addr <= std_logic_vector(unsigned(ram_waveform_addrb) + reg_scale_time); -- hold the last address of the wavetable + end if; + + -- sm_wavedata <= std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain)(31 downto 16); + -- Modelsim Cannot synthesize this above line, so we *have to* seperate them into two lines + -- # ** Error: Prefix of slice name cannot be type conversion (STD_LOGIC_VECTOR) expression. + v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain); + sm_wavedata <= v_ram_waveform_doutb_multiplied(30 downto 15); + if (sm_state_d1 = S_WAIT) then -- data valid is delayed by one clock cycle + sm_wavedata_dv <= '0'; + else + sm_wavedata_dv <= '1'; + end if; + + ------------------------------------------------------------------------ + -- Hold the last address and output its data + -- decrement from this address when finished waiting + ------------------------------------------------------------------------ + when S_WAVE_FLAT => + -- count the 17-bit flat top, if the counter reaches the flat top value, then go to the next state + if (cnt_wave_top = reg_pulse_flattop) then + sm_state <= S_WAVE_DOWN; + + cnt_wave_top <= (others=>'0'); -- reset the counter for the next transition + + else + cnt_wave_top <= cnt_wave_top + 1; + end if; + v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain); + sm_wavedata <= v_ram_waveform_doutb_multiplied(30 downto 15); + sm_wavedata_dv <= '1'; + + ------------------------------------------------------------------------ + -- Output the falling edge of a waveform + -- Hold the start address when complete + ------------------------------------------------------------------------ + when S_WAVE_DOWN => + + -- End of waveform? + -- TODO: convert the numbers below to constaint. right now just make sure I'm not confused + if (unsigned(ram_waveform_addrb) - reg_scale_time < (resize(unsigned(reg_wave_start_addr), 20) sll 8)) or (unsigned(ram_waveform_addrb) = 0) then + ram_waveform_addrb <= (others=>'0'); -- reset the address for the next waveform + cnt_addr <= (others=>'0'); + -- If the end of the pulse table is reached then go to idle, increment pulse address for the next waveform otherwise + if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_LEN_PULSE-1, C_BITS_ADDR_PULSE))) then + ram_pulse_addrb <= (others=>'0'); + pc <= (others=>'0'); + sm_state <= S_IDLE; + + else -- increment pulse address for the next waveform + ram_pulse_addrb <= pc; + sm_state <= S_LOAD; + end if; + + -- Output waveform from RAM with decremented address + else + cnt_wave_len <= cnt_wave_len + 1; + -- ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - reg_scale_time); + -- TODO: replace the above line with the following code if fall should be EXACTLY the same as rise + if (sm_state_d1 = S_WAVE_FLAT) or (sm_state_d1 = S_WAVE_UP) then -- previous state was either S_WAVE_UP or S_WAVE_FLAT, so the ram_waveform_addrb should be whatever it was in the S_WAVE_UP state + ram_waveform_addrb <= wave_last_addr; -- get the last address of the wavetable + else + ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - reg_scale_time); + end if; + cnt_addr <= cnt_addr - 1; + end if; + v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain); + sm_wavedata <= v_ram_waveform_doutb_multiplied(30 downto 15); + sm_wavedata_dv <= '1'; + + ------------------------------------------------------------------------ + -- Default + ------------------------------------------------------------------------ + when others => + sm_state <= S_IDLE; + + end case; + end if; + end process; + + busy <= sm_busy; + + -- AXI-Stream output. + -- TBD: This should come from a FIFO + -- TODO: the bits are not correct, should be top bits (C_BITS_GAIN_FACTOR + 16 downto C_BITS_GAIN_FACTOR), but for now just make it this way so modelsim can simulate + axis_tdata <= sm_wavedata; -- axi stream output data, this output should be multiplied by the gain factor, then take the top 16 bits + axis_tvalid <= sm_wavedata_dv; -- axi_stream output data valid + + -- TBD : Generate in state machine? + axis_tlast <= '0'; -- axi_stream output last +end channel; \ No newline at end of file diff --git a/src/hdl/pkg/iopakb.vhd b/src/hdl/pkg/iopakb.vhd new file mode 100644 index 0000000..b984952 --- /dev/null +++ b/src/hdl/pkg/iopakb.vhd @@ -0,0 +1,9531 @@ +-- ---------------------------------------------------------------------------- +-- +-- Copyright (c) Mentor Graphics Corporation, 1982-1996, All Rights Reserved. +-- UNPUBLISHED, LICENSED SOFTWARE. +-- CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE +-- PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS. +-- +-- +-- PackageName : std_iopak +-- Title : Package Body for STD_IOPAK +-- Purpose : This package contains additional support for +-- : performing text IO. +-- : +-- Comments : +-- : +-- Assumptions : none +-- Limitations : none +-- Known Errors: none +-- ---------------------------------------------------------------------------- +-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<< +-- ---------------------------------------------------------------------------- +-- Mentor Graphics Corporation owns the sole copyright to this software. +-- Under International Copyright laws you (1) may not make a copy of this +-- software except for the purposes of maintaining a single archive copy, +-- (2) may not derive works herefrom, (3) may not distribute this work to +-- others. These rights are provided for information clarification, +-- other restrictions of rights may apply as well. +-- +-- This is an "Unpublished" work. +-- ---------------------------------------------------------------------------- +-- >>>>>>>>>>>>>>>>>>>>>>> License NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<< +-- ---------------------------------------------------------------------------- +-- This software is further protected by specific source code and/or +-- object code licenses provided by Mentor Graphics Corporation. Use of this +-- software other than as provided in the licensing agreement constitues +-- an infringement. No modification or waiver of any right(s) shall be +-- given other than by the written authorization of an officer of The +-- Mentor Graphics Corporation. +-- ---------------------------------------------------------------------------- +-- >>>>>>>>>>>>>>>>>>>>>>> Proprietary Information <<<<<<<<<<<<<<<<<<<< +-- ---------------------------------------------------------------------------- +-- This source code contains proprietary information of Mentor Graphics +-- Corporation and shall not be disclosed other than as provided in the software +-- licensing agreement. +-- ---------------------------------------------------------------------------- +-- >>>>>>>>>>>>>>>>>>>>>>>>>>>>> Warrantee <<<<<<<<<<<<<<<<<<<<<<<<<<<< +-- ---------------------------------------------------------------------------- +-- Mentor Graphics Corporation MAKES NO WARRANTY OF ANY KIND WITH REGARD TO +-- THE USE OF THIS SOFTWARE, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS +-- FOR A PARTICULAR PURPOSE. +-- ---------------------------------------------------------------------------- +-- Modification History : +-- ---------------------------------------------------------------------------- +-- Version No: | Author: | Mod. Date: | Changes Made: +-- v1.000 | M.K.Dhodhi | 10/26/91 | Production Release +-- v1.100 | M.K.Dhodhi | 11/19/91 | Compatible w/ Vantage 3.650 Release +-- v1.110 | wdb | 01/27/92 | compatible w/Intermetrics +-- v1.110 | M.K.Dhodhi | 02/13/92 | fixing bug in T0_String input time +-- | fixing comment in SOX_Machine +-- v1.110 | M.K.Dhodhi | 03/06/92 | production release +-- v1.200 | M.K.Dhodhi | 04/21/92 | stand alone version +-- v1.130 | M.K.Dhodhi | 08/03/92 | production release +-- v1.140 | M.K.Dhodhi | 11/05/92 | fixing real 0.0 case for To_String +-- | | an extra loop in default time. +-- v1.150 | M.K.Dhodhi | 11/17/92 | extending fscan upto 20 arguments. +-- | fixing default 0 time. +-- v1.160 | M.K.Dhodhi | 02/11/93 | fixing Find_Char +-- v1.610 | wrm | 03/30/93 | fixed error assertions in From_String, From_XString +-- v1.700 B | W.R. Migatz | 05/03/93 | Beta release - changes to all f routines (not fprint) +-- | modified str*cpy and str*cmp +-- | fixed memory leak +-- v1.700 | W.R. Migatz | 05/25/93 | production release - change to fscan with %t to allow time unit +-- v1.800 | W.R. Migatz | 07/28/93 | combining into 1 file, mentor support, and From_String(time) bug fix +-- v2.000 | W.R. Migatz | 07/21/94 | production release - fix bug in fprint, fs ps ns timing changes +-- v2.100 | W.R. Migatz | 01/10/96 | production release +-- | Initialization banner removed +-- v2.110 | W.R. Migatz | 04/02/96 | Fixed Find_Char and To_String(TIME) bugs +-- | Find_char did not stop at a NUL character +-- | To_String(TIME) did not handle a precision of 0 +-- v2.2 | B. Caslis | 07/25/96 | Updated for Mentor Graphics Release +-- ---------------------------------------------------------------------------- + +PACKAGE BODY std_iopak is + + -- ************************************************************************ + -- Display Banner + -- ************************************************************************ + + FUNCTION DisplayBanner return BOOLEAN is + + BEGIN + ASSERT FALSE + report LF & + "-- Initializing Std_Developerskit (Std_IOpak package v2.10)" & LF & + "-- Copyright by Mentor Graphics Corporation" & LF & + "-- [Please ignore any warnings associated with this banner.]" + severity NOTE; + return TRUE; + END; + + --CONSTANT StdIOpakBanner : BOOLEAN := DisplayBanner; + CONSTANT StdIOpakBanner : BOOLEAN := TRUE; + + TYPE char_to_hex_table is array (character'low To character'high) of Integer; + TYPE char_to_oct_table is array (character'low TO character'high) of integer; + SUBTYPE INT8 is INTEGER RANGE 0 to 7; + + CONSTANT WarningsOn : BOOLEAN := TRUE; + CONSTANT END_OF_LINE_MARKER : STRING(1 TO 2) := LF & ' '; + CONSTANT invalid_input : INTEGER := -201; +-- ------------------------------------------------------------------------------ +-- ------------------------------------------------------------------------------ +-- P L E A S E N O T E +-- Following routines are hidden, they are not visible to the user of +-- this package but are used internally +-- ----------------------------------------------------------------------------- +--+----------------------------------------------------------------------------- +--| Procedure Name : S_Machine +--| hidden +--| Overloading : None +--| +--| Purpose : Finite State automaton to recognise a string format. +--| format will be broken into field width, precision +--| and justification (left or right). +--| +--| Parameters : fwidth -- output, INTEGER, field width +--| precision -- output, INTEGER, precison +--| justify -- OUTPUT, BIT +--| '0' right justified, +--| '1' left justified +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : +--| +--| NOTE : +--| This procedure is +--| called in the function To_String. +--| +--| Use : +--| VARIABLE fmt : STRING(1 TO format'LENGTH) := format; +--| VARIABLE fw : INTEGER; +--| VARIABLE precis : INTEGER; +--| VARIABLE justfy : BIT; +--| +--| S_Machine(fw, precis, justy, fmt); +--| +--|----------------------------------------------------------------------------- + PROCEDURE S_Machine ( VARIABLE fwidth : OUT INTEGER; + VARIABLE precison : OUT INTEGER; + VARIABLE justify : OUT BIT; + CONSTANT format : IN STRING + ) IS + VARIABLE state : INT8 := 0; + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE ch : CHARACTER; + VARIABLE index : INTEGER := 1; + VARIABLE fw : INTEGER := 0; + VARIABLE pr : INTEGER := 0; + + BEGIN + -- make sure first character is '%' if not error + ch := fmt(index); + IF (fmt(index) /= '%') THEN + ASSERT false + REPORT " Format Error --- first character of format " & + " is not '%' as expected." + SEVERITY ERROR; + RETURN; + END IF; + justify := '0'; -- default is right justification + + WHILE (state /= 3) LOOP + IF (index < format'LENGTH) THEN + index := index + 1; + ch := fmt(index); + CASE state IS + WHEN 0 => + IF (ch ='-') THEN + state := 1; -- justify + ELSIF (ch >= '0' AND ch <= '9') THEN + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 2; -- digits + ELSIF (ch = 's') THEN + state := 3; -- end state + ELSIF (ch = '.') THEN + state := 4; + ELSIF (ch = '%') THEN + state := 5; + ELSE + state := 6; -- error + END IF; + + WHEN 1 => + justify := '1'; -- left justfy + IF (ch >= '0' AND ch <= '9') THEN + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 2; + ELSIF (ch = '.') THEN + state := 4; + ELSIF (ch = 's') THEN + state := 3; + justify := '0'; -- %-s is equivalent to %s + ELSE + state := 6; -- error + END IF; + + WHEN 2 => -- + IF (ch >= '0' AND ch <= '9') THEN + fw := fw * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); + state := 2; + ELSIF (ch = 's') THEN + state := 3; + ELSIF (ch = '.') THEN + state := 4; + ELSE + state := 6; -- error + END IF; + + WHEN 3 => -- s state + -- s format successfully recognized exit now. + EXIT; + + WHEN 4 => -- . state + IF (ch >= '0' AND ch <= '9') THEN + pr := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 7; + ELSE + state := 6; -- error + END IF; + + WHEN 5 => -- print % + EXIT; + + WHEN 6 => -- error state + -- print error message + ASSERT false + REPORT " Format error --- expected %s format " + SEVERITY ERROR; + EXIT; + + WHEN 7 => + -- precision + IF (ch >= '0' AND ch <= '9') THEN + pr := pr * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); + state := 7; + ELSIF (ch = 's') THEN + state := 3; + ELSE + state := 6; -- error + END IF; + END CASE; + ELSE + assert false + report " Format Error: Observed =" & fmt &LF + & " Expected = %s (detected by S_Machine) " + severity ERROR; + exit; + END IF; + + END LOOP; + + IF (fw > max_string_len) THEN + fwidth := max_string_len; + ELSE + fwidth := fw; + END IF; + + precison := pr; + RETURN; + END; + +--+----------------------------------------------------------------------------- +--| Function Name : SOX_Machine +--| hidden +--| Overloading : None +--| +--| Purpose : Finite State automaton to recognise a binary_vector +--| to a string format. +--| format will be broken into field width, precision +--| and justification (left or right) and notation (binary, +--| octal or hex ). +--| +--| Parameters : fwidth -- output, INTEGER, field width +--| precision -- output, INTEGER, precison +--| justify -- OUTPUT, BIT +--| '0' right justified, +--| '1' left justified +--| str_type -- output, character, +--| -- can be any of the characters s, O (o), X (x) +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : +--| +--| NOTE : +--| This procedure is +--| called in the function To_String. +--| +--| Use : +--| VARIABLE fmt : STRING(1 TO format'LENGTH) := format; +--| VARIABLE fw : INTEGER; +--| VARIABLE precis : INTEGER; +--| VARIABLE justfy : BIT; +--| VARIABLE sttype : Character; +--| +--| SOX_Machine(fw, precis, justy, sttype,fmt); +--| +--|----------------------------------------------------------------------------- + PROCEDURE SOX_Machine ( VARIABLE fwidth : OUT INTEGER; + VARIABLE precison : OUT INTEGER; + VARIABLE justify : OUT BIT; + VARIABLE str_type : OUT character; + CONSTANT format : IN STRING + ) IS + VARIABLE state : INT8 := 0; + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE ch : CHARACTER; + VARIABLE index : INTEGER := 1; + VARIABLE fw : INTEGER := 0; + VARIABLE pr : INTEGER := 0; + + BEGIN + -- make sure first character is '%' if not error + ch := fmt(index); + IF (fmt(index) /= '%') THEN + ASSERT false + REPORT " Format Error --- first character of format " & + " is not '%' as expected." + SEVERITY ERROR; + RETURN; + END IF; + justify := '0'; -- default is right justification + + WHILE (state /= 3) LOOP + IF (index < format'LENGTH) THEN + index := index + 1; + ch := fmt(index); + CASE state IS + WHEN 0 => + IF (ch ='-') THEN + state := 1; -- justify + ELSIF (ch >= '0' AND ch <= '9') THEN + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 2; -- digits + ELSIF ((ch = 's') OR (ch = 'o') OR (ch ='O') + OR (ch = 'x') OR (ch = 'X')) THEN + state := 3; -- end state + str_type := ch; + ELSIF (ch = '.') THEN + state := 4; + ELSIF (ch = '%') THEN + state := 5; + ELSE + state := 6; -- error + END IF; + + WHEN 1 => + justify := '1'; -- left justfy + IF (ch >= '0' AND ch <= '9') THEN + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 2; + ELSIF (ch = '.') THEN + state := 4; + ELSIF ((ch = 's') OR (ch = 'o') OR (ch ='O') + OR (ch = 'x') OR (ch = 'X')) THEN + state := 3; + justify := '0'; -- %- is equivalent to % + ELSE + state := 6; -- error + END IF; + + WHEN 2 => -- + IF (ch >= '0' AND ch <= '9') THEN + fw := fw * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); + state := 2; + ELSIF ((ch = 's') OR (ch = 'o') OR (ch ='O') + OR (ch = 'x') OR (ch = 'X')) THEN + state := 3; -- end state + str_type := ch; + ELSIF (ch = '.') THEN + state := 4; + ELSE + state := 6; -- error + END IF; + + WHEN 3 => -- sox state + -- sox format successfully recognized exit now. + EXIT; + + WHEN 4 => -- . state + IF (ch >= '0' AND ch <= '9') THEN + pr := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 7; + ELSE + state := 6; -- error + END IF; + + WHEN 5 => -- print % + EXIT; + + WHEN 6 => -- error state + -- print error message + ASSERT false + REPORT " Format error --- expected %s format " + SEVERITY ERROR; + EXIT; + + WHEN 7 => + -- precision + IF (ch >= '0' AND ch <= '9') THEN + pr := pr * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); + state := 7; + ELSIF ((ch = 's') OR (ch = 'o') OR (ch ='O') + OR (ch = 'x') OR (ch = 'X')) THEN + state := 3; -- end state + str_type := ch; + ELSE + state := 6; -- error + END IF; + END CASE; + ELSE + assert false + report " Format Error: Observed =" & fmt &LF + & " Expected = %s or %o r %x (detected by SOX_Machine) " + severity ERROR; + exit; + END IF; + + END LOOP; + + IF (fw > max_string_len) THEN + fwidth := max_string_len; + ELSE + fwidth := fw; + END IF; + + precison := pr; + RETURN; + END; + +--+----------------------------------------------------------------------------- +--| Function Name : F_Machine +--| hidden +--| Overloading : None +--| +--| Purpose : Finite State automaton to recognise real number format. +--| format will be broken into field width, precision +--| and justification (left or right). +--| +--| Parameters : fwidth -- output, INTEGER, field width +--| precision -- output, INTEGER, Precision +--| justify -- OUTPUT, BIT +--| '0' right justified, +--| '1' left justified +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : INTEGER, length of output string. +--| +--| NOTE : +--| This procedure is +--| called in the funtion To_String when need to +--| a real number string. +--| +--| Use : +--| VARIABLE fmt : STRING(1 TO format'LENGTH) := format; +--| VARIABLE fw : INTEGER; +--| VARIABLE precis : INTEGER; +--| VARIABLE justfy : BIT; +--| +--| F_Machine(fw, precis, justy, fmt); +--| +--| +--|----------------------------------------------------------------------------- + PROCEDURE F_Machine ( VARIABLE fwidth : OUT INTEGER; + VARIABLE precison : OUT INTEGER; + VARIABLE justify : OUT BIT; + CONSTANT format : IN STRING + ) IS + VARIABLE state : INT8 := 0; -- starting state + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE ch : CHARACTER; + VARIABLE index : INTEGER := 1; + VARIABLE fw : INTEGER := 0; + VARIABLE pr : INTEGER := 0; + + BEGIN + + -- make sure first character is '%' if not error + ch := fmt(index); + IF (fmt(index) /= '%') THEN + ASSERT false + REPORT " Format Error --- first character of format " & + " is not '%' as expected." + SEVERITY ERROR; + return; + END IF; + justify := '0'; -- default is right justification + + WHILE (state /= 3) LOOP + IF (index < format'LENGTH) THEN + index := index + 1; + ch := fmt(index); + CASE state IS + WHEN 0 => + IF (ch ='-') THEN + state := 1; -- justify + ELSIF (ch >= '0' AND ch <= '9') THEN + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 2; -- digits + ELSIF (ch = 'f') THEN + state := 3; -- end state + ELSIF (ch = '.') THEN + state := 4; + ELSIF (ch = '%') THEN + state := 5; + ELSE + state := 6; -- error + END IF; + + WHEN 1 => + justify := '1'; -- left justfy + IF (ch >= '0' AND ch <= '9') THEN + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 2; + ELSIF (ch = '.') THEN + state := 4; + ELSIF (ch = 'f') THEN + state := 3; + justify := '0'; -- %-f is equivalent to %f + ELSE + state := 6; -- error + END IF; + + WHEN 2 => -- + IF (ch >= '0' AND ch <= '9') THEN + fw := fw * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); + state := 2; + ELSIF (ch = 'f') THEN + state := 3; + ELSIF (ch = '.') THEN + state := 4; + ELSE + state := 6; + END IF; + + WHEN 3 => -- f state + -- fromat successfully recognized, exit now. + EXIT; + + WHEN 4 => -- . state + IF (ch >= '0' AND ch <= '9') THEN + pr := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 7; + ELSE + state := 6; -- error + END IF; + + WHEN 5 => -- print % + EXIT; + + WHEN 6 => -- error state + -- print error message + ASSERT false + REPORT " Format Error --- expected %f format. " + SEVERITY ERROR; + EXIT; + + WHEN 7 => + -- precision + IF (ch >= '0' AND ch <= '9') THEN + pr := pr * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); -- to_digit + state := 7; + ELSIF (ch = 'f') THEN + state := 3; + ELSE + state := 6; -- error + END IF; + END CASE; + ELSE + assert false + report " Format Error: Observed =" & fmt &LF + & " Expected = %f (detected by F_Machine) " + severity ERROR; + exit; + END IF; + + END LOOP; + + IF (fw > max_string_len) THEN + fwidth := max_string_len; + ELSE + fwidth := fw; + END IF; + + IF (pr=0) THEN + precison := 6; -- use default precision + ELSE + precison := pr; + END IF; + RETURN; + END F_Machine; +--+----------------------------------------------------------------------------- +--| Function Name : D_Machine +--| hidden +--| Overloading : None +--| +--| Purpose : Finite State automaton to recognise integer format. +--| format will be broken into field width, precision +--| and justification (left or right). +--| +--| Parameters : fwidth -- output, INTEGER, field width +--| precision -- output, INTEGER, Precision +--| justify -- OUTPUT, BIT +--| '0' right justified, +--| '1' left justified +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : INTEGER, length of output string. +--| +--| NOTE : +--| This procedure is +--| called in the funtion To_String when need to +--| a real number string. +--| +--| Use : +--| VARIABLE fmt : STRING(1 TO format'LENGTH) := format; +--| VARIABLE fw : INTEGER; +--| VARIABLE precis : INTEGER; +--| VARIABLE justfy : BIT; +--| +--| D_Machine(fw, precis, justy, fmt); +--| +--|----------------------------------------------------------------------------- + PROCEDURE D_Machine ( VARIABLE fwidth : OUT INTEGER; + VARIABLE precison : OUT INTEGER; + VARIABLE justify : OUT BIT; + CONSTANT format : IN STRING + ) IS + VARIABLE state : INT8 := 0; -- starting state + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE ch : CHARACTER; + VARIABLE index : INTEGER := 1; + VARIABLE fw : INTEGER := 0; + VARIABLE pr : INTEGER := 0; + + BEGIN + -- make sure first character is '%' if not error + ch := fmt(index); + IF (fmt(index) /= '%') THEN + ASSERT false + REPORT " Format Error --- first character of format " & + " is not '%' as expected." + SEVERITY ERROR; + return; + END IF; + justify := '0'; -- default is right justification + WHILE (state /= 3) LOOP + IF (index < format'LENGTH) THEN + index := index + 1; + ch := fmt(index); + CASE state IS + WHEN 0 => IF (ch ='-') THEN + state := 1; -- justify + ELSIF (ch >= '0' AND ch <= '9') THEN -- to_digit + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); + state := 2; -- digits state + ELSIF (ch = 'd') THEN + state := 3; -- end state + ELSIF (ch = '.') THEN + state := 4; + ELSIF (ch = '%') THEN + state := 5; + ELSE + state := 6; -- error + END IF; + + WHEN 1 => justify := '1'; -- left justfy + IF (ch >= '0' AND ch <= '9') THEN -- to_digit + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); + state := 2; + ELSIF (ch = '.') THEN + state := 4; + ELSIF (ch = 'd') THEN + state := 3; + justify := '0'; -- %-d is equivalent to %d + ELSE + state := 6; -- error + END IF; + + WHEN 2 => -- digits state + IF (ch >= '0' AND ch <= '9') THEN + fw := fw * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); + state := 2; + ELSIF (ch = 'd') THEN + state := 3; + ELSIF (ch = '.') THEN + state := 4; + ELSE + state := 6; + END IF; + + WHEN 3 => -- d state + -- fromat successfully recognized, exit now. + EXIT; + + WHEN 4 => -- . state + IF (ch >= '0' AND ch <= '9') THEN + pr := CHARACTER'POS(ch) - CHARACTER'POS('0'); -- to_digit + state := 7; + ELSE + state := 6; -- error + END IF; + + WHEN 5 => -- print % + EXIT; + + WHEN 6 => -- error state + -- print error message + ASSERT false + REPORT " Format Error --- expected %f format. " + SEVERITY ERROR; + EXIT; + + WHEN 7 => -- precision + IF (ch >= '0' AND ch <= '9') THEN + pr := pr * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); -- to_digit + state := 7; + ELSIF (ch = 'd') THEN + state := 3; + ELSE + state := 6; -- error + END IF; + END CASE; + ELSE + assert false + report " Format Error: Observed =" & fmt &LF + & " Expected = %d (detected by D_Machine) " + severity ERROR; + exit; + END IF; + END LOOP; + -- decide field width (fwidth) + IF (fw > max_string_len) THEN + fwidth := max_string_len; + ELSE + fwidth := fw; + END IF; + precison := pr; -- set precision + RETURN; + END D_Machine; + ---------------------------------------------------------- + -- Function Name : i_TRUNC + -- hidden + -- Parameters : + -- in :: Real_val : real; + -- Returns : Integer portions of a real number + -- Purpose : TO obtain the integer part of a general real + -- Notes : + ---------------------------------------------------------- + FUNCTION i_TRUNC ( CONSTANT real_val : IN real + ) RETURN integer IS + VARIABLE rval : real; + VARIABLE i : integer; + begin + -- find the integer value rounded to integer number less than + -- the real value. if the real number is 0.0 then return 0 + if (real_val = 0.0) then + i := 0; + else + rval := real_val - 0.5; + i := INTEGER(rval); + end if; + RETURN i; + END i_TRUNC; + + ------------------------------------------------------- + -- Function Name : i_FRAC + -- hidden + -- Parameters : + -- in :: Real_val : real; + -- Returns : Fractional portion of the real and no of fractional + -- digits present + -- Purpose : to obtain the fractional part of a general real + -- Notes : + ---------------------------------------------------------- + PROCEDURE i_FRAC ( CONSTANT real_val : IN real; + VARIABLE f_val : OUT INTEGER; + VARIABLE f_digits : OUT INTEGER + ) IS + VARIABLE rval : real; + VARIABLE ival : integer; + VARIABLE i : integer := 0; + begin + ival := i_TRUNC(real_val); + rval := real_val - REAL(ival); + i := INTEGER(rval * 1000000.0); + IF (i>=0 and i<=9) THEN + f_digits := 1; + ELSIF (i>=10 and i<=99) THEN + f_digits := 2; + + ELSIF (i>=10 and i<=99) THEN + f_digits := 2; + + ELSIF (i>=100 and i<=999) THEN + f_digits := 3; + + ELSIF (i>=1000 and i<=9999) THEN + f_digits := 4; + + ELSIF (i>=10000 and i<=99999) THEN + f_digits := 5; + + ELSIF (i>=100000 and i<=999999) THEN + f_digits := 6; + ELSE + f_digits := 0; + END IF; + + f_val := i; + return; + + end i_FRAC; +--|----------------------------------------------------------------------------- + +--+----------------------------------------------------------------------------- +--| Function Name : Is_White +--| hidden. +--| Overloading : None +--| +--| Purpose : Test whether a character is a blank, a tab or +--| a newline character. +--| +--| Parameters : +--| c - input Character. +--| +--| Result :Booelan -- True if the argument c is a blank or a tab(HT), +--| or a line feed (LF), or carriage return (CR). false otherwise. +--| +--| +--| See Also : Is_Space +--|----------------------------------------------------------------------------- + FUNCTION Is_White ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN IS + VARIABLE result : BOOLEAN; + BEGIN + IF ( (c = ' ') OR (c = HT) OR (c = CR) OR (c=LF) ) THEN + result := TRUE; + ELSE + result := FALSE; + END IF; + RETURN result; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : Find_NonBlank +--| hidden +--| Overloading : for extra parameter - index (see below) +--| +--| Purpose : Find first non_blank character in a string. +--| +--| Parameters : +--| str_in - input , +--| +--| Result : Natural, index of non_blank character. If string +--| has all the white character then str_in'LENGTH is +--| returned; +--| +--| NOTE : +--| +--| Use : +--| VARIABLE s_flag : String(1 TO 10) := " TRUE"; +--| VARIABLE idx: Natural +--| +--| idx := Find_NonBlank (s_flag); +--| +--|----------------------------------------------------------------------------- + FUNCTION Find_NonBlank ( CONSTANT str_in : IN STRING + ) RETURN NATURAL IS + VARIABLE str_copy : STRING (1 TO str_in'LENGTH) := str_in; + VARIABLE index : Natural := 1; + VARIABLE ch : character; + + BEGIN + loop + EXIT WHEN ( (index > str_in'LENGTH) or (str_copy(index) = NUL) ); + if Is_White(str_copy(index)) then + index := index + 1; + else + EXIT; + end if; + end loop; + return index; +-- +-- old code +-- +-- ch := str_copy(index); +-- while ( ( index < str_in'LENGTH) AND (Is_White(ch) ) ) LOOP +-- index := index + 1; +-- ch := str_copy(index); +-- end LOOP; +-- return index; + END; + + +--+----------------------------------------------------------------------------- +--| Function Name : Find_NonBlank +--| hidden +--| Overloading : for no index parameter - see abov +--| +--| Purpose : Find first non_blank character in a string, starting +--| from position indicated by index. +--| +--| Parameters : str_in - input string , +--| index - input NATURAL +--| +--| Result : Natural, index of non_blank character. If string +--| has all the white character then str_in'LENGTH is +--| returned; +--| +--| NOTE : assumes string has left index of 1 +--| +--| Use : +--| VARIABLE s_flag : String(1 TO 10) := " TRUE"; +--| VARIABLE idx: Natural +--| +--| idx := Find_NonBlank (s_flag); +--| +--|----------------------------------------------------------------------------- + FUNCTION Find_NonBlank ( CONSTANT str_in : IN STRING; + CONSTANT index : IN NATURAL + ) RETURN NATURAL IS + + VARIABLE ch : character; + VARIABLE indx : integer := index; + + BEGIN + loop + EXIT WHEN ( (indx > str_in'LENGTH) or (str_in(indx) = NUL) ); + if Is_White(str_in(indx)) then + indx := indx + 1; + else + EXIT; + end if; + end loop; + return indx; + END; + + +--+----------------------------------------------------------------------------- +--| Function Name : get_token +--| hidden +--| Overloading : None +--| +--| Purpose : To get a token from a format string. +--| used in fprint procedure. +--| +--| +--| Parameters : +--| format -- input, STRING, +--| index -- input_output, INTEGER, +--| at input it represents the beginning +--| position of the word in the format +--| string. When procedure terminates +--| index represent the end of word. +--| token -- output, STRING, holds the result. +--| +--| NOTE : +--| +--| --------------------------------------------------------------------------- + PROCEDURE get_token ( CONSTANT format : IN STRING; + VARIABLE index : INOUT INTEGER; + VARIABLE token : OUT STRING + ) IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE indx : INTEGER := index; + VARIABLE res_str : STRING(1 TO max_token_len); + -- % - fw.precison s + VARIABLE i : INTEGER := 1; + BEGIN + -- make sure it is a format string + ASSERT (fmt(indx) = '%') + REPORT " get_token --- not a format string " + SEVERITY ERROR; + res_str(i) := fmt(indx); + + fmt_loop: LOOP + i := i + 1; + indx := indx + 1; + res_str(i) := fmt(indx); + EXIT fmt_loop WHEN ( fmt(indx) = 's'); + END LOOP; + + index := indx; + token(1 TO i) := res_str(1 to i); -- fixing bug + RETURN; + END; + +--+----------------------------------------------------------------------------- +--| Function Name : print_str_buf +--| +--| Overloading : None +--| +--| Purpose : Prints a string according to format specification to a +--| buffer string. +--| +--| Parameters : +--| buf - input_output, string, +--| index - input_output, integer +--| format - input STRING, +--| arg - input STRING, +--| +--| Result : formated LINE. +--| +--| NOTE : This will be called in the fprint to print each +--| individual argument. +--| +--| +--|----------------------------------------------------------------------------- + PROCEDURE print_str_buf (VARIABLE buf : INOUT string; + VARIABLE index : INOUT integer; + CONSTANT format : IN STRING; + CONSTANT arg : IN STRING + ) IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE arg_copy : STRING(1 TO arg'LENGTH) := arg; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE non_nul_str : STRING(1 TO arg'LENGTH); + VARIABLE len : INTEGER := 0; + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + + BEGIN + -- call procedure S_Machine to split the format string + S_Machine(fw, precis, justfy, fmt); + + IF ((precis = 0) OR (precis > arg'LENGTH)) THEN + precis := arg'LENGTH; + END IF; + + -- check for the null argument + IF ((arg'LENGTH = 0) AND (fw = 0)) THEN + return; + + ELSIF ((arg'LENGTH = 0) AND (fw /= 0)) THEN + result(1 TO fw) := (OTHERS => ' '); + + ELSIF (arg'LENGTH /= 0) THEN -- argument is not null + + -- copy arg until NUL character encountered or precis to the non_nul_str; + + FOR i IN 1 TO precis LOOP + EXIT when (arg_copy(i) = NUL); + len := len + 1; + non_nul_str(len) := arg_copy(i); + END LOOP; + + IF (len > fw) THEN + fw := len; + END IF; + + IF (justfy = '1') THEN + result(1 TO len) := non_nul_str(1 to len); --modifying + FOR i IN len + 1 TO fw LOOP + result(i) := ' '; + END LOOP; + ELSE + FOR i IN 1 TO fw - len LOOP + result(i) := ' '; + END LOOP; + result(fw - len + 1 TO fw) := non_nul_str(1 to len); -- modifying + END IF; + END IF; + + for i IN 1 TO fw LOOP + EXIT when (index > buf'LENGTH); + buf(index) := result(i); + index := index + 1; + END LOOP; + + IF (index <= buf'LENGTH) THEN + buf(index) := ' '; -- leave one blank between two strings. + index := index - 1; + END IF; + RETURN; + + -- That's all + END; + + +--+----------------------------------------------------------------------------- +--| Function Name : print_str +--| +--| Overloading : None +--| +--| Purpose : Prints a string according to format specification. +--| +--| Parameters : +--| ll - input_output, LINE, +--| format - input STRING, +--| arg - input STRING, +--| +--| Result : formated LINE. +--| +--| NOTE : This will be called in the fprint to print each +--| individual argument. +--| +--| +--|----------------------------------------------------------------------------- + PROCEDURE print_str (VARIABLE ll : INOUT LINE; + CONSTANT format : IN STRING; + CONSTANT arg : IN STRING + ) IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE arg_copy : STRING(1 TO arg'LENGTH) := arg; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE non_nul_str : STRING(1 TO arg'LENGTH); + VARIABLE len : INTEGER := 0; + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + + BEGIN + -- call procedure S_Machine to split the format string + S_Machine(fw, precis, justfy, fmt); + + IF ((precis = 0) OR (precis > arg'LENGTH)) THEN + precis := arg'LENGTH; + END IF; + + -- check for the null argument + IF ((arg'LENGTH = 0) AND (fw = 0)) THEN + return; + + ELSIF ((arg'LENGTH = 0) AND (fw /= 0)) THEN + result(1 TO fw) := (OTHERS => ' '); + + ELSIF (arg'LENGTH /= 0) THEN -- argument is not null + -- copy arg until NUL character to the non_nul_str; + FOR i IN 1 TO precis LOOP + EXIT when (arg_copy(i) = NUL); + len := len + 1; + non_nul_str(len) := arg_copy(i); + END LOOP; + + IF ( len > fw) THEN + fw := len; + END IF; + + IF (justfy = '1') THEN + result(1 TO len) := non_nul_str(1 to len); -- modifying + FOR i IN len + 1 TO fw LOOP + result(i) := ' '; + END LOOP; + ELSE + FOR i IN 1 TO fw - len LOOP + result(i) := ' '; + END LOOP; + result(fw - len + 1 TO fw) := non_nul_str(1 to len); -- modifying + END IF; + END IF; + WRITE(ll, result(1 TO fw)); + RETURN; + + -- That's all + END; + + +--+----------------------------------------------------------------------------- +--| Function Name : print_str +--| +--| Overloading : None +--| +--| Purpose : writes a string according to format specification to an +--| ascii_text file +--| +--| Parameters : +--| asc_file - input, ASCII_TEXT, +--| format - input STRING, +--| arg - input STRING, +--| +--| Result : formated LINE. +--| +--| NOTE : This will be called in the fprint to print each +--| individual argument. +--| +--| +--|----------------------------------------------------------------------------- + PROCEDURE print_str (VARIABLE asc_file : OUT ASCII_TEXT; + CONSTANT format : IN STRING; + CONSTANT arg : IN STRING + ) IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE arg_copy : STRING(1 TO arg'LENGTH) := arg; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE non_nul_str : STRING(1 TO arg'LENGTH); + VARIABLE len : INTEGER := 0; + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + + BEGIN + -- call procedure S_Machine to split the format string + S_Machine(fw, precis, justfy, fmt); + + IF ((precis = 0) OR (precis > arg'LENGTH)) THEN + precis := arg'LENGTH; + END IF; + + -- check for the null argument + IF ((arg'LENGTH = 0) AND (fw = 0)) THEN + return; + + ELSIF ((arg'LENGTH = 0) AND (fw /= 0)) THEN + result(1 TO fw) := (OTHERS => ' '); + + ELSIF (arg'LENGTH /= 0) THEN -- argument is not null + -- copy arg until NUL character encountered or precison to the non_nul_str; + FOR i IN 1 TO precis LOOP + EXIT when (arg_copy(i) = NUL); + len := len + 1; + non_nul_str(len) := arg_copy(i); + END LOOP; + + IF (len > fw) THEN + fw := len; + END IF; + + IF (justfy = '1') THEN + result(1 TO len) := non_nul_str(1 to len); -- modifying + FOR i IN len + 1 TO fw LOOP + result(i) := ' '; + END LOOP; + ELSE + FOR i IN 1 TO fw - len LOOP + result(i) := ' '; + END LOOP; + result(fw - len + 1 TO fw) := non_nul_str(1 to len); -- modifying + END IF; + END IF; + + FOR i IN 1 TO fw LOOP + WRITE(asc_file, result(i)); + END LOOP; + + RETURN; + + -- That's all + END; + + + +-- ----------------------------------------------------------------------------- +-- ----------------------------------------------------------------------------- +-- V I S I B L E ROUTINES START HERE +-------------------------------------------------------------------------------- +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a boolean. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : A boolean true or false. +--| +--| NOTE : +--| +--| Use : +--| VARIABLE s_flag : String(1 TO 5) := " TRUE"; +--| VARIABLE OK : BOOLEAN +--| +--| OK := From_String (s_flag); +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN boolean IS + VARIABLE str_copy : STRING (1 TO str'LENGTH) := To_Upper(str); + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE result : boolean ; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_String -- input string has zero length. Boolean case" + severity ERROR; + RETURN FALSE; + END IF; + -- find the position of the first non_white character + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_String --- input string is empty "; + RETURN FALSE; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_String -- first non_white character is a NUL "; + RETURN FALSE; + END IF; + ch := str_copy(index); + CASE ch IS + WHEN 'F' => IF ((str'length - index) < 4 ) THEN + result := FALSE; + assert false + report " From_String --- input string has too few characters." + severity ERROR; + ELSIF ( ((str'length - index) = 4 ) AND + (str_copy(index TO index+4) = "FALSE") ) THEN + result := FALSE; + ELSIF ( (str_copy(index TO index + 4) = "FALSE") + AND( (str_copy(index + 5) = NUL) OR + Is_White( str_copy(index + 5) ) ) ) THEN + result := FALSE; + ELSE + result := FALSE; + assert false + report " From_String --- mismatch in boolean " + severity ERROR; + END IF; + + WHEN 'T' => IF ((str'length - index) < 3 ) THEN + result := FALSE; + assert false + report " From_String --- input string has too few characters " + severity ERROR; + ELSIF ( (( str'length - index ) = 3) AND + (str_copy(index TO index + 3 ) = "TRUE")) THEN + result := TRUE; + ELSIF ((str_copy(index TO index + 3) = "TRUE") + AND( (str_copy(index + 4) = NUL) OR + Is_White( str_copy(index + 4) ) ) ) THEN + result := TRUE; + ELSE + result := FALSE; + assert false + report "From_String --- mismatch in boolean " + severity ERROR; + END IF; + + WHEN OTHERS => result := FALSE; + assert false + report " From_String --- cannot find a boolean " + severity ERROR; + + END CASE; + RETURN result; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a bit. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : bit. +--| +--| NOTE : +--| +--| Use : +--| VARIABLE b_val : bit; +--| +--| b_val := From_String (" 100"); +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN bit IS + VARIABLE str_copy : STRING (1 TO str'LENGTH) := str; + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE result : bit ; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_String --- input string has zero length" + severity ERROR; + RETURN '0'; + END IF; + -- find the position of the first non_white character + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_String --- input string is empty "; + RETURN '0'; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_String -- first non_white character is a NUL "; + RETURN '0'; + END IF; + + ch := str_copy(index); + CASE ch IS + WHEN '1' => result := '1'; + WHEN '0' => result := '0'; + WHEN OTHERS => assert false + REPORT "From_String(str(" & To_String(index) & ") => " + & To_String(ch) & ") is an invalid character " + severity ERROR; + result := '0'; + END CASE; + RETURN RESULT; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a Severity_Level. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : Severity_Level +--| +--| NOTE : +--| +--| Use : +--| VARIABLE str10 : String(1 TO 10) := " WARNING"; +--| VARIABLE sev : severity_level; +--| +--| sev := From_String (str10); +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN severity_level IS + + VARIABLE str_copy : STRING (1 TO str'LENGTH):= To_Upper(str); + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE result : SEVERITY_LEVEL ; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_String --- input string has zero length " + severity ERROR; + RETURN NOTE; + END IF; + -- find the position of the first non_white character + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_String --- input string is empty "; + RETURN NOTE; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_String -- first non_white character is a NUL "; + RETURN NOTE; + END IF; + + ch := str_copy(index); + CASE ch IS + WHEN 'N' => result := NOTE; + IF ((str'length - index) < 3 ) THEN + assert false + report " From_String --- input string has too few characters." + severity ERROR; + + ELSIF ( (( str'length - index ) = 3) AND + (str_copy(index TO index + 3 ) = "NOTE")) THEN + result := NOTE; + ELSIF ((str_copy(index TO index + 3) = "NOTE") + AND( (str_copy(index + 4) = NUL) OR + Is_White( str_copy(index + 4) ) ) ) THEN + result := NOTE; + ELSE + assert false + report " From_String --- mismatch in string " + severity ERROR; + END IF; + + WHEN 'W' => result := NOTE; + IF ((str'length - index) < 6 ) THEN + assert false + report " From_String --- input string has too few characters." + severity ERROR; + + ELSIF ( (( str'length - index ) = 6) AND + (str_copy(index TO index + 6) = "WARNING")) THEN + result := WARNING; + ELSIF ((str_copy(index TO index + 6) = "WARNING") + AND( (str_copy(index + 7) = NUL) OR + Is_White( str_copy(index + 7) ) ) ) THEN + result := WARNING; + ELSE + assert false + report " From_String --- mismatch in string " + severity ERROR; + END IF; + + WHEN 'E' => result := NOTE; + IF ((str'length - index) < 4 ) THEN + assert false + report " From_String --- input string has too few characters." + severity ERROR; + + ELSIF ( (( str'length - index ) = 4) AND + (str_copy(index TO index + 4) = "ERROR")) THEN + result := ERROR; + ELSIF ((str_copy(index TO index + 4) = "ERROR") + AND( (str_copy(index + 5) = NUL) OR + Is_White( str_copy(index + 5) ) ) ) THEN + result := ERROR; + ELSE + assert false + report " From_String --- mismatch in string " + severity ERROR; + END IF; + + WHEN 'F' => result := NOTE; + IF ((str'length - index) < 6 ) THEN + assert false + report " From_String --- input string has too few characters." + severity ERROR; + + ELSIF ( (( str'length - index ) = 6) AND + (str_copy(index TO index + 6) = "FAILURE")) THEN + result := FAILURE; + ELSIF ((str_copy(index TO index + 6) = "FAILURE") + AND( (str_copy(index + 7) = NUL) OR + Is_White( str_copy(index + 7) ) ) ) THEN + result := FAILURE; + ELSE + assert false + report " From_String --- mismatch in string " + severity ERROR; + END IF; + + WHEN OTHERS => result := NOTE; + assert false + report " From_String --- cannot find a severity-level " + severity ERROR; + END CASE; + return result; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a character. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : Character +--| +--| NOTE : +--| +--| Use : +--| VARIABLE str10 : String(1 TO 10) := "WARNING "; +--| VARIABLE ch : character; +--| +--| ch := From_String (str10); +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN character IS + VARIABLE str_copy : STRING (1 TO str'LENGTH) := str; + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE result : character; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_String --- input string has a null range " + severity ERROR; + RETURN NUL; + + END IF; + -- left most character of the string is returned + result := str_copy(1); + IF (result = NUL) THEN + assert false + report " From_String --- First character is a NUL " + severity ERROR; + END IF; + return result; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to an Integer. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : Integer +--| +--| NOTE : +--| +--| Use : +--| VARIABLE n : Integer; +--| +--| n := From_String ("32 56"); +--| This statement will set n to integer 32. +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN INTEGER IS + VARIABLE str_copy : STRING (1 TO str'LENGTH) := str; + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE result : INTEGER := 0; + VARIABLE neg_sign : boolean := false; + VARIABLE invalid : boolean := false; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_String --- input string has zero length " + severity ERROR; + RETURN INTEGER'LEFT; + END IF; + -- find the position of the first non_white character + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_String --- input string is empty "; + RETURN INTEGER'LEFT; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_String -- first non_white character is a NUL "; + RETURN INTEGER'LEFT; + END IF; + ch := str_copy(index); + -- check for - sign or + sign + IF (ch = '-') Then + neg_sign := NOT neg_sign; + index := index + 1; + ch := str_copy(index); -- get_char + elsif (ch = '+') then + index := index + 1; + ch := str_copy(index); -- get_char + END IF; + + -- Strip off leading zero's + While ( (ch = '0') AND (index < str'LENGTH)) LOOP + index := index + 1; + ch := str_copy(index); -- get_char + END LOOP; + For i in index TO str'LENGTH LOOP + ch := str_copy(i); + if (Is_Digit(ch)) then + result := result * 10 + ( CHARACTER'POS(ch) + - CHARACTER'POS('0') ); -- to digit + elsif ((Is_White(ch)) OR (ch = NUL)) THEN + exit; + else + invalid := TRUE; + result := INTEGER'LEFT; + ASSERT FALSE + REPORT "From_String(str(" & To_String(i) & ") => " + & To_String(ch) & ") is an invalid character " + SEVERITY ERROR; + exit; + end if; + end loop; + if ( neg_sign AND (not invalid) )THEN + result := - result; + END IF; + return result; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a real. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : real value +--| +--| NOTE : +--| +--| Use : +--| VARIABLE n : real ; +--| +--| n := From_String (" -354.78"); +--| This statement will set n to real value -354.78. +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN REAL IS + VARIABLE str_copy : STRING (1 TO str'LENGTH) := str; + VARIABLE index : Natural; + VARIABLE digit_val : Integer; + VARIABLE power : Integer; + VARIABLE integ_part : Integer := 0; + VARIABLE fract_part : Integer := 0; + VARIABLE r : real := 0.0; + VARIABLE ch : character; + VARIABLE neg_sign : boolean := false; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_String --- input string has zero length " + severity ERROR; + RETURN REAL'LEFT; + + END IF; + -- find the position of the first non_white character + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_String --- input string is empty "; + RETURN REAL'LEFT; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_String -- first non_white character is a NUL "; + RETURN REAL'LEFT; + END IF; + ch := str_copy(index); + -- check for - sign or + sign + IF (ch = '-') Then + neg_sign := NOT neg_sign; + index := index + 1; + ch := str_copy(index); -- get_char + elsif (ch = '+') then + index := index + 1; + ch := str_copy(index); -- get_char + END IF; + + -- Strip off leading zero's + While ( (ch = '0') AND (index < str'LENGTH)) LOOP + index := index + 1; + ch := str_copy(index); -- get_char + END LOOP; + + -- convert the integeral part by going through the loop + -- until '.' is encountered + + WHILE ((ch /= '.') AND (index < str'LENGTH)) LOOP + + if (Is_digit(ch)) THEN + integ_part := integ_part * 10 + ( CHARACTER'POS(ch) + - CHARACTER'POS('0') ); -- to digit + else + ASSERT FALSE + REPORT "From_String(str(" & To_String(index) & ") => " + & To_String(ch) & ") is an invalid character " + SEVERITY ERROR; + return real'LEFT; + end if; + index := index + 1; + ch := str_copy(index); + END LOOP; + -- convert the fractional part to real value + -- + if ( ch = '.') THEN + index := index + 1; + END IF; + power := 0; + For i IN index TO str'LENGTH LOOP + ch := str_copy(i); + if (Is_digit(ch)) THEN + power := power + 1; + fract_part := fract_part * 10 + ( CHARACTER'POS(ch) + - CHARACTER'POS('0') ); -- to digit + elsif ((Is_White(ch)) OR (ch = NUL)) THEN + exit; + else + ASSERT FALSE + REPORT "From_String(str(" & To_String(i) & ") => " + & To_String(ch) & ") is an invalid character " + SEVERITY ERROR; + return real'LEFT; + end if; + end loop; + + r := real(integ_part) + real(fract_part) / 10.0 ** power; + if neg_sign THEN + r := - r; + END IF; + return r; + END; +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to an std_ulogic. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : std_ulogic +--| +--| NOTE : +--| +--| Use : +--| VARIABLE u_val : std_ulogic ; +--| +--| u_val := From_String (" 100"); +--| This statement will set u_val equal to the value '1'. +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN std_ulogic IS + VARIABLE str_copy : STRING (1 TO str'LENGTH) := To_Upper(str); + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE result : std_ulogic; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_String --- input string has zero length " + severity ERROR; + RETURN 'U'; + END IF; + -- find the position of the first non-white character. + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_String --- input string is empty "; + RETURN 'U'; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_String -- first non_white character is a NUL "; + RETURN 'U'; + END IF; + ch := str_copy(index); + CASE ch IS + WHEN 'U' => result := 'U'; + WHEN 'X' => result := 'X'; + WHEN '0' => result := '0'; + WHEN '1' => result := '1'; + WHEN 'Z' => result := 'Z'; + WHEN 'W' => result := 'W'; + WHEN 'L' => result := 'L'; + WHEN 'H' => result := 'H'; + WHEN '-' => result := '-'; + WHEN OTHERS => + result := 'U'; + ASSERT FALSE + REPORT "From_String(str(" & To_String(index) & ") => " + & To_String(ch) & ") is an invalid character " + SEVERITY ERROR; + END CASE; + return result; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to an std_ulogic_vector. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : std_ulogic_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE u_vector : std_ulogic_vector( 7 DOWNTO 0) ; +--| +--| u_vector := From_String (" 0-ZU1010 1010"); +--| This statement will set u_vector equal to "0-ZU1010". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN std_ulogic_vector IS + VARIABLE str_copy : STRING ( 1 to str'LENGTH ) := To_Upper(str); + VARIABLE invalid : boolean := false; + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE i, idx : Integer; + VARIABLE r : std_ulogic_vector(1 TO str'length); + VARIABLE result : std_ulogic_vector(str'length-1 downto 0); + BEGIN + if (StrLen (str) = 0) THEN + assert false report " From String --- input string has zero length "; + return ""; + end if; + -- find the position of the first non-white character. + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_String --- input string is empty "; + RETURN ""; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_String -- first non_white character is a NUL "; + RETURN ""; + END IF; + i := 0; + FOR idx IN index TO str'length LOOP + i := i + 1; + ch := str_copy(idx); + CASE ch IS + WHEN 'U' => r(i) := 'U'; + WHEN 'X' => r(i) := 'X'; + WHEN '0' => r(i) := '0'; + WHEN '1' => r(i) := '1'; + WHEN 'Z' => r(i) := 'Z'; + WHEN 'W' => r(i) := 'W'; + WHEN 'L' => r(i) := 'L'; + WHEN 'H' => r(i) := 'H'; + WHEN '-' => r(i) := '-'; + WHEN NUL => i := i - 1; -- last index was the non-NUL + exit; + WHEN OTHERS => IF (NOT Is_White(ch)) THEN + -- a non binary value was passed + ASSERT (invalid) + REPORT "From_String(str(" & To_String(idx) & ") => " + & To_String(ch) & ") is an invalid character " + SEVERITY ERROR; + invalid := TRUE; + else + i := i - 1; -- last index was the non-white + EXIT; -- found a white space ! + END IF; + END CASE; + END LOOP; + if invalid THEN + for k in 1 to i loop + r(k) := 'U'; -- fill with 'U's + end loop; + end if; + result (i-1 downto 0) := r(1 to i); + return result(i-1 downto 0); + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to an std_logic_vector. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : std_logic_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE logic_vect : std_logic_vector( 7 DOWNTO 0) ; +--| +--| logic_vect := From_String (" 0-ZU1010 1010"); +--| This statement will set logic_vect equal to "0-ZU1010". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN std_logic_vector IS + VARIABLE str_copy : STRING ( 1 to str'LENGTH ) := To_Upper(str); + VARIABLE invalid : boolean := false; + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE i, idx : Integer; + VARIABLE r : std_logic_vector(1 TO str'length); + VARIABLE result : std_logic_vector(str'length-1 downto 0); + BEGIN + if (StrLen (str) = 0) THEN + assert false report " From String --- input string has zero length "; + return ""; + end if; + -- find the position of the first non-white character. + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_String --- input string is empty "; + RETURN ""; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_String -- first non_white character is a NUL "; + RETURN ""; + END IF; + + i := 0; + FOR idx IN index TO str'length LOOP + i := i + 1; + ch := str_copy(idx); + CASE ch IS + WHEN 'U' => r(i) := 'U'; + WHEN 'X' => r(i) := 'X'; + WHEN '0' => r(i) := '0'; + WHEN '1' => r(i) := '1'; + WHEN 'Z' => r(i) := 'Z'; + WHEN 'W' => r(i) := 'W'; + WHEN 'L' => r(i) := 'L'; + WHEN 'H' => r(i) := 'H'; + WHEN '-' => r(i) := '-'; + WHEN NUL => i := i - 1; -- last index was the non-NUL + exit; + WHEN OTHERS => IF (NOT Is_White(ch)) THEN + -- a non binary value was passed + ASSERT (invalid) + REPORT "From_String(str(" & To_String(idx) & ") => " + & To_String(ch) & ") is an invalid character" + SEVERITY ERROR; + invalid := TRUE; + ELSE + i := i - 1; -- last index was the non-white + EXIT; -- found a white space ! + END IF; + END CASE; + END LOOP; + if invalid THEN + for k in 1 to i loop + r(k) := 'U'; -- fill with 'U's + end loop; + end if; + result (i-1 downto 0) := r(1 to i); + return result(i-1 downto 0); + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_BinString +--| +--| Overloading : None +--| +--| Purpose : Convert from a Binary String to a bit_vector. +--| +--| Parameters : +--| str - input , binary string to be converted, +--| +--| Result : bit_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE b_vect : bit_vector( 7 DOWNTO 0) ; +--| +--| b_vect := From_BinString (" 01101111 1010"); +--| This statement will set b_vect equal to "01101111". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_BinString ( CONSTANT str : IN STRING + ) RETURN bit_vector IS + VARIABLE str_copy : STRING (1 TO str'LENGTH) := To_Upper(str); + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE i, idx : Integer; + VARIABLE invalid : boolean := false; + VARIABLE r : bit_vector(1 TO str'length); + VARIABLE result : bit_vector(str'length - 1 DOWNTO 0) ; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_BinString --- input string has a zero length "; + RETURN ""; + ELSIF (str(str'LEFT) = NUL) THEN + assert false + report " From_BinString --- input string has nul character " + &" at the LEFT position " + severity ERROR; + RETURN ""; + END IF; + -- find the position of the first non_white character + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_BinString --- input string is empty "; + RETURN ""; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_BinString -- first non_white character is a NUL "; + RETURN ""; + END IF; + + i := 0; + FOR idx IN index TO str'length LOOP + i := i + 1; + ch := str_copy(idx); + CASE ch IS + WHEN '0' => r(i) := '0'; + WHEN '1' => r(i) := '1'; + WHEN NUL => i := i - 1; -- last index was the non-NUL + exit; + WHEN OTHERS => IF (NOT IS_White(ch)) THEN + -- a non binary value was passed + ASSERT (invalid) + REPORT "From_BinString(str(" & To_String(idx) & ") => " + & To_String(ch) & ") is an invalid character" + SEVERITY ERROR; + invalid := TRUE; + else + i := i - 1; -- last index was the non-NUL + exit; + end if; + END CASE; + END LOOP; + -- check for invalid character in the string + if ( invalid ) THEN + r(1 TO i) := (OTHERS => '0'); + end if; + result(i-1 DOWNTO 0) := r(1 TO i); + return result(i - 1 DOWNTO 0); -- return slice of result + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_OctString +--| +--| Overloading : None +--| +--| Purpose : Convert from an Octal String to a bit_vector. +--| +--| Parameters : +--| str - input , Octal string to be converted, +--| +--| Result : bit_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE b_vect : bit_vector( 15 DOWNTO 4) ; +--| +--| b_vect := From_OctString (" 1735 1010"); +--| This statement will set b_vect equal to "001111011101". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_OctString ( CONSTANT str : IN STRING + ) RETURN bit_vector IS + CONSTANT len : Integer := 3 * str'LENGTH; + CONSTANT oct_dig_len : Integer := 3; + VARIABLE str_copy : STRING (1 TO str'LENGTH) := To_Upper(str); + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE i, idx : Integer; + VARIABLE invalid : boolean := false; + VARIABLE r : bit_vector( 1 TO len) ; + VARIABLE result : bit_vector(len - 1 DOWNTO 0) ; + CONSTANT bin_zero : bit_vector(1 to 3) := "000"; -- this done for Mentor unsupported feature + CONSTANT bin_one : bit_vector(1 to 3) := "001"; + CONSTANT bin_two : bit_vector(1 to 3) := "010"; + CONSTANT bin_three : bit_vector(1 to 3) := "011"; + CONSTANT bin_four : bit_vector(1 to 3) := "100"; + CONSTANT bin_five : bit_vector(1 to 3) := "101"; + CONSTANT bin_six : bit_vector(1 to 3) := "110"; + CONSTANT bin_seven : bit_vector(1 to 3) := "111"; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_OctString --- input string has zero length "; + RETURN ""; + ELSIF (str(str'LEFT) = NUL) THEN + assert false + report " From_OctString --- input string has nul character" + & " at the LEFT position " + severity ERROR; + RETURN ""; -- null bit_vector + END IF; + -- find the position of the first non_white character + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_OctString --- input string is empty "; + RETURN ""; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_OctString -- first non_white character is a NUL "; + RETURN ""; + END IF; + + i := 0; + FOR idx IN index TO str'length LOOP + ch := str_copy(idx); + EXIT WHEN ((Is_White(ch)) OR (ch = NUL)); + CASE ch IS + WHEN '0' => r(i+1 TO i+oct_dig_len) := bin_zero; + WHEN '1' => r(i+1 TO i+oct_dig_len) := bin_one; + WHEN '2' => r(i+1 TO i+oct_dig_len) := bin_two; + WHEN '3' => r(i+1 TO i+oct_dig_len) := bin_three; + WHEN '4' => r(i+1 TO i+oct_dig_len) := bin_four; + WHEN '5' => r(i+1 TO i+oct_dig_len) := bin_five; + WHEN '6' => r(i+1 TO i+oct_dig_len) := bin_six; + WHEN '7' => r(i+1 TO i+oct_dig_len) := bin_seven; + WHEN NUL => exit; + WHEN OTHERS => -- a non binary value was passed + ASSERT (invalid) + REPORT "From_OctString(str(" & To_String(idx) & ") => " + & To_String(ch) & ") is an invalid character" + SEVERITY ERROR; + invalid := TRUE; + END CASE; + i := i + oct_dig_len; + END LOOP; + -- check for invalid character in the string + if ( invalid ) THEN + r(1 TO i) := (OTHERS => '0'); + end if; + result(i - 1 DOWNTO 0) := r(1 TO i); + return result(i-1 DOWNTO 0); -- return slice of result + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : From_HexString +--| +--| Overloading : None +--| +--| Purpose : Convert from a Hex String to a bit_vector. +--| +--| Parameters : +--| str - input , Hex string to be converted, +--| +--| Result : bit_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE b_vect : bit_vector( 15 DOWNTO 4) ; +--| +--| b_vect := From_HexString (" 3DD 1010"); +--| This statement will set b_vect equal to "001111011101". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_HexString ( CONSTANT str : IN STRING + ) RETURN bit_vector IS + + CONSTANT len : Integer := 4 * str'LENGTH; + CONSTANT hex_dig_len : Integer := 4; + VARIABLE str_copy : STRING (1 TO str'LENGTH) := To_Upper(str); + VARIABLE index : Natural; + VARIABLE ch : character; + VARIABLE i, idx : Integer; + VARIABLE invalid : boolean := false; + VARIABLE r : bit_vector(1 TO len) ; + VARIABLE result : bit_vector(len - 1 DOWNTO 0); + CONSTANT bin_zero : bit_vector(1 to 4) := "0000"; -- this done for Mentor unsupported feature + CONSTANT bin_one : bit_vector(1 to 4) := "0001"; + CONSTANT bin_two : bit_vector(1 to 4) := "0010"; + CONSTANT bin_three : bit_vector(1 to 4) := "0011"; + CONSTANT bin_four : bit_vector(1 to 4) := "0100"; + CONSTANT bin_five : bit_vector(1 to 4) := "0101"; + CONSTANT bin_six : bit_vector(1 to 4) := "0110"; + CONSTANT bin_seven : bit_vector(1 to 4) := "0111"; + CONSTANT bin_eight : bit_vector(1 to 4) := "1000"; + CONSTANT bin_nine : bit_vector(1 to 4) := "1001"; + CONSTANT bin_ten : bit_vector(1 to 4) := "1010"; + CONSTANT bin_eleven : bit_vector(1 to 4) := "1011"; + CONSTANT bin_twelve : bit_vector(1 to 4) := "1100"; + CONSTANT bin_thirteen : bit_vector(1 to 4) := "1101"; + CONSTANT bin_fourteen : bit_vector(1 to 4) := "1110"; + CONSTANT bin_fifteen : bit_vector(1 to 4) := "1111"; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_HexString --- input string has zero length "; + RETURN ""; + + ELSIF (str(str'LEFT) = NUL) THEN + assert false + report " From_HexString --- input string has nul character" + & " at the LEFT position " + severity ERROR; + RETURN ""; -- null bit_vector + END IF; + -- find the position of the first non_white character + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_HexString --- input string is empty "; + RETURN ""; + ELSIF (str_copy(index)=NUL) THEN + assert false report " From_HexString -- first non_white character is a NUL "; + RETURN ""; + END IF; + + i := 0; + FOR idx IN index TO str'length LOOP + ch := str_copy(idx); + EXIT WHEN ((Is_White(ch)) OR (ch = NUL)); + CASE ch IS + WHEN '0' => r(i+1 TO i+ hex_dig_len) := bin_zero; + WHEN '1' => r(i+1 TO i+ hex_dig_len) := bin_one; + WHEN '2' => r(i+1 TO i+ hex_dig_len) := bin_two; + WHEN '3' => r(i+1 TO i+ hex_dig_len) := bin_three; + WHEN '4' => r(i+1 TO i+ hex_dig_len) := bin_four; + WHEN '5' => r(i+1 TO i+ hex_dig_len) := bin_five; + WHEN '6' => r(i+1 TO i+ hex_dig_len) := bin_six; + WHEN '7' => r(i+1 TO i+ hex_dig_len) := bin_seven; + WHEN '8' => r(i+1 TO i+ hex_dig_len) := bin_eight; + WHEN '9' => r(i+1 TO i+ hex_dig_len) := bin_nine; + WHEN 'A' | 'a' => r(i+1 TO i+ hex_dig_len) := bin_ten; + WHEN 'B' | 'b' => r(i+1 TO i+ hex_dig_len) := bin_eleven; + WHEN 'C' | 'c' => r(i+1 TO i+ hex_dig_len) := bin_twelve; + WHEN 'D' | 'd' => r(i+1 TO i+ hex_dig_len) := bin_thirteen; + WHEN 'E' | 'e' => r(i+1 TO i+ hex_dig_len) := bin_fourteen; + WHEN 'F' | 'f' => r(i+1 TO i+ hex_dig_len) := bin_fifteen; + WHEN NUL => exit; + WHEN OTHERS => -- a non binary value was passed + ASSERT (invalid) + REPORT "From_HexString(str(" & To_String(idx) & ") => " + & To_String(ch) & ") is an invalid character" + SEVERITY ERROR; + invalid := TRUE; + END CASE; + i := i + hex_dig_len; + END LOOP; + -- check for invalid character in the string + if ( invalid ) THEN + r(1 TO i) := (OTHERS => '0'); + end if; + result(i - 1 DOWNTO 0) := r(1 TO i); + return result(i - 1 DOWNTO 0); -- return slice of result + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.1 +--| Overloading : None +--| +--| Purpose : Convert a boolean to a String. +--| +--| Parameters : +--| val - input value, BOOLEAN, +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of a boolean. +--| +--| NOTE : +--| Default is right justified +--| +--| Use : +--| VARIABLE s_flag : String(1 TO 5); +--| VARIABLE good : BOOLEAN := TRUE; +--| +--| s_flag := To_String ( good, "%5s" ); +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN BOOLEAN; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE buf_str : STRING(1 TO 5) := (OTHERS => ' '); + VARIABLE str_len : INTEGER; + VARIABLE fw : INTEGER; + VARIABLE precis1 : INTEGER; + VARIABLE justfy : BIT; + CONSTANT FALSE_STR : STRING(1 to 5) := "FALSE"; -- for mentor unsupported feature + CONSTANT TRUE_STR : STRING(1 to 4) := "TRUE"; + + BEGIN + -- call procedure S_Machine to split the format string into + -- field width, precision, and justification(left or right). + -- procedure S_Machine will issue the proper error messages. + S_Machine(fw, precis1, justfy, fmt); + + CASE val IS + WHEN FALSE + => + str_len := 5; + buf_str(1 TO str_len) := FALSE_STR; + + IF ((precis1 = 0) OR (precis1 > str_len)) THEN + precis1 := str_len; + END IF; + + IF (fw = 0) THEN + fw := precis1; + END IF; + + IF (precis1 >= fw) THEN + return(buf_str(1 TO precis1)); + ELSE + result(precis1 + 1 TO fw) := (OTHERS => ' '); + + END IF; + WHEN TRUE + => + str_len := 4; + buf_str(1 TO str_len) := TRUE_STR; + + IF ((precis1 = 0) OR (precis1 > str_len)) THEN + precis1 := str_len; + END IF; + + IF (fw = 0) THEN + fw := precis1; + END IF; + + IF (precis1 >= fw) THEN + return(buf_str(1 TO precis1)); + ELSE + result(precis1 + 1 TO fw) := (OTHERS => ' '); + + END IF; + + END CASE; + + IF (justfy = '1') THEN -- left jsutify + return (buf_str(1 TO precis1) & result(precis1 + 1 TO fw)); + ELSE -- right justified + return( result(precis1 + 1 TO fw) & buf_str(1 TO precis1)); + END IF; + + -- That's all + + END; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.2 +--| Overloading : None +--| +--| Purpose : Convert a bit Value to a String. +--| +--| Parameters : +--| val - input bit. +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of a bit. +--| +--| +--| Use : +--| VARIABLE bit_string : String(1 TO 5); +--| +--| bit_string := To_String ( '1', "%1s"); +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN BIT; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + + BEGIN + -- + -- call procedure S_Machine to split the format string into + -- field width, precision, and justification(left or right). + -- + S_Machine(fw, precis, justfy, fmt); + + IF (fw < 1) THEN + fw := 1; + END IF; + -- fill result from 1 to fw with blanks + result(1 TO fw) := (OTHERS => ' '); + + CASE val IS + + WHEN '1' => + IF (justfy = '1') THEN -- left justify + result(1) := '1'; + ELSE -- right justify + result (fw) := '1'; + END if; + + WHEN '0' => IF (justfy = '1') THEN -- left justify + result(1) := '0'; + ELSE -- right justify + result (fw) := '0'; + END if; + END CASE; + RETURN result(1 TO fw); -- return a slice. + END; + +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.3 +--| Overloading : None +--| +--| Purpose : Convert a Character to a String. +--| +--| Parameters : +--| val - input character. +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Note : This function allows to see the non-printable characters. +--| FOR non_printable characters if precision is less than +--| 3 it will be automatically set to 3. +--| +--| Default precision will be set to eigther 3 or 1 +--| +--| Result : STRING representation of a character. +--| +--| +--| Use : +--| VARIABLE ascii_char : String(1 TO 5); +--| +--| ascii_char := To_String ( d, "%3s"); +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN CHARACTER; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + VARIABLE str2 : STRING(1 to 2); + VARIABLE str3 : STRING(1 to 3); + + + + BEGIN + -- + -- call procedure S_Machine to split the format string into + -- field width, precision, and justification(left or right). + -- + S_Machine(fw, precis, justfy, fmt); + + -- since purpose of this routine to see input characters even if + -- they are non_printable, precision 3 for non_printable and 1 for + -- graphic characters. + + IF ((val >= NUL AND val <= USP) AND (fw < 3)) THEN + fw := 3; + ELSIF ((val = DEL) AND (fw < 3)) THEN + fw := 3; + ELSIF (fw = 0) THEN + fw := 1; + END IF; + + FOR i IN 1 TO fw LOOP + result(i) := ' '; + END LOOP; + + CASE val is + WHEN NUL => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "NUL"; + ELSE -- right justify + str3 := "NUL"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN SOH => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "SOH"; + ELSE -- right justify + str3 := "SOH"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN STX => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "STX"; + ELSE -- right justify + str3 := "STX"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN ETX => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "ETX"; + ELSE -- right justify + str3 := "ETX"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN EOT => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "EOT"; + ELSE -- right justify + str3 := "EOT"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN ENQ => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "ENQ"; + ELSE -- right justify + str3 := "ENQ"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN ACK => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "ACK"; + ELSE -- right justify + str3 := "ACK"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN BEL => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "BEL"; + ELSE -- right justify + str3 := "BEL"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN BS => + IF (justfy = '1') THEN -- left justify + result(1 TO 2) := "BS"; + ELSE -- right justify + str2 := "BS"; -- fix for mentor unsupported feature + result (fw - 1 TO fw) := str2; + END if; + WHEN HT => + IF (justfy = '1') THEN -- left justify + result(1 TO 2) := "HT"; + ELSE -- right justify + str2 := "HT"; -- fix for mentor unsupported feature + result (fw - 1 TO fw) := str2; + END if; + WHEN LF => + IF (justfy = '1') THEN -- left justify + result(1 TO 2) := "LF"; + ELSE -- right justify + str2 := "LF"; -- fix for mentor unsupported feature + result (fw - 1 TO fw) := str2; + END if; + WHEN VT => + IF (justfy = '1') THEN -- left justify + result(1 TO 2) := "VT"; + ELSE -- right justify + str2 := "VT"; -- fix for mentor unsupported feature + result (fw - 1 TO fw) := str2; + END if; + WHEN FF => + IF (justfy = '1') THEN -- left justify + result(1 TO 2) := "FF"; + ELSE -- right justify + str2 := "FF"; -- fix for mentor unsupported feature + result (fw - 1 TO fw) := str2; + END if; + WHEN CR => + IF (justfy = '1') THEN -- left justify + result(1 TO 2) := "CR"; + ELSE -- right justify + str2 := "CR"; -- fix for mentor unsupported feature + result (fw - 1 TO fw) := str2; + END if; + WHEN SO => + IF (justfy = '1') THEN -- left justify + result(1 TO 2) := "SO"; + ELSE -- right justify + str2 := "SO"; -- fix for mentor unsupported feature + result (fw - 1 TO fw) := str2; + END if; + WHEN SI => + IF (justfy = '1') THEN -- left justify + result(1 TO 2) := "SI"; + ELSE -- right justify + str2 := "SI"; -- fix for mentor unsupported feature + result (fw - 1 TO fw) := str2; + END if; + WHEN DLE => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "DLE"; + ELSE -- right justify + str3 := "DLE"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN DC1 => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "DC1"; + ELSE -- right justify + str3 := "DC1"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN DC2 => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "DC2"; + ELSE -- right justify + str3 := "DC2"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN DC3 => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "DC3"; + ELSE -- right justify + str3 := "DC3"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN DC4 => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "DC4"; + ELSE -- right justify + str3 := "DC4"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN NAK => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "NAK"; + ELSE -- right justify + str3 := "NAK"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN SYN => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "SYN"; + ELSE -- right justify + str3 := "SYN"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN ETB => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "ETB"; + ELSE -- right justify + str3 := "ETB"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN CAN => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "CAN"; + ELSE -- right justify + str3 := "CAN"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN EM => + IF (justfy = '1') THEN -- left justify + result(1 TO 2) := "EM"; + ELSE -- right justify + str2 := "EM"; -- fix for mentor unsupported feature + result (fw - 1 TO fw) := str2; + END if; + WHEN SUB => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "SUB"; + ELSE -- right justify + str3 := "SUB"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN ESC => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "ESC"; + ELSE -- right justify + str3 := "ESC"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN FSP => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "FSP"; + ELSE -- right justify + str3 := "FSP"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN GSP => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "GSP"; + ELSE -- right justify + str3 := "GSP"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN RSP => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "RSP"; + ELSE -- right justify + str3 := "RSP"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN USP => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "USP"; + ELSE -- right justify + str3 := "USP"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN DEL => + IF (justfy = '1') THEN -- left justify + result(1 TO 3) := "DEL"; + ELSE -- right justify + str3 := "DEL"; -- fix for mentor unsupported feature + result (fw - 2 TO fw) := str3; + END if; + WHEN OTHERS => + IF (justfy = '1') THEN -- left justify + result(1) := val; + ELSE -- right justify + result (fw) := val; + END if; + END CASE; + RETURN result(1 TO fw); -- return a slice + END; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.4 +--| Overloading : None +--| +--| Purpose : Convert a severity-level to a string. +--| +--| Parameters : +--| val - input severity-level. +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of a severity-level. +--| +--| Use : +--| VARIABLE s_level : String(1 TO 7); +--| VARIABLE message : SEVERITY_LEVEL := NOTE; +--| +--| s_level := To_String (message, "%7s"); +--|------------------------------------------------------------------ + FUNCTION To_String ( CONSTANT val : IN SEVERITY_LEVEL; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE buf_str : STRING(1 TO 10); -- severity-level is maximum 7 characters + VARIABLE str_len : INTEGER; + VARIABLE fw : INTEGER; + VARIABLE precis2 : INTEGER; + VARIABLE justfy : BIT; + CONSTANT NOTE_STR : STRING(1 to 4) := "NOTE"; -- fix for mentor unsupported feature + CONSTANT WARNING_STR : STRING(1 to 7) := "WARNING"; + CONSTANT ERROR_STR : STRING(1 to 5) := "ERROR"; + CONSTANT FAILURE_STR : STRING(1 to 7) := "FAILURE"; + + BEGIN + -- call procedure S_Machine to split the format string into + -- field width, precision, and justification(left or right). + -- + S_Machine(fw, precis2, justfy, fmt); + + CASE val IS + WHEN NOTE + => + str_len := 4; + buf_str(1 TO str_len) := NOTE_STR; + + IF ((precis2 = 0) OR (precis2 > str_len)) THEN + precis2 := str_len; + END IF; + + IF (fw = 0) THEN + fw := precis2; + END IF; + + IF (precis2 >= fw) THEN + return(buf_str(1 TO precis2)); + ELSE + result(precis2 + 1 TO fw) := (OTHERS => ' '); + + END IF; + + WHEN WARNING => + str_len := 7; + buf_str(1 TO str_len) := WARNING_STR; + + IF ((precis2 = 0) OR (precis2 > str_len)) THEN + precis2 := str_len; + END IF; + + IF (fw = 0) THEN + fw := precis2; + END IF; + + IF (precis2 >= fw) THEN + return(buf_str(1 TO precis2)); + ELSE + result(precis2 + 1 TO fw) := (OTHERS => ' '); + END IF; + + WHEN ERROR => + str_len := 5; + buf_str(1 TO str_len) := ERROR_STR; + + IF ((precis2 = 0) OR (precis2 > str_len)) THEN + precis2 := str_len; + END IF; + + IF (fw = 0) THEN + fw := precis2; + END IF; + + IF (precis2 >= fw) THEN + return(buf_str(1 TO precis2)); + ELSE + result(precis2 + 1 TO fw) := (OTHERS => ' '); + END IF; + + WHEN FAILURE => + str_len := 7; + buf_str(1 TO str_len) := FAILURE_STR; + + IF ((precis2 = 0) OR (precis2 > str_len)) THEN + precis2 := str_len; + END IF; + + IF (fw = 0) THEN + fw := precis2; + END IF; + + IF (precis2 >= fw) THEN + return(buf_str(1 TO precis2)); + ELSE + result(precis2 + 1 TO fw) := (OTHERS => ' '); + END IF; + + END CASE; + IF (justfy = '1') THEN -- left jsutify + return ( buf_str(1 TO precis2) & result(precis2 + 1 TO fw)); + ELSE -- right justified + return (result(precis2 + 1 TO fw) & buf_str(1 TO precis2)); + END IF; + + -- That's all + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.5 +--| Overloading : None +--| +--| Purpose : Convert an integer into a String according +--| format specification. +--| +--| Parameters : +--| val - input value, INTEGER, +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of an integer. +--| +--| NOTE : Format string has same meaning a in C language. +--| That if format is "%d " will convert an integer to +--| a string of length equal to number of digits in the +--| given inetger argument. While "%10d " return +--| a string of length 10 and if the number of digits +--| in the integer are less than 10 it will pad the +--| string with blank on the left because default +--| justification is right. if number of digits are +--| larger than 10 it will return 10 leftmost digits. +--| +--| +--| +--| USE : +--| VARIABLE str : STRING(1 TO 10); +--| VARIABLE val : INTEGER := 2750; +--| +--| str := TO_String(val, "%10d"), +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN INTEGER; + CONSTANT format : IN STRING := "%d" + ) RETURN STRING IS + VARIABLE buf : string(max_string_len DOWNTO 1) ; -- implicitly == NUL + VARIABLE rbuf : string(max_string_len DOWNTO 1) ; + VARIABLE result : string(1 TO max_string_len) ; + VARIABLE str_index : integer := 0; + VARIABLE ival : integer; + VARIABLE format_cpy : STRING(1 TO format'LENGTH) := format; + VARIABLE indx : INTEGER; + VARIABLE fw : INTEGER; -- field width + VARIABLE precis : INTEGER; + VARIABLE justy : BIT := '0'; + + BEGIN + -- convert to positive number + ival := ABS(val); + IF ival = 0 then + str_index := str_index + 1; + buf(str_index) := '0'; + ELSE + int_loop : LOOP + str_index := str_index + 1; + CASE (ival MOD 10) IS + WHEN 0 => buf (str_index) := '0'; + WHEN 1 => buf (str_index) := '1'; + WHEN 2 => buf (str_index) := '2'; + WHEN 3 => buf (str_index) := '3'; + WHEN 4 => buf (str_index) := '4'; + WHEN 5 => buf (str_index) := '5'; + WHEN 6 => buf (str_index) := '6'; + WHEN 7 => buf (str_index) := '7'; + WHEN 8 => buf (str_index) := '8'; + WHEN 9 => buf (str_index) := '9'; + WHEN OTHERS => null; -- do nothing + END CASE; + ival := ival / 10; + EXIT int_loop WHEN ival=0; + END LOOP; + END IF; + + -- call procedure D_Machine to split the format string into + -- field width, and justification(left or right) and precision + D_Machine(fw, precis, justy, format_cpy); + + IF (precis > str_index) THEN -- pad with zeros to make up precision + buf(precis DOWNTO str_index + 1) := (OTHERS => '0'); + str_index := precis; + END IF; + + -- Handle the negative numbers here... + IF val < 0 then + str_index := str_index + 1; + buf (str_index) := '-'; + END IF; + + -- return the result according to field width and justification + IF (fw > str_index) THEN + case justy IS + WHEN '0' => + buf(fw DOWNTO str_index + 1) := (OTHERS => ' '); + return buf(fw DOWNTO 1); + WHEN '1' => + rbuf(fw - str_index DOWNTO 1) := (OTHERS => ' '); + result(1 TO str_index) := buf(str_index DOWNTO 1); + indx := str_index; + FOR i IN fw DOWNTO str_index+1 LOOP + indx := indx + 1; + result(indx) := ' '; + END LOOP; + return result(1 TO fw); + WHEN OTHERS => + ASSERT NOT WarningsOn + report " To_String --- error in justification " + SEVERITY WARNING; + return buf(str_index DOWNTO 1); + end case; + ELSE -- fw is lessthan or equal to std_index + return buf(str_index DOWNTO 1); + END IF; + + -- That's all + END; + +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.6 +--| Overloading : None +--| +--| Purpose : Convert a real number to a String. +--| +--| Parameters : +--| val - input value, REAL, +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of a real number. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 10); +--| VARIABLE val : REAL := 67.560 +--| +--| str := TO_String(val, "%10.3f"), +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN REAL; + CONSTANT format : IN STRING := "%f" + ) RETURN STRING IS + VARIABLE tbuf : string(max_string_len DOWNTO 1) ; -- implicitly == NUL + VARIABLE rbuf : string(max_string_len DOWNTO 1); + VARIABLE result : string(1 TO max_string_len); + VARIABLE str_index : Natural := 0; + VARIABLE rval : real; + VARIABLE int_val : INTEGER; + VARIABLE frac_digits : INTEGER; + VARIABLE fract_val : INTEGER; + VARIABLE format_cpy : string(1 TO format'length) := format; + VARIABLE fw_actual : integer; -- actual field width + VARIABLE indx : integer; + VARIABLE pr_actual : integer; -- actual precision + VARIABLE fw : integer; -- field width + VARIABLE precis : integer; -- precision + VARIABLE justy : BIT := '0'; -- justification + VARIABLE neg_sign : BOOLEAN := false ; + BEGIN + -- Handle the negative numbers here... + if val < 0.0 then + neg_sign := NOT neg_sign; + end if; + + rval := ABS (val); + int_val := i_TRUNC(rval); + i_Frac(rval, fract_val, frac_digits); + + -- call procedure F_Machine to split the format string into + -- field width, precision, and justification + + F_Machine(fw, precis, justy, format_cpy); + + -- convert fractional part to a string + IF fract_val = 0 then + str_index := str_index + 1; + tbuf(str_index) := '0'; + ELSE + fract_loop : LOOP + str_index := str_index + 1; + + CASE (fract_val MOD 10) IS + WHEN 0 => tbuf (str_index) := '0'; + WHEN 1 => tbuf (str_index) := '1'; + WHEN 2 => tbuf (str_index) := '2'; + WHEN 3 => tbuf (str_index) := '3'; + WHEN 4 => tbuf (str_index) := '4'; + WHEN 5 => tbuf (str_index) := '5'; + WHEN 6 => tbuf (str_index) := '6'; + WHEN 7 => tbuf (str_index) := '7'; + WHEN 8 => tbuf (str_index) := '8'; + WHEN 9 => tbuf (str_index) := '9'; + WHEN OTHERS => null; -- do nothing + END CASE; + fract_val := fract_val / 10; + EXIT fract_loop WHEN fract_val=0; + END LOOP; + END IF; + -- add leading zeros of fractional part + + FOR i IN 1 to 6 - frac_digits LOOP + str_index := str_index + 1; + tbuf(str_index) := '0'; + END LOOP; + + pr_actual := str_index; -- actual precision of give real number + + IF (precis > str_index) THEN + rbuf(precis - str_index DOWNTO 1) := (OTHERS => '0'); + rbuf(precis DOWNTO precis - str_index + 1) := tbuf(str_index DOWNTO 1); + ELSE + rbuf(precis DOWNTO 1) := tbuf(str_index DOWNTO str_index - precis + 1); + END IF; + + -- decimal point + str_index := precis + 1; + rbuf(str_index) := '.'; + + -- integer part of a real number + + IF int_val = 0 then + str_index := str_index + 1; + rbuf(str_index) := '0'; + ELSE + int_loop : LOOP + str_index := str_index + 1; + + CASE (int_val MOD 10) IS + WHEN 0 => rbuf (str_index) := '0'; + WHEN 1 => rbuf (str_index) := '1'; + WHEN 2 => rbuf (str_index) := '2'; + WHEN 3 => rbuf (str_index) := '3'; + WHEN 4 => rbuf (str_index) := '4'; + WHEN 5 => rbuf (str_index) := '5'; + WHEN 6 => rbuf (str_index) := '6'; + WHEN 7 => rbuf (str_index) := '7'; + WHEN 8 => rbuf (str_index) := '8'; + WHEN 9 => rbuf (str_index) := '9'; + WHEN OTHERS => null; -- do nothing + END CASE; + int_val := int_val / 10; + EXIT int_loop WHEN int_val=0; + END LOOP; + END IF; + -- negative sign + IF neg_sign THEN + str_index := str_index + 1; + rbuf(str_index) := '-'; + END IF; + fw_actual := str_index; -- actual field width of real + IF (fw <= fw_actual) THEN + return rbuf(fw_actual DOWNTO 1); + ELSIF (justy = '0') THEN -- right justify + For i In fw DOWNTO fw_actual + 1 LOOP + rbuf(i) := ' '; + END LOOP; + return rbuf(fw DOWNTO 1); + ELSIF (justy = '1' ) THEN -- left justify + result(1 TO fw_actual) := rbuf(fw_actual DOWNTO 1); + indx := fw_actual; + For i In fw - fw_actual DOWNTO 1 LOOP + indx := indx + 1; + result(indx) := ' '; + END LOOP; + return result(1 TO indx); + END IF; + -- That's all + END; +--+----------------------------------------------------------------------------- +--| Function Name : To_OctString +--| hidden +--| Overloading : None +--| +--| Purpose : Convert a bit_vector to a octal String. +--| +--| Parameters : +--| val - input, BIT_VECTOR, +--| +--| Result : STRING representation of a bit_vector. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 16); +--| VARIABLE vect : BIT_VECTOR (7 DOWNTO 0); +--| +--| str := TO_String(vect, "%16s"), +--| +--|----------------------------------------------------------------------------- + FUNCTION To_OctString ( CONSTANT val : IN BIT_VECTOR; + CONSTANT format : IN STRING := "%o" + ) RETURN STRING IS + CONSTANT reslen : INTEGER := val'LENGTH; + CONSTANT oct_bits : INTEGER := 3; + VARIABLE last_bits : INTEGER; + VARIABLE oct_len : NATURAL; + VARIABLE loc_result : STRING(1 TO reslen); + VARIABLE oct_result : STRING(1 TO reslen) := (OTHERS => ' '); +-- VARIABLE oct_str : STRING(1 TO oct_bits); -- Intermetrics can't handle this on the case statement below! + VARIABLE oct_str : STRING(1 TO 3 ); + VARIABLE bv : BIT_VECTOR(1 TO reslen) := val; + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + VARIABLE str_type : CHARACTER; + VARIABLE index : INTEGER; + + BEGIN + -- + -- convert Bit_Vector to string without taking care of format + + FOR i IN reslen DOWNTO 1 LOOP + IF ( bv(i) = '1') THEN + loc_result(i) := '1'; + ELSE -- bv(i) = '0' + loc_result(i) := '0'; + END IF; + END LOOP; + + -- call procedure SOX_Machine to split the format string into + -- field width, precision, and justification(left or right), and + -- string_type ( binary, octal or hex) + + SOX_Machine(fw, precis, justfy, str_type, fmt); + -- set the field width and precison propoerly + IF ((precis = 0) OR (precis > reslen)) THEN + precis := reslen; + END IF; + + last_bits := precis MOD oct_bits; + IF (last_bits = 0) THEN + oct_len := precis / oct_bits; + ELSE + oct_len := precis /oct_bits + 1; + END IF; + + index := precis; + FOR i IN oct_len DOWNTO 1 LOOP + IF ( i = 1) AND (last_bits /= 0) THEN + oct_str(1 TO oct_bits - last_bits) := (OTHERS => '0'); + oct_str(oct_bits - last_bits + 1 TO oct_bits) := loc_result(1 TO last_bits); + ELSE + oct_str := loc_result(index - 2 TO index); + END IF; + CASE oct_str IS + WHEN "000" => oct_result(i) := '0'; + WHEN "001" => oct_result(i) := '1'; + WHEN "010" => oct_result(i) := '2'; + WHEN "011" => oct_result(i) := '3'; + WHEN "100" => oct_result(i) := '4'; + WHEN "101" => oct_result(i) := '5'; + WHEN "110" => oct_result(i) := '6'; + WHEN "111" => oct_result(i) := '7'; + WHEN OTHERS => null; + END CASE; + index := index - oct_bits; + END LOOP; + + IF (fw < oct_len) THEN + fw := oct_len; + END IF; + + IF (oct_len >= fw) THEN + return(oct_result(1 TO oct_len)); + ELSE + result(oct_len+1 TO fw) := (OTHERS => ' '); + END IF; + + -- Now according to justification return the result; + IF (justfy = '1') THEN -- left justify + return (oct_result(1 TO oct_len) & result(oct_len+1 TO fw)); + ELSE -- right justify + return( result(oct_len + 1 TO fw) & oct_result(1 TO oct_len)); + END IF; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : To_HexString +--| hidden +--| Overloading : None +--| +--| Purpose : Convert a bit_vector to a octal String. +--| +--| Parameters : +--| val - input, BIT_VECTOR, +--| +--| Result : STRING representation of a bit_vector. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 16); +--| VARIABLE vect : BIT_VECTOR (7 DOWNTO 0); +--| +--| str := TO_String(vect, "%4x"), +--| +--|----------------------------------------------------------------------------- + FUNCTION To_HexString ( CONSTANT val : IN BIT_VECTOR; + CONSTANT format : IN STRING := "%x" + ) RETURN STRING IS + CONSTANT reslen : INTEGER := val'LENGTH; + CONSTANT hex_bits : INTEGER := 4; + VARIABLE last_bits : INTEGER; + VARIABLE hex_len : NATURAL; + VARIABLE loc_result : STRING(1 TO reslen); + VARIABLE hex_result : STRING(1 TO reslen) := (OTHERS => ' '); +-- VARIABLE hex_str : STRING(1 TO hex_bits); -- Intermetrics can't handle this on the case statement below! + VARIABLE hex_str : STRING(1 TO 4 ); + VARIABLE bv : BIT_VECTOR(1 TO reslen) := val; + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + VARIABLE str_type : CHARACTER; + VARIABLE index : INTEGER; + + BEGIN + -- + -- convert Bit_Vector to string without taking care of format + + FOR i IN reslen DOWNTO 1 LOOP + IF ( bv(i) = '1') THEN + loc_result(i) := '1'; + ELSE -- bv(i) = '0' + loc_result(i) := '0'; + END IF; + END LOOP; + + -- call procedure SOX_Machine to split the format string into + -- field width, precision, and justification(left or right), and + -- string_type ( binary, octal or hex) + + SOX_Machine(fw, precis, justfy, str_type, fmt); + -- set the field width and precison propoerly + IF ((precis = 0) OR (precis > reslen)) THEN + precis := reslen; + END IF; + + last_bits := precis MOD hex_bits; + IF (last_bits = 0) THEN + hex_len := precis / hex_bits; + ELSE + hex_len := precis /hex_bits + 1; + END IF; + + index := precis; + FOR i IN hex_len DOWNTO 1 LOOP + IF ( i = 1) AND (last_bits /= 0) THEN + hex_str(1 TO hex_bits - last_bits) := (OTHERS => '0'); + hex_str(hex_bits - last_bits + 1 TO hex_bits) := loc_result(1 TO last_bits); + ELSE + hex_str := loc_result(index - 3 TO index); + END IF; + CASE hex_str IS + WHEN "0000" => hex_result(i) := '0'; + WHEN "0001" => hex_result(i) := '1'; + WHEN "0010" => hex_result(i) := '2'; + WHEN "0011" => hex_result(i) := '3'; + WHEN "0100" => hex_result(i) := '4'; + WHEN "0101" => hex_result(i) := '5'; + WHEN "0110" => hex_result(i) := '6'; + WHEN "0111" => hex_result(i) := '7'; + WHEN "1000" => hex_result(i) := '8'; + WHEN "1001" => hex_result(i) := '9'; + WHEN "1010" => hex_result(i) := 'A'; + WHEN "1011" => hex_result(i) := 'B'; + WHEN "1100" => hex_result(i) := 'C'; + WHEN "1101" => hex_result(i) := 'D'; + WHEN "1110" => hex_result(i) := 'E'; + WHEN "1111" => hex_result(i) := 'F'; + WHEN OTHERS => null; + END CASE; + index := index - hex_bits; + END LOOP; + + IF (fw < hex_len) THEN + fw := hex_len; + END IF; + + IF (hex_len >= fw) THEN + return(hex_result(1 TO hex_len)); + ELSE + result(hex_len+1 TO fw) := (OTHERS => ' '); + END IF; + + -- Now according to justification return the result; + IF (justfy = '1') THEN -- left justify + return (hex_result(1 TO hex_len) & result(hex_len+1 TO fw)); + ELSE -- right justify + return( result(hex_len + 1 TO fw) & hex_result(1 TO hex_len)); + END IF; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.8 +--| Overloading : None +--| +--| Purpose : Convert a bit_vector to a String. +--| +--| Parameters : +--| val - input, BIT_VECTOR, +--| +--| Result : STRING representation of a bit_vector. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 16); +--| VARIABLE vect : BIT_VECTOR (7 DOWNTO 0); +--| +--| str := TO_String(vect, "%16s"), +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN BIT_VECTOR; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING IS + CONSTANT reslen : INTEGER := val'LENGTH; + VARIABLE loc_result : STRING(1 TO reslen); + VARIABLE bv : BIT_VECTOR(1 TO reslen) := val; + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + VARIABLE str_type : CHARACTER; + VARIABLE index : INTEGER; + + BEGIN + -- call procedure SOX_Machine to split the format string into + -- field width, precision, and justification(left or right), and + -- string_type ( binary, octal or hex) + SOX_Machine(fw, precis, justfy, str_type, fmt); + CASE str_type IS + WHEN 's' => + -- convert Bit_Vector to string without taking care of format + FOR i IN reslen DOWNTO 1 LOOP + IF ( bv(i) = '1') THEN + loc_result(i) := '1'; + ELSE -- bv(i) = '0' + loc_result(i) := '0'; + END IF; + END LOOP; + -- set the field width and precison propoerly + IF ((precis = 0) OR (precis > reslen)) THEN + precis := reslen; + END IF; + + IF (fw < val'LENGTH) THEN + fw := val'LENGTH; + END IF; + + IF (precis >= fw) THEN + return(loc_result(1 TO precis)); + ELSE + result(precis+1 TO fw) := (OTHERS => ' '); + END IF; + + -- Now according to justification return the result; + IF (justfy = '1') THEN -- left justify + return (loc_result(1 TO precis) & result(precis+1 TO fw)); + ELSE -- right justify + return( result(precis+1 TO fw) & loc_result(1 TO precis)); + END IF; + + WHEN 'o' | 'O' => return(To_OctString(val, format)); + + WHEN 'x' | 'X' => return(TO_HexString(val, format)); + + WHEN OTHERS => --ASSERT false + --report " To_String (bit_vector case)-- format error " + --SEVERITY ERROR; + return result; + END CASE; + END To_String; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.10.2 +--| Overloading : None +--| +--| Purpose : Convert an std_ulogic to a String. +--| +--| Parameters : +--| val - input std_ulogic. +--| +--| Result : STRING representation of std_ulogic. +--| +--| Use : +--| VARIABLE str_ovf : STRING(1 TO 4); +--| VARIABLE overflow : std_ulogic; +--| +--| str_ovf := TO_String(vect, "%4s"), +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN std_ulogic; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING IS + + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justify : BIT; + + BEGIN + -- call procedure S_Machine to split the format string into + -- field width, precision, and justification(left or right). + -- + S_Machine(fw, precis, justify, fmt); + + IF (fw < 1) THEN + fw := 1; + END IF; + -- fill result from 1 to fw with blanks + result(1 TO fw) := (OTHERS => ' '); + CASE val IS + WHEN 'U' => IF (justify = '1') THEN -- left justify + result(1) := 'U'; + ELSE -- right justify + result(fw) := 'U'; + END IF; + + WHEN 'X' => IF (justify = '1') THEN -- left justify + result(1) := 'X'; + ELSE -- right justify + result(fw) := 'X'; + END IF; + + WHEN '0' => IF (justify = '1') THEN -- left justify + result(1) := '0'; + ELSE -- right justify + result(fw) := '0'; + END IF; + + WHEN '1' => IF (justify = '1') THEN -- left justify + result(1) := '1'; + ELSE -- right justify + result(fw) := '1'; + END IF; + + WHEN 'Z' => IF (justify = '1') THEN -- left justify + result(1) := 'Z'; + ELSE -- right justify + result(fw) := 'Z'; + END IF; + + WHEN 'W' => IF (justify = '1') THEN -- left justify + result(1) := 'W'; + ELSE -- right justify + result(fw) := 'W'; + END IF; + + WHEN 'L' => IF (justify = '1') THEN -- left justify + result(1) := 'L'; + ELSE -- right justify + result(fw) := 'L'; + END IF; + + WHEN 'H' => IF (justify = '1') THEN -- left justify + result(1) := 'H'; + ELSE -- right justify + result(fw) := 'H'; + END IF; + + WHEN '-' => IF (justify = '1') THEN -- left justify + result(1) := '-'; + ELSE -- right justify + result(fw) := '-'; + END IF; + + WHEN OTHERS => -- An unknown std_ulogic value was passed + ASSERT FALSE + REPORT "To_String - Unknown std_ulogic value" + SEVERITY ERROR; + END CASE; + RETURN result(1 TO fw); + END To_String; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| +--| Overloading : None +--| +--| Purpose : Convert an std_logic_vector to a String. +--| +--| Parameters : +--| val - input std_logic_vector. +--| +--| Result : STRING representation of std_logic_vector. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 16); +--| VARIABLE vect : std_logic_vector (7 DOWNTO 0); +--| +--| str := TO_String(vect, "%16s"), +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN std_logic_vector; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING IS + CONSTANT reglen : INTEGER := val'LENGTH; + VARIABLE loc_result : STRING(1 TO reglen); + VARIABLE slv : std_logic_vector(1 TO reglen) := val; + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + + BEGIN + -- Convert to string without taking care of the format. + FOR i IN reglen DOWNTO 1 LOOP + CASE slv(i) IS + WHEN 'U' => loc_result(i) := 'U'; + WHEN 'X' => loc_result(i) := 'X'; + WHEN '0' => loc_result(i) := '0'; + WHEN '1' => loc_result(i) := '1'; + WHEN 'Z' => loc_result(i) := 'Z'; + WHEN 'W' => loc_result(i) := 'W'; + WHEN 'L' => loc_result(i) := 'L'; + WHEN 'H' => loc_result(i) := 'H'; + WHEN '-' => loc_result(i) := '-'; + WHEN OTHERS => -- An unknown std_logic value was passed + ASSERT FALSE + REPORT "To_String -- Unknown std_logic_vector value" + SEVERITY ERROR; + END CASE; + END LOOP; + -- call procedure S_Machine to split the format string into + -- field width, precision, and justification(left or right). + -- + S_Machine(fw, precis, justfy, fmt); + -- set the field width and precison propoerly + IF ((precis = 0) OR (precis > reglen)) THEN + precis := reglen; + END IF; + IF (fw < val'LENGTH) THEN + fw := val'LENGTH; + END IF; + IF (precis >= fw) THEN + return(loc_result(1 TO precis)); + ELSE + result(precis+1 TO fw) := (OTHERS => ' '); + END IF; + -- Now according to justification return the result; + IF (justfy = '1') THEN -- left justify + return (loc_result(1 TO precis) & result(precis+1 TO fw)); + ELSE -- right justify + return( result(precis+1 TO fw) & loc_result(1 TO precis)); + END IF; + END To_String; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| +--| Overloading : None +--| +--| Purpose : Convert an std_ulogic_vector to a String. +--| +--| Parameters : +--| val - input std_ulogic_vector. +--| +--| Result : STRING representation of std_ulogic_vector. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 16); +--| VARIABLE vect : std_ulogic_vector (7 DOWNTO 0); +--| +--| str := TO_String(vect, "%16s"), +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN std_ulogic_vector; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING IS + CONSTANT reglen : INTEGER := val'LENGTH; + VARIABLE loc_result : STRING(1 TO reglen); + VARIABLE slv : std_ulogic_vector(1 TO reglen) := val; + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE result : STRING(1 TO max_string_len); + VARIABLE fw : INTEGER; + VARIABLE precis : INTEGER; + VARIABLE justfy : BIT; + + BEGIN + -- Convert to string without taking care of the format. + FOR i IN reglen DOWNTO 1 LOOP + CASE slv(i) IS + WHEN 'U' => loc_result(i) := 'U'; + WHEN 'X' => loc_result(i) := 'X'; + WHEN '0' => loc_result(i) := '0'; + WHEN '1' => loc_result(i) := '1'; + WHEN 'Z' => loc_result(i) := 'Z'; + WHEN 'W' => loc_result(i) := 'W'; + WHEN 'L' => loc_result(i) := 'L'; + WHEN 'H' => loc_result(i) := 'H'; + WHEN '-' => loc_result(i) := '-'; + WHEN OTHERS => -- An unknown std_logic value was passed + ASSERT FALSE + REPORT "To_String -- Unknown std_logic_vector value" + SEVERITY ERROR; + END CASE; + END LOOP; + -- call procedure S_Machine to split the format string into + -- field width, precision, and justification(left or right). + -- + S_Machine(fw, precis, justfy, fmt); + -- set the field width and precison propoerly + IF ((precis = 0) OR (precis > reglen)) THEN + precis := reglen; + END IF; + IF (fw < val'LENGTH) THEN + fw := val'LENGTH; + END IF; + IF (precis >= fw) THEN + return(loc_result(1 TO precis)); + ELSE + result(precis+1 TO fw) := (OTHERS => ' '); + END IF; + -- Now according to justification return the result; + IF (justfy = '1') THEN -- left justify + return (loc_result(1 TO precis) & result(precis+1 TO fw)); + ELSE -- right justify + return( result(precis+1 TO fw) & loc_result(1 TO precis)); + END IF; + END To_String; +-- +-- character Handling Functions +-- +--+----------------------------------------------------------------------------- +--| Function Name : Is_Alpha +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is a letter of the alphabet. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is a letter of the +--| alphabet, false otherwise. +--| +--| +--| Use : VARIABLE ch : character; +--| +--| While (Is_Alpha(ch)) LOOP +--| -- do somthing +--| END LOOP; +--| +--| See Also : Is_Digit, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION Is_Alpha ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN IS + + VARIABLE result : BOOLEAN := false; + BEGIN + IF ( (c >= 'a' AND c <= 'z') OR ( c >= 'A' AND c <= 'Z')) THEN + result := TRUE; + ELSE + result := FALSE; + END IF; + RETURN result; + END Is_Alpha; +--+----------------------------------------------------------------------------- +--| Function Name : Is_Upper +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is an upper case letter. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is an upper case letter of +--| the alphabet, false otherwise. +--| +--| Use : VARIABLE ch : character; +--| +--| IF (IS_Upper(ch)) THEN +--| +--| -- do somthing +--| ELSE +--| -- do alternate action +--| END IF; +--| +--| See Also : Is_Digit, Is_Alpha, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION Is_Upper ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN IS + VARIABLE result : BOOLEAN := false; + BEGIN + IF ( c >= 'A' AND c <= 'Z') THEN + result := TRUE; + ELSE + result := FALSE; + END IF; + RETURN result; + END Is_Upper; +--+----------------------------------------------------------------------------- +--| Function Name : Is_Lower +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is a lower case letter. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is a lower case letter of +--| the alphabet, false otherwise. +--| +--| +--| See Also : Is_Digit, Is_Upper, Is_Alpha +--|----------------------------------------------------------------------------- + FUNCTION Is_Lower ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN IS + VARIABLE result : BOOLEAN := false; + BEGIN + IF ( c >= 'a' AND c <= 'z' ) THEN + result := TRUE; + ELSE + result := FALSE; + END IF; + RETURN result; + END Is_Lower; +--+----------------------------------------------------------------------------- +--| Function Name : Is_Digit +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is a digit 0-9. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is a digit, false +--| otherwise. +--| +--| +--| See Also : Is_Alpha, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION Is_Digit ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN IS + VARIABLE result : BOOLEAN; + BEGIN + IF (c >= '0' and c <= '9') THEN + result := TRUE; + ELSE + result := FALSE; + END IF; + RETURN result; + END Is_Digit; +--+----------------------------------------------------------------------------- +--| Function Name : Is_Space +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is a blank, tab or newline. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is a blank or tab(HT), +--| false otherwise. +--| +--| +--| See Also : Is_Digit, Is_Upper, Is_Lower, Is_Alpha +--|----------------------------------------------------------------------------- + FUNCTION Is_Space ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN IS + VARIABLE result : BOOLEAN; + BEGIN + IF (c = ' ' OR c = HT ) THEN + result := TRUE; + ELSE + result := FALSE; + END IF; + RETURN result; + END Is_Space; +--+----------------------------------------------------------------------------- +--| Function Name : To_Upper +--| 1. +--| Overloading : None +--| +--| Purpose :Convert a character to upper case. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : Character converted to upper case. +--| +--| +--| See Also : To_Lower, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION To_Upper ( CONSTANT c : IN CHARACTER + ) RETURN CHARACTER IS + VARIABLE result : CHARACTER := c; + BEGIN + IF ( c >= 'a' and c <= 'z') THEN + result := CHARACTER'VAL( CHARACTER'POS(c) + - CHARACTER'POS('a') + + CHARACTER'POS('A') ); + END IF; + RETURN result; + END To_Upper; +--+----------------------------------------------------------------------------- +--| Function Name : To_Upper +--| 1. +--| Overloading : None +--| +--| Purpose :Convert a string to upper case. +--| +--| Parameters : +--| val - input, string to be converted +--| +--| Result : string . +--| +--| +--| See Also : To_Lower, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION To_Upper ( CONSTANT val : IN String + ) RETURN STRING IS + VARIABLE result : string (1 TO val'LENGTH) := val; + VARIABLE ch : character; + BEGIN + FOR i IN 1 TO val'LENGTH LOOP + ch := result(i); + EXIT WHEN ((ch = NUL) OR (ch = nul)); + IF ( ch >= 'a' and ch <= 'z') THEN + result(i) := CHARACTER'VAL( CHARACTER'POS(ch) + - CHARACTER'POS('a') + + CHARACTER'POS('A') ); + END IF; + END LOOP; + RETURN result; + END To_Upper; +--+----------------------------------------------------------------------------- +--| Function Name : To_Lower +--| 1. +--| Overloading : None +--| +--| Purpose : Convert a Character to lower case. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : Character converted to lower case. +--| +--| See Also : To_Upper, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION To_Lower ( CONSTANT c : IN CHARACTER + ) RETURN CHARACTER IS + VARIABLE result : CHARACTER := c; + BEGIN + IF ( c >= 'A' and c <= 'Z') THEN + result := CHARACTER'VAL( CHARACTER'POS(c) + - CHARACTER'POS('A') + + CHARACTER'POS('a') ); + END IF; + RETURN result; + END To_Lower; +--+----------------------------------------------------------------------------- +--| Function Name : To_Lower +--| 1. +--| Overloading : None +--| +--| Purpose : Convert a String to lower case. +--| +--| Parameters : +--| val - input string to be converted. +--| +--| Result : string +--| +--| See Also : To_Upper, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION To_Lower ( CONSTANT val : IN STRING + ) RETURN STRING IS + VARIABLE result : string (1 TO val'LENGTH) := val; + VARIABLE ch : character; + BEGIN + FOR i IN 1 TO val'LENGTH LOOP + ch := result(i); + EXIT WHEN ((ch = NUL) OR (ch = nul)); + IF ( ch >= 'A' and ch <= 'Z') THEN + result(i) := CHARACTER'VAL( CHARACTER'POS(ch) + - CHARACTER'POS('A') + + CHARACTER'POS('a') ); + END IF; + END LOOP; + RETURN result; + END To_Lower; +--+----------------------------------------------------------------------------- +--| Function Name : StrCat +--| 1.2.1 +--| Overloading : None +--| +--| Purpose : Concatenate two string. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| +--| Result : Concatenated string. +--| +--|----------------------------------------------------------------------------- + FUNCTION StrCat ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING + ) RETURN STRING IS + CONSTANT len_l : INTEGER := StrLen(l_str); + CONSTANT len_r : INTEGER := StrLen(r_str); + CONSTANT len_result : INTEGER := len_l + len_r; + VARIABLE l : STRING ( 1 to l_str'length) := l_str; + VARIABLE r : STRING ( 1 to r_str'length) := r_str; + VARIABLE result : STRING (1 to len_result); + BEGIN + If (len_result /= 0) THEN + result (1 to len_l) := l ( 1 to len_l); + result (len_l+1 to len_result) := r ( 1 to len_r ); + RETURN result; + else + return ""; + end if; + + END StrCat; +--+----------------------------------------------------------------------------- +--| Function Name : StrNCat +--| 1.2.2 +--| Overloading : None +--| +--| Purpose : Concatenate upto n characters of r_string to l_string. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| +--| Result : Concatenated string. +--| +--|----------------------------------------------------------------------------- + FUNCTION StrNCat ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING; + CONSTANT n : INTEGER + ) RETURN STRING IS + CONSTANT len_l : INTEGER := StrLen(l_str); + CONSTANT len_result : INTEGER := len_l + n; + VARIABLE l : STRING ( 1 to l_str'length) := l_str; + VARIABLE r : STRING ( 1 to r_str'length) := r_str; + VARIABLE result : STRING (1 TO len_result); + + BEGIN + IF (len_result = 0) THEN + return ""; + END IF; + IF ((n <= 0) OR (r_str'LENGTH = 0)) THEN + result(1 TO len_l) := l(1 To len_l); + ELSE + result(1 TO len_l) := l(1 TO len_l); + FOR i IN 1 TO n LOOP + result(len_l + i) := r(i); + EXIT when ((r(i) = NUL) OR + (i >= r_str'LENGTH)); + END LOOP; + END IF; + RETURN result; + END StrNCat; +--+----------------------------------------------------------------------------- +--| Function Name : StrCpy +--| 1.2.3 +--| Overloading : None +--| +--| Purpose : Copy r_string to l_string. +--| +--| Parameters : +--| l_str - output, STRING, target string +--| r_str - input, STRING, source string +--| +--| Result : +--| +--| NOTE : If the length of target string is greater than +--| the source string, then target string is padded +--| with space characters on the right side and when +--| the length of target string is shorter than the +--| length of source string only left most characters +--| of the source string will be be copied to the target. +--| +--| +--| USE : +--| Variable s1: string(1 TO 8); +--| +--| StrCpy(s1, "123456789A"); +--| s1 will hold "12345678" +--|----------------------------------------------------------------------------- + PROCEDURE StrCpy ( VARIABLE l_str : OUT STRING; + CONSTANT r_str : IN STRING) IS + VARIABLE l_len : integer := l_str'LENGTH; + VARIABLE r_len : integer := r_str'LENGTH; + VARIABLE r : STRING ( 1 to r_len) := r_str; + VARIABLE result : STRING (1 to l_len); + VARIABLE indx : integer := 1; + BEGIN + +-- removed because it is not needed and because other routines call strcpy +-- and they should not generate a strcpy error +-- assert (l_len > 0) +-- report "StrCpy: target string is of zero length " +-- severity ERROR; + + while ( (indx <= r_len) and (indx <= l_len) and (r(indx) /= NUL) ) loop + result(indx) := r(indx); + indx := indx + 1; + end loop; + if (indx <= l_len) then + result(indx) := NUL; + end if; + l_str := result; + return; + END StrCpy; +--+----------------------------------------------------------------------------- +--| Function Name : StrNCpy +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : Copy at most n characters of r_string to l_string. +--| +--| Parameters : +--| l_str - output, STRING, target +--| r_str - input, STRING, source +--| n - input, Natural, number of characters to +--| to be copied. +--| +--| Result : l_string holds the result. +--| +--| NOTE : If n is less than or equal to zero then a srting +--| filled with blanks is returned. +--| +--| +--|----------------------------------------------------------------------------- + PROCEDURE StrNCpy ( VARIABLE l_str : OUT STRING; + CONSTANT r_str : IN STRING; + CONSTANT n : IN NATURAL + ) IS + VARIABLE l_len : integer := l_str'LENGTH; + VARIABLE r_len : integer := r_str'LENGTH; + VARIABLE r : STRING ( 1 to r_len) := r_str; + VARIABLE result : STRING (1 to l_len); + VARIABLE indx : integer := 1; + BEGIN + +-- removed - for reason see strcpy +-- assert (l_len > 0) +-- report "StrNCpy: target string is of zero length " +-- severity ERROR; + + while ( (indx <= r_len) and (indx <= l_len) and (r(indx) /= NUL) and (indx <= n) ) loop + result(indx) := r(indx); + indx := indx + 1; + end loop; + if (indx <= l_len) then + result(indx) := NUL; + end if; + l_str := result; + return; + END StrNCpy; +--+----------------------------------------------------------------------------- +--| Function Name : StrCmp +--| +--| Overloading : None +--| +--| Purpose : Compare left input string to right input string. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| +--| Result : INTEGER, returns an integer less than 0 if the left string +--| is less than the right string, returns integer 0 if the +--| the string are equal and returns an integer greater than +--| 0 if the left string is greater than the right string. +--| +--| +--|----------------------------------------------------------------------------- + FUNCTION StrCmp ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING + ) RETURN INTEGER IS + VARIABLE ls : STRING(1 TO l_str'LENGTH) := l_str; + VARIABLE rs : STRING(1 TO r_str'LENGTH) := r_str; + VARIABLE lv, rv : INTEGER; + VARIABLE i : INTEGER := 1; + BEGIN + WHILE ( (i <= ls'LENGTH) and (i <= rs'LENGTH) and (ls(i) /= NUL) and (rs(i) /= NUL) ) LOOP + if ( ls(i) /= rs(i) ) then + return (CHARACTER'POS(ls(i)) - CHARACTER'POS(rs(i))); + end if; + i := i + 1; + END LOOP; + + if ( i > ls'LENGTH) then + lv := 0; + else + lv := CHARACTER'POS(ls(i)); + end if; + + if ( i > rs'LENGTH) then + rv := 0; + else + rv := CHARACTER'POS(rs(i)); + end if; + + return (lv - rv); + END StrCmp; +--+----------------------------------------------------------------------------- +--| Function Name : StrNCmp +--| +--| Overloading : None +--| +--| Purpose : Compare at most n characters of left input string +--| to right input string. Returns an Integer. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| n - input, Natural, +--| +--| Result : Returns an integer less than 0 if left_most n +--| characters of the left string is less than the +--| right string, returns integer 0 if both strings +--| are equal, and returns an integer greater than 0 +--| if the left string is greater than the right string. +--| +--|----------------------------------------------------------------------------- + FUNCTION StrNCmp ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING; + CONSTANT n : IN Natural + ) RETURN INTEGER IS + VARIABLE ls : STRING(1 TO l_str'LENGTH) := l_str; + VARIABLE rs : STRING(1 TO r_str'LENGTH) := r_str; + VARIABLE i : INTEGER := 1; + VARIABLE lv, rv : INTEGER; + BEGIN + IF ( n <= 0) THEN + RETURN (0); + ELSE + WHILE ( (i <= ls'LENGTH) and (i <= rs'LENGTH) and (ls(i) /= NUL) and (rs(i) /= NUL) and (i <= n) ) LOOP + if ( ls(i) /= rs(i) ) then + return (CHARACTER'POS(ls(i)) - CHARACTER'POS(rs(i))); + end if; + i := i + 1; + END LOOP; + + if ( i > n ) then + return 0; + end if; + + if ( i > ls'LENGTH) then + lv := 0; + else + lv := CHARACTER'POS(ls(i)); + end if; + + if ( i > rs'LENGTH) then + rv := 0; + else + rv := CHARACTER'POS(rs(i)); + end if; + + return (lv - rv); + END IF; + END StrNCmp; +--+----------------------------------------------------------------------------- +--| Function Name : StrNcCmp +--| +--| Overloading : None +--| +--| Purpose : Compare to strings and determine whether left input +--| string is less than, equal to or greater than right +--| input string. The comparison is Not case sensitive. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| +--| Result : Returns an integer less than 0 if left_most n +--| characters of the left string is less than the +--| right string, returns integer 0 if both strings +--| are equal, and returns an integer greater than 0 +--| if the left string is greater than the right string. +--| +--|----------------------------------------------------------------------------- + FUNCTION StrNcCmp ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING + ) RETURN INTEGER IS + + VARIABLE ls : STRING(1 TO l_str'LENGTH); + VARIABLE rs : STRING(1 TO r_str'LENGTH); + VARIABLE lv, rv : INTEGER; + VARIABLE i : INTEGER := 1; + + BEGIN + -- convert both strings to upper case + ls := To_Upper(l_str); + rs := To_Upper(r_str); + + WHILE ( (i <= ls'LENGTH) and (i <= rs'LENGTH) and (ls(i) /= NUL) and (rs(i) /= NUL) ) LOOP + if ( ls(i) /= rs(i) ) then + return (CHARACTER'POS(ls(i)) - CHARACTER'POS(rs(i))); + end if; + i := i + 1; + END LOOP; + + if ( i > ls'LENGTH) then + lv := 0; + else + lv := CHARACTER'POS(ls(i)); + end if; + + if ( i > rs'LENGTH) then + rv := 0; + else + rv := CHARACTER'POS(rs(i)); + end if; + + return (lv - rv); + END StrNcCmp; +--+----------------------------------------------------------------------------- +--| Function Name : StrLen +--| +--| Overloading : None +--| +--| Purpose : Returns length of a string. +--| +--| Parameters : +--| l_str - input, STRING, +--| +--| Result : Natural +--| +--| NOTE : +--| This is in fact same as String'LENGTH provided +--| by VHDL. +--| +--| +--|----------------------------------------------------------------------------- + FUNCTION StrLen ( CONSTANT l_str : IN STRING + ) RETURN NATURAL IS + VARIABLE len : natural := 0; + BEGIN + length_check : for i in l_str'range loop + EXIT length_check WHEN l_str(i) = NUL; + len := len + 1; + end loop; + return len; + END StrLen; +-- +-- FILE I/O +-- + +--+----------------------------------------------------------------------------- +--| Function Name :Copyfile +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : Copy one ASCII_TEXT file to an other ASCII_TEXT file. +--| +--| Parameters : +--| in_fptr -- input, ASCII_TEXT, source file +--| out_fptr -- output, ASCII_TEXT, destination file +--| +--| NOTE : +--| +--| USE : +--| file romdata : ASCII_TEXT IS IN "NEW_ROM.dat"; +--| file dest_file : ASCII_TEXT IS OUT "SAVE_ROM.dat"; +--| +--| Copyfile(romdata, dest_file); +--|----------------------------------------------------------------------------- + PROCEDURE Copyfile ( VARIABLE in_fptr : IN ASCII_TEXT; + VARIABLE out_fptr : OUT ASCII_TEXT + ) IS + VARIABLE ch : character; + BEGIN + WHILE NOT ENDFILE(in_fptr) LOOP + READ(in_fptr, ch); + WRITE(out_fptr, ch); + END LOOP; + RETURN; + END Copyfile; + +--+----------------------------------------------------------------------------- +--| Function Name :Copyfile +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : Copy one TEXT file to an other TEXT file. +--| +--| Parameters : +--| in_fptr -- input, TEXT, +--| out_fptr -- output, TEXT +--| +--| NOTE : +--| This is combination of READLINE() and WRITELINE() +--| procedures provided in the standard +--| TEXTIO package. +--| +--| USE : +--| file in_f : TEXT IS IN "data_in"; +--| file out_f : TEXT IS OUT "save_data"; +--| +--| Copyfile(in_f, out_f); +--|----------------------------------------------------------------------------- + PROCEDURE Copyfile ( VARIABLE in_fptr : IN TEXT; + VARIABLE out_fptr : OUT TEXT + ) IS + VARIABLE ll : LINE; -- LINE is declared in TEXTIO + + BEGIN + WHILE NOT ENDFILE(in_fptr) LOOP + READLINE(in_fptr, ll); -- call procedure from TEXTIO + WRITELINE(out_fptr, ll); + END LOOP; + DEALLOCATE(ll); + RETURN; + END Copyfile; + +--+----------------------------------------------------------------------------- +--| Function Name : fprint +--| 1.2.1 +--| Overloading : None +--| +--| Purpose : Convert up to 10 arguments to a file according to +--| the format specifications give by a format string. +--| +--| Parameters : +--| file_ptr - output ASCII_TEXT, destination file +--| format - input STRING, format control specifications. +--| arg1 - input STRING, +--| arg2 - input STRING, +--| arg3 - input STRING, +--| arg4 - input STRING, +--| arg5 - input STRING, +--| arg6 - input STRING, +--| arg7 - input STRING, +--| arg8 - input STRING, +--| arg9 - input STRING, +--| arg10 - input STRING +--| +--| Result : formated TEXT. +--| +--| Note: This procedure provides formated output +--| of upto 10 arguments. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fprint ( VARIABLE file_ptr : OUT ASCII_TEXT; + CONSTANT format : IN STRING; + CONSTANT arg1 : IN STRING := ""; + CONSTANT arg2 : IN STRING := ""; + CONSTANT arg3 : IN STRING := ""; + CONSTANT arg4 : IN STRING := ""; + CONSTANT arg5 : IN STRING := ""; + CONSTANT arg6 : IN STRING := "" ; + CONSTANT arg7 : IN STRING := ""; + CONSTANT arg8 : IN STRING := ""; + CONSTANT arg9 : IN STRING := "" ; + CONSTANT arg10 : IN STRING := "" + ) IS + VARIABLE arg : STRING(1 TO max_string_len); + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE index : INTEGER := 0; + VARIABLE ch : CHARACTER; + VARIABLE lookahead : CHARACTER; + VARIABLE tokn : STRING(1 TO max_token_len); + VARIABLE ArgNum : INTEGER RANGE 1 TO 11; + BEGIN + -- + IF (format'LENGTH = 0) THEN + assert false + report " fprint --- format string is null " + severity ERROR; + return; + END IF; + + ArgNum := 1; + WHILE (true) LOOP + index := index + 1; + ch := fmt(index); + + IF (index < format'LENGTH) THEN + lookahead := fmt(index+1); + ELSE + lookahead := ' '; + END IF; + + IF (( ch = '%') AND (lookahead = '%')) THEN + index := index + 1; -- print % character + WRITE(file_ptr, ch); + + ELSIF ((ch = '\') AND (lookahead ='n')) THEN -- new line + index := index + 1; + ch := LF; + WRITE(file_ptr, ch); + + ELSIF (ch = '%') AND (lookahead /= '%') THEN + -- format %s expected + EXIT WHEN (ArgNum > 10); -- only first 10 argments will be printed + tokn := (OTHERS => ' '); -- fill token with blank space + get_token(fmt, index, tokn); + + -- select argument number 1 to 10 + Case ArgNum IS + WHEN 1 => + IF (arg1 /= "") THEN + print_str(file_ptr, tokn, arg1); + ELSE + EXIT; + END IF; + + WHEN 2 => + IF (arg2 /= "") THEN + print_str(file_ptr, tokn, arg2); + ELSE + EXIT; + END IF; + WHEN 3 => + IF (arg3 /= "") THEN + print_str(file_ptr, tokn, arg3); + ELSE + EXIT; + END IF; + WHEN 4 => + IF (arg4 /= "") THEN + print_str(file_ptr, tokn, arg4); + ELSE + EXIT; + END IF; + WHEN 5 => + IF (arg5 /= "") THEN + print_str(file_ptr, tokn, arg5); + ELSE + EXIT; + END IF; + WHEN 6 => + IF (arg6 /= "") THEN + print_str(file_ptr, tokn, arg6); + ELSE + EXIT; + END IF; + WHEN 7 => + IF (arg7 /= "") THEN + print_str(file_ptr, tokn, arg7); + ELSE + EXIT; + END IF; + WHEN 8 => + IF (arg8 /= "") THEN + print_str(file_ptr, tokn, arg8); + ELSE + EXIT; + END IF; + WHEN 9 => + IF (arg9 /= "") THEN + print_str(file_ptr, tokn, arg9); + ELSE + EXIT; + END IF; + WHEN 10 => + IF (arg10 /= "") THEN + print_str(file_ptr, tokn, arg10); + ELSE + EXIT; + END IF; + WHEN 11 => -- should not happen + Assert false + Report "fprint -- ASCII_TEXT, arguments > 10 " + SEVERITY ERROR; + END CASE; + ArgNum := ArgNum + 1; + + ELSIF (ch /= '%') THEN -- printable characters + WRITE(file_ptr, ch); + END IF; + EXIT WHEN (index = format'LENGTH); + END LOOP; -- end of while true loop + + -- That's it + END fprint; + +--+----------------------------------------------------------------------------- +--| Function Name : fprint +--| 1.2.1 +--| Overloading : None +--| +--| Purpose : Print up to 10 arguments to a file according to +--| the specifications given by a format string. +--| +--| Parameters : +--| file_ptr - output TEXT, destination file +--| line_ptr - INOUT LINE, pointer to a string. +--| format - input STRING, format control specifications. +--| arg1 - input STRING, +--| arg2 - input STRING, +--| arg3 - input STRING, +--| arg4 - input STRING, +--| arg5 - input STRING, +--| arg6 - input STRING, +--| arg7 - input STRING, +--| arg8 - input STRING, +--| arg9 - input STRING, +--| arg10 - input STRING +--| +--| Result : formated TEXT. +--| +--| Note: This procedure provides formated output +--| of upto 10 arguments. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fprint ( VARIABLE file_ptr : OUT TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + CONSTANT arg1 : IN STRING := ""; + CONSTANT arg2 : IN STRING := ""; + CONSTANT arg3 : IN STRING := ""; + CONSTANT arg4 : IN STRING := ""; + CONSTANT arg5 : IN STRING := ""; + CONSTANT arg6 : IN STRING := "" ; + CONSTANT arg7 : IN STRING := ""; + CONSTANT arg8 : IN STRING := ""; + CONSTANT arg9 : IN STRING := "" ; + CONSTANT arg10 : IN STRING := "" + ) IS + VARIABLE arg : STRING(1 TO max_string_len); + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE index : INTEGER := 0; + VARIABLE ch : CHARACTER; + VARIABLE lookahead : CHARACTER; + VARIABLE tokn : STRING(1 TO max_token_len); + VARIABLE ArgNum : INTEGER RANGE 1 TO 11; + + BEGIN + -- check for null format string + IF (format'LENGTH = 0) THEN + assert false + report " fprint --- format string is null " + severity ERROR; + return; + END IF; + -- initialize index to 0 and ArgNum to 1 + index := 0; + ArgNum := 1; + WHILE (true) LOOP + index := index + 1; + ch := fmt(index); + + IF (index < format'LENGTH) THEN + lookahead := fmt(index+1); + ELSE + lookahead := ' '; + END IF; + + IF (( ch = '%') AND (lookahead = '%')) THEN + index := index + 1; -- print % character + WRITE(line_ptr, ch); + + ELSIF ((ch = '\') AND (lookahead ='n')) THEN -- new line + index := index + 1; + WRITELINE(file_ptr, line_ptr); + DEALLOCATE(line_ptr); + ELSIF (ch = '%') AND (lookahead /= '%') THEN + -- format %s expected + EXIT WHEN (ArgNum > 10); -- only first 10 argments will be printed + tokn := (OTHERS => ' '); -- fill token with blank space + get_token(fmt, index, tokn); + + -- select argument number 1 to 10 + Case ArgNum IS + WHEN 1 => IF (arg1 /= "") THEN + print_str(line_ptr, tokn, arg1); + ELSE + EXIT; + END IF; + + WHEN 2 => IF (arg2 /= "") THEN + print_str(line_ptr, tokn, arg2); + ELSE + EXIT; + END IF; + WHEN 3 => IF (arg3 /= "") THEN + print_str(line_ptr, tokn, arg3); + ELSE + EXIT; + END IF; + + WHEN 4 => IF (arg4 /= "") THEN + print_str(line_ptr, tokn, arg4); + ELSE + EXIT; + END IF; + + WHEN 5 => IF (arg5 /= "") THEN + print_str(line_ptr, tokn, arg5); + ELSE + EXIT; + END IF; + + WHEN 6 => IF (arg6 /= "") THEN + print_str(line_ptr, tokn, arg6); + ELSE + EXIT; + END IF; + + WHEN 7 => IF (arg7 /= "") THEN + print_str(line_ptr, tokn, arg7); + ELSE + EXIT; + END IF; + + WHEN 8 => IF (arg8 /= "") THEN + print_str(line_ptr, tokn, arg8); + ELSE + EXIT; + END IF; + + WHEN 9 => IF (arg9 /= "") THEN + print_str(line_ptr, tokn, arg9); + ELSE + EXIT; + END IF; + + WHEN 10 => IF (arg10 /= "") THEN + print_str(line_ptr, tokn, arg10); + ELSE + EXIT; + END IF; + + WHEN 11 => -- should not happen + Assert false + Report "fprint -- TEXT, arguments > 10 " + SEVERITY ERROR; + END CASE; + -- increment the argument number + ArgNum := ArgNum + 1; + + ELSIF (ch /= '%') THEN -- printable characters + WRITE(line_ptr, ch); + END IF; + EXIT WHEN (index = format'LENGTH); + END LOOP; -- end of while true loop + -- That's it + END fprint; +--+----------------------------------------------------------------------------- +--| Function Name : fprint +--| 1.2.2 +--| Overloading : None +--| +--| Purpose : Print up to 10 arguments to a string buffer according to +--| the specifications given by a format string. +--| +--| Parameters : +--| string_buf - output STRING, +--| format - input STRING +--| arg1 - input STRING, +--| arg2 - input STRING, +--| arg3 - input STRING, +--| arg4 - input STRING, +--| arg5 - input STRING, +--| arg6 - input STRING, +--| arg7 - input STRING, +--| arg8 - input STRING, +--| arg9 - input STRING, +--| arg10 - input STRING +--| +--| Result : STRING representation of arguments. +--| +--| Note: This procedure provides formated output +--| of upto 10 arguments. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fprint ( VARIABLE string_buf : OUT STRING; + CONSTANT format : IN STRING; + CONSTANT arg1 : IN STRING := ""; + CONSTANT arg2 : IN STRING := ""; + CONSTANT arg3 : IN STRING := ""; + CONSTANT arg4 : IN STRING := ""; + CONSTANT arg5 : IN STRING := ""; + CONSTANT arg6 : IN STRING := ""; + CONSTANT arg7 : IN STRING := ""; + CONSTANT arg8 : IN STRING := ""; + CONSTANT arg9 : IN STRING := "" ; + CONSTANT arg10 : IN STRING := "" + ) IS + VARIABLE rbuf : STRING(1 TO string_buf'LENGTH); + VARIABLE arg : STRING(1 TO max_string_len); + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; + VARIABLE index : INTEGER := 0; + VARIABLE buf_indx : INTEGER := 0; + VARIABLE ch : CHARACTER; + VARIABLE lookahead : CHARACTER; + VARIABLE tokn : STRING(1 TO max_token_len); + VARIABLE ArgNum : INTEGER RANGE 1 TO 11; + + BEGIN + -- check for null format string + IF (format'LENGTH = 0) THEN + assert false + report " fprint --- format string is null " + severity ERROR; + return; + END IF; + + index := 0; + ArgNum := 1; + WHILE (true) LOOP + index := index + 1; + buf_indx := buf_indx + 1; + ch := fmt(index); + + IF (index < format'LENGTH) THEN + lookahead := fmt(index+1); + ELSE + lookahead := ' '; + END IF; + + IF (( ch = '%') AND (lookahead = '%')) THEN + rbuf(buf_indx) := ch; + index := index + 1; -- print % character + + ELSIF ((ch = '\') AND (lookahead ='n')) THEN -- new line + ch := LF; + rbuf(buf_indx) := ch; + index := index + 1; + + ELSIF (ch = '%') AND (lookahead /= '%') THEN + -- format %s expected + EXIT WHEN (ArgNum > 10); -- only first 10 argments will be printed + tokn := (OTHERS => ' '); -- fill token with blank space + get_token(fmt, index, tokn); + + -- select argument number 1 to 10 + + Case ArgNum IS + WHEN 1 => + IF (arg1 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg1); + ELSE + EXIT; + END IF; + + WHEN 2 => + IF (arg2 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg2); + ELSE + EXIT; + END IF; + WHEN 3 => + IF (arg3 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg3); + ELSE + EXIT; + END IF; + WHEN 4 => + IF (arg4 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg4); + ELSE + EXIT; + END IF; + WHEN 5 => + IF (arg5 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg5); + ELSE + EXIT; + END IF; + WHEN 6 => + IF (arg6 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg6); + ELSE + EXIT; + END IF; + WHEN 7 => + IF (arg7 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg7); + ELSE + EXIT; + END IF; + WHEN 8 => + IF (arg8 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg8); + ELSE + EXIT; + END IF; + WHEN 9 => + IF (arg9 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg9); + ELSE + EXIT; + END IF; + WHEN 10 => + IF (arg10 /= "") THEN + print_str_buf(rbuf, buf_indx, tokn, arg10); + ELSE + EXIT; + END IF; + + WHEN 11 => -- should not happen + Assert false + Report "fprint -- String buffer, arguments > 10 " + SEVERITY ERROR; + END CASE; + -- increment the argument number + ArgNum := ArgNum + 1; + + ELSIF (ch /= '%') THEN -- printable characters + rbuf(buf_indx) := ch; + END IF; + EXIT WHEN ((index >= format'LENGTH) OR ( buf_indx >= string_buf'LENGTH)) ; + END LOOP; -- end of while true loop + + IF (buf_indx > string_buf'LENGTH) THEN + string_buf := rbuf; + ELSIF (buf_indx = string_buf'LENGTH) THEN + string_buf := rbuf; +-- If (rbuf(buf_indx) = ' ') THEN +-- string_buf(buf_indx) := NUL; +-- end if; + ELSE + string_buf(1 TO buf_indx) := rbuf(1 To buf_indx); + string_buf(buf_indx + 1) := NUL; + END IF; + + return; + -- That's it + END fprint; + +--+----------------------------------------------------------------------------- +--| Function Name : ffgetc +--| +--| Overloading : Text, ASCII_TEXT +--| +--| Purpose : to read the next character from a file +--| +--| +--| Parameters : result - output character -- returned char +--| eof - output BOOLEAN -- TRUE if end of file reached +--| stream - in ASCII_TEXT -- file +--| +--| Notes : returns with eof true if end of file is reached +--| +--|----------------------------------------------------------------------------- + + PROCEDURE ffgetc ( VARIABLE result : OUT CHARACTER; + VARIABLE eof : OUT BOOLEAN; + VARIABLE stream : IN ASCII_TEXT + ) IS + + VARIABLE end_file : BOOLEAN; + + BEGIN + end_file := ENDFILE(stream); + if (not end_file) then + READ(stream, result); + end if; + eof := end_file; + return; + END; + + +--+----------------------------------------------------------------------------- +--| Procedure Name : scan_for_match +--|.hidden +--| Overloading : TEXT and ASCII_TEXT +--| +--| Purpose : To scan file skipping over blank spaces and newline +--| characters until a non-whitespace character is found. +--| If that character matches match_char then mismatch is +--| return false otherwise its TRUE. +--| +--| handles all three END_OF_LINE_MARKERS (LF, CR, and CR & LF) +--| +--| Parameters : fptr : IN ASCII_TEXT +--| match_char : IN CHARACTER +--| eof : INOUT BOOLEAN +--| mismatch : OUT BOOLEAN +--| +--|----------------------------------------------------------------------------- + + + procedure scan_for_match ( VARIABLE fptr : IN ASCII_TEXT; + CONSTANT match_char : IN CHARACTER; + VARIABLE eof : INOUT BOOLEAN; + VARIABLE mismatch : OUT BOOLEAN ) is + + VARIABLE ch : CHARACTER; + VARIABLE cont : BOOLEAN; + + begin + if ( END_OF_LINE_MARKER = (LF, ' ') ) then + mismatch := FALSE; + ffgetc (ch, eof, fptr); + while ( (is_space(ch) or ( (ch = LF) and (match_char /= LF) ) ) and (not eof) ) loop + ffgetc (ch, eof, fptr); + end loop; + if (not eof) then + mismatch := (ch /= match_char); + end if; + elsif ( END_OF_LINE_MARKER = (CR, ' ') ) then + mismatch := FALSE; + ffgetc (ch, eof, fptr); + while ( (is_space(ch) or ( (ch = CR) and (match_char /= CR) ) ) and (not eof) ) loop + ffgetc (ch, eof, fptr); + end loop; + if (not eof) then + mismatch := (ch /= match_char); + end if; + else -- END_OF_LINE_MARKER = CR & LF + mismatch := FALSE; + cont := TRUE; + ffgetc (ch, eof, fptr); + while ( cont ) loop + while ( (is_space(ch) or ( ( (ch = CR) or (ch = LF) ) and (match_char /= CR) ) ) and (not eof) ) loop + ffgetc (ch, eof, fptr); + end loop; + CONT := FALSE; + if ( (match_char = CR) and (ch = CR) ) then + ffgetc(ch, eof, fptr); + cont := (ch /= LF); + if (not cont) then + return; + end if; + end if; + end loop; + if (not eof) then + mismatch := (ch /= match_char); + end if; + end if; + return; + end; + + +--+----------------------------------------------------------------------------- +--| Procedure Name : get_fw +--|.hidden +--| Overloading : NONE +--| +--| Purpose : get the field width from the format string +--| assumes index is pointing at first digit +--| will end with index pointing a forth character +--| or first non-digit, which ever comes first +--| +--| Parameters : fmt : IN STRING +--| index : INOUT INTEGER +--| +--| +--|----------------------------------------------------------------------------- + + procedure get_fw ( VARIABLE fmt : IN STRING; + VARIABLE index : INOUT INTEGER; + VARIABLE field_width : INOUT INTEGER ) is + + variable count : integer := 3; + variable fw : integer := 0; + + begin + while ( (count > 0) and is_digit(fmt(index)) ) loop + fw := (fw * 10) + (CHARACTER'POS(fmt(index)) - 48); + index := index + 1; + count := count - 1; + end loop; + field_width := fw; + return; + end; + +--+----------------------------------------------------------------------------- +--| Function Name : fscan +--| 1.2.3 +--| Overloading : TEXT, ASCII_TEXT, string_buffer +--| +--| Purpose : To read text from a file according to specifications +--| given by the format string and save the results into +--| the corresponding arguments. +--| +--| Parameters : +--| file_ptr - input ASCII_TEXT, +--| format - input STRING, +--| arg1 - output STRING, +--| arg2 - output STRING, +--| arg3 - output STRING, +--| arg4 - output STRING, +--| arg5 - output STRING, +--| arg6 - output STRING, +--| arg7 - output STRING, +--| arg8 - output STRING, +--| arg9 - output STRING, +--| arg10 - output STRING +--| arg11 - output STRING, +--| arg12 - output STRING, +--| arg13 - output STRING, +--| arg14 - output STRING, +--| arg15 - output STRING, +--| arg16 - output STRING, +--| arg17 - output STRING, +--| arg18 - output STRING, +--| arg19 - output STRING, +--| arg20 - output STRING +--| arg_count - input integer, -- # of arguments in calling procedure +--| +--| Result : STRING representation given ASCII_TEXT. +--| +--| Note: This procedure extracts upto twenty arguments +--| from a line in a file. +--| If a %s(or whatever) is used without a digit then a space +--| must the string in the file inorder for the next argument to +--| be read in or for a match with the next literal to occur properly +--| +--| NOTE that when there is a %t if a time unit follows in the format string +--| it is skipped over (i.e. not treated as a matching string). +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING; + VARIABLE arg19 : OUT STRING; + VARIABLE arg20 : OUT STRING; + CONSTANT arg_count : IN INTEGER := 20 + ) IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; -- hold format + VARIABLE index : INTEGER := 1; -- index into fmt + VARIABLE fmt_len : INTEGER; -- length of format + VARIABLE ch : CHARACTER; -- present character read from file + VARIABLE fchar : CHARACTER; -- present format character + VARIABLE look_ahead : CHARACTER; -- next format character + VARIABLE mismatch : BOOLEAN := FALSE; -- TRUE if mismatch between format literal + -- and file character + VARIABLE eof : BOOLEAN := FALSE; -- TRUE if end of file + VARIABLE field_width : integer; -- field width + VARIABLE string_type : CHARACTER; -- type of string specified by format + VARIABLE arg_num : INTEGER := 0; -- number of argument currently being read + VARIABLE arg : string(1 to MAX_STRING_LEN+1); -- used to temporarily hold argument + VARIABLE premature_end : BOOLEAN := FALSE; -- true if end of file reached prematurely + VARIABLE t_follow : string(1 to 5); -- checks for time_unit following %t + VARIABLE ii, jj : INTEGER; + + BEGIN + -- make return strings empty + arg1(arg1'left) := NUL; + arg2(arg2'left) := NUL; + arg3(arg3'left) := NUL; + arg4(arg4'left) := NUL; + arg5(arg5'left) := NUL; + arg6(arg6'left) := NUL; + arg7(arg7'left) := NUL; + arg8(arg8'left) := NUL; + arg9(arg9'left) := NUL; + arg10(arg10'left) := NUL; + arg11(arg11'left) := NUL; + arg12(arg12'left) := NUL; + arg13(arg13'left) := NUL; + arg14(arg14'left) := NUL; + arg15(arg15'left) := NUL; + arg16(arg16'left) := NUL; + arg17(arg17'left) := NUL; + arg18(arg18'left) := NUL; + arg19(arg19'left) := NUL; + arg20(arg20'left) := NUL; + + index := Find_NonBlank(fmt, index); + fmt_len := StrLen(fmt); + if ( index > fmt_len ) then + assert FALSE + report "fscan (ASCII_TEXT) -- empty format string." + severity ERROR; + return; + end if; + + eof := ENDFILE(file_ptr); + + while ( (not eof) and (index <= fmt_len) ) loop + + fchar := fmt(index); + look_ahead := NUL; + mismatch := FALSE; + if (index < fmt_len) then + look_ahead := fmt(index+1); + else + look_ahead := ' '; + end if; + + + if ( (fchar = '\') and (look_ahead = 'n') ) then -- \n + if ( END_OF_LINE_MARKER = (LF, ' ') ) then + scan_for_match (file_ptr, LF, eof, mismatch); + else + scan_for_match (file_ptr, CR, eof, mismatch); + end if; + index := index + 2; + elsif ( (fchar = '%') and (look_ahead = '%') ) then -- check for literal % + scan_for_match (file_ptr, '%', eof, mismatch); + index := index + 2; + elsif (fchar = '%') then + if (arg_num = arg_count) then + assert FALSE + report "fscan (ASCII_TEXT) -- number of format specifications exceed argument count" + severity ERROR; + return; + end if; + arg_num := arg_num + 1; + field_width := 0; + index := index + 1; + if (is_digit(look_ahead)) then + get_fw (fmt, index, field_width); + end if; + if (index <= fmt_len) then + string_type := fmt(index); + index := index + 1; + else + assert FALSE + report "fscan (ASCII_TEXT) -- error in format specification" + severity ERROR; + return; + end if; + + case string_type is + when 'c' => if (field_width = 0) then + field_width := 1; + end if; + ii := 1; + while (field_width > 0) loop + ffgetc(ch, eof, file_ptr); + exit when ( eof ); + arg(ii) := ch; + ii := ii + 1; + field_width := field_width - 1; + end loop; + arg(ii) := NUL; + premature_end := ( eof and (ii = 1) ); + + when 'd' | 'f' | 's' | + 'o' | 'x' | 'X' | + 't' => -- skip over time unit if it follows %t + if ( string_type = 't') then + t_follow := (others => ' '); + ii := index; + jj := 2; + if ( (ii < fmt_len) and is_space(fmt(ii)) ) then + ii := ii + 1; + while ( (ii <= fmt_len) and (not is_space(fmt(ii))) and (jj <= 5) ) loop + t_follow(jj) := fmt(ii); + ii := ii + 1; + jj := jj + 1; + end loop; + if ( strcmp(t_follow, " fs ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " ps ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " ns ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " us ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " ms ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " sec ") = 0 ) then + index := index + 4; + elsif ( strcmp(t_follow, " min ") = 0 ) then + index := index + 4; + elsif ( strcmp(t_follow, " hr ") = 0 ) then + index := index + 3; + end if; + end if; + end if; + if ( field_width = 0 ) then + field_width := MAX_STRING_LEN + 1; + end if; + ffgetc (ch, eof, file_ptr); -- skip over carrage return and line feed and spaces + while ( (is_space(ch) or (ch = LF) or (ch = CR) ) and (not eof) ) loop + ffgetc(ch, eof, file_ptr); + end loop; + ii := 1; + loop + exit when ( eof or is_space(ch) or (ch = LF) or (ch = CR) ); + arg(ii) := ch; + ii := ii + 1; + field_width := field_width - 1; + exit when (field_width = 0); + ffgetc(ch, eof, file_ptr); + end loop; + if ( (string_type = 't') and (not eof) and (field_width > 1) and (ch /= LF) and (ch /= CR) ) then + arg(ii) := ' '; + ii := ii + 1; + field_width := field_width - 1; + ffgetc(ch, eof, file_ptr); + loop + exit when ( eof or is_space(ch) or (ch = LF) or (ch = CR) ); + arg(ii) := ch; + ii := ii + 1; + field_width := field_width - 1; + exit when (field_width = 0); + ffgetc(ch, eof, file_ptr); + end loop; + end if; + arg(ii) := NUL; + premature_end := ( eof and (ii = 1) ); + + when others => assert FALSE + report "fscan (ASCII_TEXT) -- error in format specification" + severity ERROR; + return; + end case; + case arg_num is + when 1 => strcpy(arg1, arg); + when 2 => strcpy(arg2, arg); + when 3 => strcpy(arg3, arg); + when 4 => strcpy(arg4, arg); + when 5 => strcpy(arg5, arg); + when 6 => strcpy(arg6, arg); + when 7 => strcpy(arg7, arg); + when 8 => strcpy(arg8, arg); + when 9 => strcpy(arg9, arg); + when 10 => strcpy(arg10, arg); + when 11 => strcpy(arg11, arg); + when 12 => strcpy(arg12, arg); + when 13 => strcpy(arg13, arg); + when 14 => strcpy(arg14, arg); + when 15 => strcpy(arg15, arg); + when 16 => strcpy(arg16, arg); + when 17 => strcpy(arg17, arg); + when 18 => strcpy(arg18, arg); + when 19 => strcpy(arg19, arg); + when 20 => strcpy(arg20, arg); + when others => assert FALSE + report "fscan (ASCII_TEXT) -- internal error" + severity ERROR; + return; + end case; + else -- compare for literal + scan_for_match (file_ptr, fchar, eof, mismatch); + index := index + 1; + end if; + + if (mismatch) then + assert NOT WarningsOn + report "fscan (ASCII_TEXT) -- format string literal mismatch" + severity WARNING; + return; + end if; + + index := Find_NonBlank(fmt, index); + end loop; + + index := Find_NonBlank(fmt, index); + assert ( not (WarningsOn and ( (eof and (index <= fmt_len)) or premature_end) ) ) + report "fscan (ASCII TEXT) -- unexpected end of file" + severity WARNING; + + + END fscan; + + +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING ; + VARIABLE arg17 : OUT STRING ; + VARIABLE arg18 : OUT STRING ; + VARIABLE arg19 : OUT STRING + ) IS + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16, + arg17, arg18, arg19, dummy_arg20, 19); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING ; + VARIABLE arg17 : OUT STRING ; + VARIABLE arg18 : OUT STRING + ) IS + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16, + arg17, arg18, dummy_arg19, dummy_arg20, 18); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING ; + VARIABLE arg17 : OUT STRING + ) IS + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16, + arg17, dummy_arg18, dummy_arg19, dummy_arg20, 17); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING + ) IS + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, arg16, + dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 16); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING + ) IS + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, arg11, arg12, arg13, arg14, arg15, + dummy_arg16, dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 15); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING + ) IS + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, arg11, arg12, arg13, arg14, dummy_arg15, + dummy_arg16, dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 14); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING + ) IS + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, arg11, arg12, arg13, + dummy_arg14, dummy_arg15, dummy_arg16, + dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 13); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING + ) IS + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, arg11, arg12, + dummy_arg13, dummy_arg14, dummy_arg15, dummy_arg16, + dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 12); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING + ) IS + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, arg11, dummy_arg12, + dummy_arg13, dummy_arg14, dummy_arg15, dummy_arg16, + dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 11); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING + + ) IS + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, arg10, dummy_arg11, dummy_arg12, + dummy_arg13, dummy_arg14, dummy_arg15, dummy_arg16, + dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 10); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING + ) IS + VARIABLE dummy_arg10 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, arg9, dummy_arg10, dummy_arg11, dummy_arg12, + dummy_arg13, dummy_arg14, dummy_arg15, dummy_arg16, + dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 9); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING + ) IS + VARIABLE dummy_arg9 : STRING(1 TO 10); + VARIABLE dummy_arg10 : STRING(1 TO 10); + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + arg8, dummy_arg9, dummy_arg10, dummy_arg11, dummy_arg12, + dummy_arg13, dummy_arg14, dummy_arg15, dummy_arg16, + dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 8); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING + ) IS + VARIABLE dummy_arg8 : STRING(1 TO 10); + VARIABLE dummy_arg9 : STRING(1 TO 10); + VARIABLE dummy_arg10 : STRING(1 TO 10); + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, arg7, + dummy_arg8, dummy_arg9, dummy_arg10, dummy_arg11, dummy_arg12, + dummy_arg13, dummy_arg14, dummy_arg15, dummy_arg16, + dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 7); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING + ) IS + VARIABLE dummy_arg7 : STRING(1 TO 10); + VARIABLE dummy_arg8 : STRING(1 TO 10); + VARIABLE dummy_arg9 : STRING(1 TO 10); + VARIABLE dummy_arg10 : STRING(1 TO 10); + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, arg6, + dummy_arg7, dummy_arg8, dummy_arg9, dummy_arg10, + dummy_arg11, dummy_arg12, dummy_arg13, dummy_arg14, dummy_arg15, + dummy_arg16, dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 6); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING + ) IS + VARIABLE dummy_arg6 : STRING(1 TO 10); + VARIABLE dummy_arg7 : STRING(1 TO 10); + VARIABLE dummy_arg8 : STRING(1 TO 10); + VARIABLE dummy_arg9 : STRING(1 TO 10); + VARIABLE dummy_arg10 : STRING(1 TO 10); + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, arg5, + dummy_arg6, dummy_arg7, dummy_arg8, dummy_arg9, dummy_arg10, + dummy_arg11, dummy_arg12, dummy_arg13, dummy_arg14, dummy_arg15, + dummy_arg16, dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 5); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING + ) IS + VARIABLE dummy_arg5 : STRING(1 TO 10); + VARIABLE dummy_arg6 : STRING(1 TO 10); + VARIABLE dummy_arg7 : STRING(1 TO 10); + VARIABLE dummy_arg8 : STRING(1 TO 10); + VARIABLE dummy_arg9 : STRING(1 TO 10); + VARIABLE dummy_arg10 : STRING(1 TO 10); + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, arg4, dummy_arg5, + dummy_arg6, dummy_arg7, dummy_arg8, dummy_arg9, dummy_arg10, + dummy_arg11, dummy_arg12, dummy_arg13, dummy_arg14, dummy_arg15, + dummy_arg16, dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 4); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING + ) IS + VARIABLE dummy_arg4 : STRING(1 TO 10); + VARIABLE dummy_arg5 : STRING(1 TO 10); + VARIABLE dummy_arg6 : STRING(1 TO 10); + VARIABLE dummy_arg7 : STRING(1 TO 10); + VARIABLE dummy_arg8 : STRING(1 TO 10); + VARIABLE dummy_arg9 : STRING(1 TO 10); + VARIABLE dummy_arg10 : STRING(1 TO 10); + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, arg3, dummy_arg4, dummy_arg5, + dummy_arg6, dummy_arg7, dummy_arg8, dummy_arg9, dummy_arg10, + dummy_arg11, dummy_arg12, dummy_arg13, dummy_arg14, dummy_arg15, + dummy_arg16, dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 3); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING + ) IS + VARIABLE dummy_arg3 : STRING(1 TO 10); + VARIABLE dummy_arg4 : STRING(1 TO 10); + VARIABLE dummy_arg5 : STRING(1 TO 10); + VARIABLE dummy_arg6 : STRING(1 TO 10); + VARIABLE dummy_arg7 : STRING(1 TO 10); + VARIABLE dummy_arg8 : STRING(1 TO 10); + VARIABLE dummy_arg9 : STRING(1 TO 10); + VARIABLE dummy_arg10 : STRING(1 TO 10); + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, arg2, dummy_arg3, dummy_arg4, + dummy_arg5,dummy_arg6,dummy_arg7,dummy_arg8,dummy_arg9,dummy_arg10, + dummy_arg11, dummy_arg12, dummy_arg13, dummy_arg14, dummy_arg15, + dummy_arg16, dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 2); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING + ) IS + VARIABLE dummy_arg2 : STRING(1 TO 10); + VARIABLE dummy_arg3 : STRING(1 TO 10); + VARIABLE dummy_arg4 : STRING(1 TO 10); + VARIABLE dummy_arg5 : STRING(1 TO 10); + VARIABLE dummy_arg6 : STRING(1 TO 10); + VARIABLE dummy_arg7 : STRING(1 TO 10); + VARIABLE dummy_arg8 : STRING(1 TO 10); + VARIABLE dummy_arg9 : STRING(1 TO 10); + VARIABLE dummy_arg10 : STRING(1 TO 10); + VARIABLE dummy_arg11 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg12 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg13 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg14 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg15 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg16 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg17 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg18 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg19 : STRING(1 TO 10); -- dummy string; + VARIABLE dummy_arg20 : STRING(1 TO 10); -- dummy string; + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, format, arg1, dummy_arg2, dummy_arg3, dummy_arg4, + dummy_arg5,dummy_arg6,dummy_arg7,dummy_arg8,dummy_arg9,dummy_arg10, + dummy_arg11, dummy_arg12, dummy_arg13, dummy_arg14, dummy_arg15, + dummy_arg16, dummy_arg17, dummy_arg18, dummy_arg19, dummy_arg20, 1); + return; + END; + + +--+----------------------------------------------------------------------------- +--| Function Name : ffgetc +--| +--| Overloading : Text, ASCII_TEXT, string_buf +--| +--| Purpose : to read the next character from a file +--| +--| +--| Parameters : result - output character -- returned char +--| eof - output BOOLEAN -- TRUE if end of file reached +--| stream - in TEXT -- file +--| ptr - inout line -- line buffer +--| +--| +--| Result : next character from the specified file. +--| returns LF if the end of the line is reached. +--| return with eof true if end of file is reached +--| +--|----------------------------------------------------------------------------- + + PROCEDURE ffgetc ( VARIABLE result : OUT CHARACTER; + VARIABLE eof : OUT BOOLEAN; + VARIABLE stream : IN TEXT; + VARIABLE ptr : INOUT LINE + ) IS + + BEGIN + eof := FALSE; + if ( ptr = NULL) then + if ( not ENDFILE(stream) ) then + READLINE(stream, ptr); + read(ptr, result); + else + result := NUL; + eof := TRUE; + end if; + elsif ( ptr.all'LENGTH = 0 ) then -- vantage ENDLINE function does not compile + if ( not ENDFILE(stream) ) then + READLINE(stream, ptr); + result := LF; + else + result := NUL; + eof := TRUE; + end if; + else + read(ptr, result); + end if; + return; + END; + + +--+----------------------------------------------------------------------------- +--| Procedure Name : scan_for_match +--|.hidden +--| Overloading : TEXT and ASCII_TEXT and string_buf +--| +--| Purpose : To scan file skipping over blank spaces and newline +--| characters until a non-whitespace character is found. +--| If that character matches match_char then mismatch is +--| return false otherwise its TRUE. +--| +--| Parameters : fptr : IN TEXT +--| lptr : INOUT LINE +--| match_char : IN CHARACTER +--| eof : INOUT BOOLEAN +--| mismatch : OUT BOOLEAN +--| +--|----------------------------------------------------------------------------- + + + procedure scan_for_match ( VARIABLE fptr : IN TEXT; + VARIABLE lptr : INOUT LINE; + CONSTANT match_char : IN CHARACTER; + VARIABLE eof : INOUT BOOLEAN; + VARIABLE mismatch : OUT BOOLEAN ) is + + VARIABLE ch : CHARACTER; + + begin + mismatch := FALSE; + ffgetc (ch, eof, fptr, lptr); + while ( (is_space(ch) or ( (ch = LF) and (match_char /= LF) ) ) and (not eof) ) loop + ffgetc (ch, eof, fptr, lptr); + end loop; + if (not eof) then + mismatch := (ch /= match_char); + end if; + return; + end; + + +--+----------------------------------------------------------------------------- +--| Function Name : fscan +--| 1.2.3 +--| Overloading : None +--| +--| Purpose : To read text from a file according to specifications +--| given by the format string and save the results into +--| the corresponding arguments. +--| +--| Parameters : +--| file_ptr - input TEXT, +--| line_ptr - input_output LINE, +--| format - input STRING, +--| arg1 - output STRING, +--| arg2 - output STRING, +--| arg3 - output STRING, +--| arg4 - output STRING, +--| arg5 - output STRING, +--| arg6 - output STRING, +--| arg7 - output STRING, +--| arg8 - output STRING, +--| arg9 - output STRING, +--| arg10 - output STRING +--| arg11 - output STRING, +--| arg12 - output STRING, +--| arg13 - output STRING, +--| arg14 - output STRING, +--| arg15 - output STRING, +--| arg16 - output STRING, +--| arg17 - output STRING, +--| arg18 - output STRING, +--| arg19 - output STRING, +--| arg20 - output STRING +--| arg_count - input integer, -- # of arguments in calling procedure +--| +--| Result : STRING representation given TEXT. +--| +--| Note: This procedure extracts upto twenty arguments +--| from a line in a file. +--| If a %s(or whatever) is used without a digit then a space +--| must the string in the file inorder for the next argument to +--| be read in or for a match with the next literal to occur properly +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING; + VARIABLE arg19 : OUT STRING; + VARIABLE arg20 : OUT STRING; + CONSTANT arg_count : IN INTEGER := 20 + ) IS + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; -- hold format + VARIABLE index : INTEGER := 1; -- index into fmt + VARIABLE fmt_len : INTEGER; -- length of format + VARIABLE ch : CHARACTER; -- present character read from file + VARIABLE fchar : CHARACTER; -- present format character + VARIABLE look_ahead : CHARACTER; -- next format character + VARIABLE mismatch : BOOLEAN := FALSE; -- TRUE if mismatch between format literal + -- and file character + VARIABLE eof : BOOLEAN := FALSE; -- TRUE if end of file + VARIABLE field_width : integer; -- field width + VARIABLE string_type : CHARACTER; -- type of string specified by format + VARIABLE arg_num : INTEGER := 0; -- number of argument currently being read + VARIABLE arg : string(1 to MAX_STRING_LEN+1); -- used to temporarily hold argument + VARIABLE premature_end : BOOLEAN := FALSE; -- true if end of file reached prematurely + VARIABLE t_follow : string(1 to 5); -- used to check for time unit following %t + VARIABLE ii, jj : INTEGER; + + BEGIN + -- make return strings empty + arg1(arg1'left) := NUL; + arg2(arg2'left) := NUL; + arg3(arg3'left) := NUL; + arg4(arg4'left) := NUL; + arg5(arg5'left) := NUL; + arg6(arg6'left) := NUL; + arg7(arg7'left) := NUL; + arg8(arg8'left) := NUL; + arg9(arg9'left) := NUL; + arg10(arg10'left) := NUL; + arg11(arg11'left) := NUL; + arg12(arg12'left) := NUL; + arg13(arg13'left) := NUL; + arg14(arg14'left) := NUL; + arg15(arg15'left) := NUL; + arg16(arg16'left) := NUL; + arg17(arg17'left) := NUL; + arg18(arg18'left) := NUL; + arg19(arg19'left) := NUL; + arg20(arg20'left) := NUL; + + index := Find_NonBlank(fmt, index); + fmt_len := StrLen(fmt); + if ( index > fmt_len ) then + assert FALSE + report "fscan (TEXT) -- empty format string." + severity ERROR; + return; + end if; + + eof := ENDFILE(file_ptr) and ( (line_ptr = NULL) or (line_ptr.all'LENGTH = 0) ); -- vantage ENDLINE function does not compile + + while ( (not eof) and (index <= fmt_len) ) loop + + fchar := fmt(index); + look_ahead := NUL; + mismatch := FALSE; + if (index < fmt_len) then + look_ahead := fmt(index+1); + else + look_ahead := ' '; + end if; + + + if ( (fchar = '\') and (look_ahead = 'n') ) then -- \n + scan_for_match (file_ptr, line_ptr, LF, eof, mismatch); + index := index + 2; + elsif ( (fchar = '%') and (look_ahead = '%') ) then -- check for literal % + scan_for_match (file_ptr, line_ptr, '%', eof, mismatch); + index := index + 2; + elsif (fchar = '%') then + if (arg_num = arg_count) then + assert FALSE + report "fscan (TEXT) -- number of format specifications exceed argument count" + severity ERROR; + return; + end if; + arg_num := arg_num + 1; + field_width := 0; + index := index + 1; + if (is_digit(look_ahead)) then + get_fw (fmt, index, field_width); + end if; + if (index <= fmt_len) then + string_type := fmt(index); + index := index + 1; + else + assert FALSE + report "fscan (TEXT) -- error in format specification" + severity ERROR; + return; + end if; + + case string_type is + when 'c' => if (field_width = 0) then + field_width := 1; + end if; + ii := 1; + while (field_width > 0) loop + ffgetc(ch, eof, file_ptr, line_ptr); + exit when ( eof ); + arg(ii) := ch; + ii := ii + 1; + field_width := field_width - 1; + end loop; + arg(ii) := NUL; + premature_end := ( eof and (ii = 1) ); + + when 'd' | 'f' | 's' | + 'o' | 'x' | 'X' | + 't' => -- skip over time unit if it follows %t + if ( string_type = 't') then + t_follow := (others => ' '); + ii := index; + jj := 2; + if ( (ii < fmt_len) and is_space(fmt(ii)) ) then + ii := ii + 1; + while ( (ii <= fmt_len) and (not is_space(fmt(ii))) and (jj <= 5) ) loop + t_follow(jj) := fmt(ii); + ii := ii + 1; + jj := jj + 1; + end loop; + if ( strcmp(t_follow, " fs ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " ps ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " ns ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " us ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " ms ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " sec ") = 0 ) then + index := index + 4; + elsif ( strcmp(t_follow, " min ") = 0 ) then + index := index + 4; + elsif ( strcmp(t_follow, " hr ") = 0 ) then + index := index + 3; + end if; + end if; + end if; + if ( field_width = 0 ) then + field_width := MAX_STRING_LEN + 1; + end if; + ffgetc (ch, eof, file_ptr, line_ptr); + while ( (is_space(ch) or (ch = LF) ) and (not eof) ) loop + ffgetc(ch, eof, file_ptr, line_ptr); + end loop; + ii := 1; + loop + exit when ( eof or is_space(ch) or (ch = LF) ); + arg(ii) := ch; + ii := ii + 1; + field_width := field_width - 1; + exit when (field_width = 0); + ffgetc(ch, eof, file_ptr, line_ptr); + end loop; + if ( (string_type = 't') and (not eof) and (field_width > 1) and (ch /= LF) ) then + arg(ii) := ' '; + ii := ii + 1; + field_width := field_width - 1; + ffgetc(ch, eof, file_ptr, line_ptr); + loop + exit when ( eof or is_space(ch) or (ch = LF) ); + arg(ii) := ch; + ii := ii + 1; + field_width := field_width - 1; + exit when (field_width = 0); + ffgetc(ch, eof, file_ptr, line_ptr); + end loop; + end if; + arg(ii) := NUL; + premature_end := ( eof and (ii = 1) ); + + when others => assert FALSE + report "fscan (TEXT) -- error in format specification" + severity ERROR; + return; + end case; + case arg_num is + when 1 => strcpy(arg1, arg); + when 2 => strcpy(arg2, arg); + when 3 => strcpy(arg3, arg); + when 4 => strcpy(arg4, arg); + when 5 => strcpy(arg5, arg); + when 6 => strcpy(arg6, arg); + when 7 => strcpy(arg7, arg); + when 8 => strcpy(arg8, arg); + when 9 => strcpy(arg9, arg); + when 10 => strcpy(arg10, arg); + when 11 => strcpy(arg11, arg); + when 12 => strcpy(arg12, arg); + when 13 => strcpy(arg13, arg); + when 14 => strcpy(arg14, arg); + when 15 => strcpy(arg15, arg); + when 16 => strcpy(arg16, arg); + when 17 => strcpy(arg17, arg); + when 18 => strcpy(arg18, arg); + when 19 => strcpy(arg19, arg); + when 20 => strcpy(arg20, arg); + when others => assert FALSE + report "fscan (TEXT) -- internal error" + severity ERROR; + return; + end case; + else -- compare for literal + scan_for_match (file_ptr, line_ptr, fchar, eof, mismatch); + index := index + 1; + end if; + + if (mismatch) then + assert NOT WarningsOn + report "fscan (TEXT) -- format string literal mismatch" + severity WARNING; + return; + end if; + + index := Find_NonBlank(fmt, index); + end loop; + + index := Find_NonBlank(fmt, index); + assert ( not (WarningsOn and ( (eof and (index <= fmt_len)) or premature_end) ) ) + report "fscan (TEXT) -- unexpected end of file" + severity WARNING; + + END fscan; + +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING ; + VARIABLE arg17 : OUT STRING ; + VARIABLE arg18 : OUT STRING ; + VARIABLE arg19 : OUT STRING + ) IS + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, arg16, arg17, arg18, + arg19, dumy_arg20, 19); + return; + END fscan; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING ; + VARIABLE arg17 : OUT STRING ; + VARIABLE arg18 : OUT STRING + ) IS + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, arg16, arg17, arg18, + dumy_arg19, dumy_arg20, 18); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING ; + VARIABLE arg17 : OUT STRING + ) IS + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, arg16, arg17, dumy_arg18, + dumy_arg19, dumy_arg20, 17); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING + ) IS + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, arg16, dumy_arg17, dumy_arg18, + dumy_arg19, dumy_arg20, 16); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING + ) IS + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, dumy_arg16, dumy_arg17, + dumy_arg18, dumy_arg19, dumy_arg20, 15); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING + ) IS + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 14); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING + ) IS + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 13); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING + ) IS + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 12); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING + ) IS + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, dumy_arg12, + dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 11); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING + ) IS + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, dumy_arg11, + dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 10); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING + ) IS + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, dumy_arg10, dumy_arg11, + dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 9); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING + ) IS + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, dumy_arg9, dumy_arg10, dumy_arg11, + dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 8); + return; + END; +--|--------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING + ) IS + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, dumy_arg8, dumy_arg9, dumy_arg10, dumy_arg11, + dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 7); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING + ) IS + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 6); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING + ) IS + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 5); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING + ) IS + VARIABLE dumy_arg5 : STRING(1 TO 10); + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, arg4, + dumy_arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 4); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING + ) IS + VARIABLE dumy_arg4 : STRING(1 TO 10); + VARIABLE dumy_arg5 : STRING(1 TO 10); + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, arg3, dumy_arg4, + dumy_arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 3); + return; + END; + + + +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING + ) IS + VARIABLE dumy_arg3 : STRING(1 TO 10); + VARIABLE dumy_arg4 : STRING(1 TO 10); + VARIABLE dumy_arg5 : STRING(1 TO 10); + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, arg2, dumy_arg3, dumy_arg4, + dumy_arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 2); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING + ) IS + VARIABLE dumy_arg2 : STRING(1 TO 10); + VARIABLE dumy_arg3 : STRING(1 TO 10); + VARIABLE dumy_arg4 : STRING(1 TO 10); + VARIABLE dumy_arg5 : STRING(1 TO 10); + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(file_ptr, line_ptr, format, arg1, dumy_arg2, dumy_arg3, dumy_arg4, + dumy_arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 1); + return; + END; + + +--+----------------------------------------------------------------------------- +--| Function Name : ffgetc +--| +--| Overloading : Text, ASCII_TEXT, string_buf +--| +--| Purpose : to read the next character from a file +--| +--| +--| Parameters : result - output character -- returned char +--| eof - output BOOLEAN -- TRUE if end of file reached +--| stream - in string -- file +--| ptr - inout INTEGER -- index into string buf +--| +--| Notes : returns with eof true if end of string is reached +--| : assumes a string starting at an index of 1 +--| +--|----------------------------------------------------------------------------- + + PROCEDURE ffgetc ( VARIABLE result : OUT CHARACTER; + VARIABLE eof : OUT BOOLEAN; + VARIABLE stream : IN STRING; + VARIABLE ptr : INOUT INTEGER + ) IS + + VARIABLE end_file : BOOLEAN; -- refers to end of string + + BEGIN + end_file := ( (ptr > stream'LENGTH) or (stream(ptr) = NUL) ); + if (not end_file) then + result := stream(ptr); + ptr := ptr + 1; + end if; + eof := end_file; + return; + END; + + +--+----------------------------------------------------------------------------- +--| Procedure Name : scan_for_match +--|.hidden +--| Overloading : TEXT and ASCII_TEXT and string_buf +--| +--| Purpose : To scan file skipping over blank spaces and newline +--| characters until a non-whitespace character is found. +--| If that character matches match_char then mismatch is +--| return false otherwise its TRUE. +--| +--| handles all three END_OF_LINE_MARKERS (LF, CR, and CR & LF) +--| +--| Parameters : str : IN STRING +--| ptr : INOUT INTEGER +--| match_char : IN CHARACTER +--| eof : INOUT BOOLEAN +--| mismatch : OUT BOOLEAN +--| +--|----------------------------------------------------------------------------- + + + procedure scan_for_match ( VARIABLE str : IN STRING; + VARIABLE ptr : INOUT INTEGER; + CONSTANT match_char : IN CHARACTER; + VARIABLE eof : INOUT BOOLEAN; + VARIABLE mismatch : OUT BOOLEAN ) is + + VARIABLE ch : CHARACTER; + VARIABLE cont : BOOLEAN; + + begin + if ( END_OF_LINE_MARKER = (LF, ' ') ) then + mismatch := FALSE; + ffgetc (ch, eof, str, ptr); + while ( (is_space(ch) or ( (ch = LF) and (match_char /= LF) ) ) and (not eof) ) loop + ffgetc (ch, eof, str, ptr); + end loop; + if (not eof) then + mismatch := (ch /= match_char); + end if; + elsif ( END_OF_LINE_MARKER = (CR, ' ') ) then + mismatch := FALSE; + ffgetc (ch, eof, str, ptr); + while ( (is_space(ch) or ( (ch = CR) and (match_char /= CR) ) ) and (not eof) ) loop + ffgetc (ch, eof, str, ptr); + end loop; + if (not eof) then + mismatch := (ch /= match_char); + end if; + else -- END_OF_LINE_MARKER = CR & LF + mismatch := FALSE; + cont := TRUE; + ffgetc (ch, eof, str, ptr); + while ( cont ) loop + while ( (is_space(ch) or ( ( (ch = CR) or (ch = LF) ) and (match_char /= CR) ) ) and (not eof) ) loop + ffgetc (ch, eof, str, ptr); + end loop; + CONT := FALSE; + if ( (match_char = CR) and (ch = CR) ) then + ffgetc(ch, eof, str, ptr); + cont := (ch /= LF); + if (not cont) then + return; + end if; + end if; + end loop; + if (not eof) then + mismatch := (ch /= match_char); + end if; + end if; + return; + end; + + + + +--+----------------------------------------------------------------------------- +--| Function Name : fscan +--| 1.2.4 +--| Overloading : TEXT, ASCII_TEXT, and string_buf +--| +--| Purpose : To read text from a string buffer according to +--| specifications given by a format string and save +--| the result into corresponding arguments. +--| +--| Parameters : +--| string_buf - input string, +--| format - input STRING, +--| arg1 - output STRING, +--| arg2 - output STRING, +--| arg3 - output STRING, +--| arg4 - output STRING, +--| arg5 - output STRING, +--| arg6 - output STRING, +--| arg7 - output STRING, +--| arg8 - output STRING, +--| arg9 - output STRING, +--| arg10 - output STRING +--| arg11 - output STRING, +--| arg12 - output STRING, +--| arg13 - output STRING, +--| arg14 - output STRING, +--| arg15 - output STRING, +--| arg16 - output STRING, +--| arg17 - output STRING, +--| arg18 - output STRING, +--| arg91 - output STRING, +--| arg20 - output STRING, +--| arg_count - input INTEGER - number of argumetns passed to fscan +--| +--| Result : STRING representation given TEXT. +--| +--| Note: This procedure extracts upto twenty arguments +--| from a string buffer. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING; + VARIABLE arg19 : OUT STRING; + VARIABLE arg20 : OUT STRING; + CONSTANT arg_count : IN INTEGER := 20 + ) IS + VARIABLE str_buffer : STRING(1 TO string_buf'LENGTH) := string_buf; -- hold string buffer + VARIABLE fmt : STRING(1 TO format'LENGTH) := format; -- hold format + VARIABLE index : INTEGER := 1; -- index into fmt + VARIABLE str_indx : INTEGER := 1; -- index into str_buffer + VARIABLE fmt_len : INTEGER; -- length of format + VARIABLE ch : CHARACTER; -- present character read from string buffer + VARIABLE fchar : CHARACTER; -- present format character + VARIABLE look_ahead : CHARACTER; -- next format character + VARIABLE mismatch : BOOLEAN := FALSE; -- TRUE if mismatch between format literal + -- and string buffer character + VARIABLE eof : BOOLEAN := FALSE; -- TRUE if end of string buffer + VARIABLE field_width : integer; -- field width + VARIABLE string_type : CHARACTER; -- type of string specified by format + VARIABLE arg_num : INTEGER := 0; -- number of argument currently being read + VARIABLE arg : string(1 to MAX_STRING_LEN+1); -- used to temporarily hold argument + VARIABLE premature_end : BOOLEAN := FALSE; -- true if end of string buffer reached prematurely + VARIABLE t_follow : string(1 to 5); -- used to check for time unit following %t + VARIABLE ii, jj : INTEGER; + + BEGIN + -- make return strings empty + arg1(arg1'left) := NUL; + arg2(arg2'left) := NUL; + arg3(arg3'left) := NUL; + arg4(arg4'left) := NUL; + arg5(arg5'left) := NUL; + arg6(arg6'left) := NUL; + arg7(arg7'left) := NUL; + arg8(arg8'left) := NUL; + arg9(arg9'left) := NUL; + arg10(arg10'left) := NUL; + arg11(arg11'left) := NUL; + arg12(arg12'left) := NUL; + arg13(arg13'left) := NUL; + arg14(arg14'left) := NUL; + arg15(arg15'left) := NUL; + arg16(arg16'left) := NUL; + arg17(arg17'left) := NUL; + arg18(arg18'left) := NUL; + arg19(arg19'left) := NUL; + arg20(arg20'left) := NUL; + + index := Find_NonBlank(fmt, index); + fmt_len := StrLen(fmt); + if ( index > fmt_len ) then + assert FALSE + report "fscan (String Buffer) -- empty format string." + severity ERROR; + return; + end if; + + eof := ( (str_indx > str_buffer'length) or (str_buffer(str_indx) = NUL) ); + + while ( (not eof) and (index <= fmt_len) ) loop + + fchar := fmt(index); + look_ahead := NUL; + mismatch := FALSE; + if (index < fmt_len) then + look_ahead := fmt(index+1); + else + look_ahead := ' '; + end if; + + + if ( (fchar = '\') and (look_ahead = 'n') ) then -- \n + if ( END_OF_LINE_MARKER = (LF, ' ') ) then + scan_for_match (str_buffer, str_indx, LF, eof, mismatch); + else + scan_for_match (str_buffer, str_indx, CR, eof, mismatch); + end if; + index := index + 2; + elsif ( (fchar = '%') and (look_ahead = '%') ) then -- check for literal % + scan_for_match (str_buffer, str_indx, '%', eof, mismatch); + index := index + 2; + elsif (fchar = '%') then + if (arg_num = arg_count) then + assert FALSE + report "fscan (String Buffer) -- number of format specifications exceed argument count" + severity ERROR; + return; + end if; + arg_num := arg_num + 1; + field_width := 0; + index := index + 1; + if (is_digit(look_ahead)) then + get_fw (fmt, index, field_width); + end if; + if (index <= fmt_len) then + string_type := fmt(index); + index := index + 1; + else + assert FALSE + report "fscan (String Buffer) -- error in format specification" + severity ERROR; + return; + end if; + + case string_type is + when 'c' => if (field_width = 0) then + field_width := 1; + end if; + ii := 1; + while (field_width > 0) loop + ffgetc(ch, eof, str_buffer, str_indx); + exit when ( eof ); + arg(ii) := ch; + ii := ii + 1; + field_width := field_width - 1; + end loop; + arg(ii) := NUL; + premature_end := (eof and (ii = 1) ); + + when 'd' | 'f' | 's' | + 'o' | 'x' | 'X' | + 't' => -- skip over time unit if it follows %t + if ( string_type = 't') then + t_follow := (others => ' '); + ii := index; + jj := 2; + if ( (ii < fmt_len) and is_space(fmt(ii)) ) then + ii := ii + 1; + while ( (ii <= fmt_len) and (not is_space(fmt(ii))) and (jj <= 5) ) loop + t_follow(jj) := fmt(ii); + ii := ii + 1; + jj := jj + 1; + end loop; + if ( strcmp(t_follow, " fs ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " ps ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " ns ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " us ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " ms ") = 0 ) then + index := index + 3; + elsif ( strcmp(t_follow, " sec ") = 0 ) then + index := index + 4; + elsif ( strcmp(t_follow, " min ") = 0 ) then + index := index + 4; + elsif ( strcmp(t_follow, " hr ") = 0 ) then + index := index + 3; + end if; + end if; + end if; + if ( field_width = 0 ) then + field_width := MAX_STRING_LEN + 1; + end if; + ffgetc (ch, eof, str_buffer, str_indx); -- skip over carrage return and line feed and spaces + while ( (is_space(ch) or (ch = LF) or (ch = CR) ) and (not eof) ) loop + ffgetc(ch, eof, str_buffer, str_indx); + end loop; + ii := 1; + loop + exit when ( eof or is_space(ch) or (ch = LF) or (ch = CR) ); + arg(ii) := ch; + ii := ii + 1; + field_width := field_width - 1; + exit when (field_width = 0); + ffgetc(ch, eof, str_buffer, str_indx); + end loop; + if ( (string_type = 't') and (not eof) and (field_width > 1) and (ch /= LF) and (ch /= CR) ) then + arg(ii) := ' '; + ii := ii + 1; + field_width := field_width - 1; + ffgetc(ch, eof, str_buffer, str_indx); + loop + exit when ( eof or is_space(ch) or (ch = LF) or (ch = CR) ); + arg(ii) := ch; + ii := ii + 1; + field_width := field_width - 1; + exit when (field_width = 0); + ffgetc(ch, eof, str_buffer, str_indx); + end loop; + end if; + arg(ii) := NUL; + premature_end := ( eof and (ii = 1) ); + + when others => assert FALSE + report "fscan (String Buffer) -- error in format specification" + severity ERROR; + return; + end case; + case arg_num is + when 1 => strcpy(arg1, arg); + when 2 => strcpy(arg2, arg); + when 3 => strcpy(arg3, arg); + when 4 => strcpy(arg4, arg); + when 5 => strcpy(arg5, arg); + when 6 => strcpy(arg6, arg); + when 7 => strcpy(arg7, arg); + when 8 => strcpy(arg8, arg); + when 9 => strcpy(arg9, arg); + when 10 => strcpy(arg10, arg); + when 11 => strcpy(arg11, arg); + when 12 => strcpy(arg12, arg); + when 13 => strcpy(arg13, arg); + when 14 => strcpy(arg14, arg); + when 15 => strcpy(arg15, arg); + when 16 => strcpy(arg16, arg); + when 17 => strcpy(arg17, arg); + when 18 => strcpy(arg18, arg); + when 19 => strcpy(arg19, arg); + when 20 => strcpy(arg20, arg); + when others => assert FALSE + report "fscan (String Buffer) -- internal error" + severity ERROR; + return; + end case; + else -- compare for literal + scan_for_match (str_buffer, str_indx, fchar, eof, mismatch); + index := index + 1; + end if; + + if (mismatch) then + assert NOT WarningsOn + report "fscan (String Buffer) -- format string literal mismatch" + severity WARNING; + return; + end if; + + index := Find_NonBlank(fmt, index); + end loop; + + index := Find_NonBlank(fmt, index); + assert ( not (WarningsOn and ( (eof and (index <= fmt_len)) or premature_end) ) ) + report "fscan (String BUffer) -- unexpected end of string" + severity WARNING; + + END fscan; + + +--|--------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING ; + VARIABLE arg17 : OUT STRING ; + VARIABLE arg18 : OUT STRING ; + VARIABLE arg19 : OUT STRING + ) IS + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, arg16, arg17, arg18, + arg19, dumy_arg20, 19); + return; + END; +--|--------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING ; + VARIABLE arg17 : OUT STRING ; + VARIABLE arg18 : OUT STRING + ) IS + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, arg16, arg17, arg18, + dumy_arg19, dumy_arg20, 18); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING ; + VARIABLE arg17 : OUT STRING + ) IS + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, arg16, arg17, dumy_arg18, + dumy_arg19, dumy_arg20, 17); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING ; + VARIABLE arg16 : OUT STRING + ) IS + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, arg16, dumy_arg17, dumy_arg18, + dumy_arg19, dumy_arg20, 16); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING ; + VARIABLE arg15 : OUT STRING + ) IS + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, arg15, dumy_arg16, dumy_arg17, + dumy_arg18, dumy_arg19, dumy_arg20, 15); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING ; + VARIABLE arg14 : OUT STRING + ) IS + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 14); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING ; + VARIABLE arg13 : OUT STRING + ) IS + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 13); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING ; + VARIABLE arg12 : OUT STRING + ) IS + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, arg12, + dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 12); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING ; + VARIABLE arg11 : OUT STRING + ) IS + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, arg11, dumy_arg12, + dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 11); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING ; + VARIABLE arg10 : OUT STRING + ) IS + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, arg10, dumy_arg11, + dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 10); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING + ) IS + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, arg9, dumy_arg10, dumy_arg11, + dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 9); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING + ) IS + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, arg8, dumy_arg9, dumy_arg10, dumy_arg11, + dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 8); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING + ) IS + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, arg7, dumy_arg8, dumy_arg9, dumy_arg10, dumy_arg11, + dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, dumy_arg16, + dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 7); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING + ) IS + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 6); + return; + END; +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING + ) IS + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 5); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING + ) IS + VARIABLE dumy_arg5 : STRING(1 TO 10); + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, arg4, + dumy_arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 4); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING + ) IS + VARIABLE dumy_arg4 : STRING(1 TO 10); + VARIABLE dumy_arg5 : STRING(1 TO 10); + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, arg3, dumy_arg4, + dumy_arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 3); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING + ) IS + VARIABLE dumy_arg3 : STRING(1 TO 10); + VARIABLE dumy_arg4 : STRING(1 TO 10); + VARIABLE dumy_arg5 : STRING(1 TO 10); + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, arg2, dumy_arg3, dumy_arg4, + dumy_arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 2); + return; + END; +--|---------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING + ) IS + VARIABLE dumy_arg2 : STRING(1 TO 10); + VARIABLE dumy_arg3 : STRING(1 TO 10); + VARIABLE dumy_arg4 : STRING(1 TO 10); + VARIABLE dumy_arg5 : STRING(1 TO 10); + VARIABLE dumy_arg6 : STRING(1 TO 10); + VARIABLE dumy_arg7 : STRING(1 TO 10); + VARIABLE dumy_arg8 : STRING(1 TO 10); + VARIABLE dumy_arg9 : STRING(1 TO 10); + VARIABLE dumy_arg10 : STRING(1 TO 10); + VARIABLE dumy_arg11 : STRING(1 TO 10); + VARIABLE dumy_arg12 : STRING(1 TO 10); + VARIABLE dumy_arg13 : STRING(1 TO 10); + VARIABLE dumy_arg14 : STRING(1 TO 10); + VARIABLE dumy_arg15 : STRING(1 TO 10); + VARIABLE dumy_arg16 : STRING(1 TO 10); + VARIABLE dumy_arg17 : STRING(1 TO 10); + VARIABLE dumy_arg18 : STRING(1 TO 10); + VARIABLE dumy_arg19 : STRING(1 TO 10); + VARIABLE dumy_arg20 : STRING(1 TO 10); + BEGIN + -- call procedure fscan with 20 arguments + fscan(string_buf, format, arg1, dumy_arg2, dumy_arg3, dumy_arg4, + dumy_arg5, dumy_arg6, dumy_arg7, dumy_arg8, dumy_arg9, dumy_arg10, + dumy_arg11, dumy_arg12, dumy_arg13, dumy_arg14, dumy_arg15, + dumy_arg16, dumy_arg17, dumy_arg18, dumy_arg19, dumy_arg20, 1); + return; + END; + +--+---------------------------------------------------------------------------- +--| Function Name : fgetc +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To read the next character from a file of type +--| ASCII_TEXT. +--| +--| Parameters : +--| stream - input ASCII_TEXT, +--| +--| Result : Returns the ordinate value of the character read. If +--| end of file is reached then return - 1 +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| USE: : +--| VARIABLE n : Integer; +--| FILE f_in : ASCII_TEXT IS IN "design.doc"; +--| +--| fgetc(n, f_in); +--| +--| Will return ordinal value of character in integer n +--|----------------------------------------------------------------------------- + PROCEDURE fgetc ( VARIABLE result : OUT INTEGER; + VARIABLE stream : IN ASCII_TEXT + ) IS + VARIABLE ch : CHARACTER; + BEGIN + IF ( NOT ENDFILE(stream)) THEN + READ(stream, ch); + result := CHARACTER'POS(ch); + ELSE + result := -1; -- end of file + END IF; + return; + + END; + +--+----------------------------------------------------------------------------- +--| Function Name : fgetc +--| +--| Overloading : None +--| +--| Purpose : To read the next character from a file of type TEXT. +--| +--| Parameters : +--| stream - input TEXT, +--| ptr - INOUT, LINE +--| Result :Integer, the ordinate value of the character being read. +--| -1 when end of file (EOF). +--| +--| Note: : The TEXT is defined in the package TEXTIO to be +--| a file of string. +--| +--| USE: : +--| VARIABLE n : Integer; +--| FILE f_in : TEXT IS IN "design.doc"; +--| +--| fgetc(n, f_in); +--| +--| Will return ordinal value of character in integer n +--| +--| Problems : When reading last line of file, if it is terminated with +--| an end of line marker then when the end of the last line is +--| reached the final eol will not be returned (instead -1 will be +--| returned). +--| +--|----------------------------------------------------------------------------- + PROCEDURE fgetc ( VARIABLE result : OUT INTEGER; + VARIABLE stream : IN TEXT; + VARIABLE ptr : INOUT LINE + ) IS + VARIABLE ch : character; + + BEGIN + if ( (ptr /= NULL) and (ptr'LENGTH /= 0) ) then + READ(ptr, ch); + result := CHARACTER'POS(ch); + elsif ( not ENDFILE(stream) ) then + if ( ptr /= NULL) then -- ptr'length = 0 + READLINE(stream, ptr); + result := 10; -- ascii code for LF (line feed) + else -- ptr = null (this should mean its at the beginning of the file) + READLINE(stream, ptr); + READ(ptr, ch); + result := CHARACTER'POS(ch); + end if; + else + result := -1; -- end of file + end if; + return; + END; + +--+----------------------------------------------------------------------------- +--| Function Name : fgets +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To read, at most, the next n characters from a file +--| of type ASCII_TEXT and save them to a string. +--| +--| Parameters : +--| l_str -- output, STRING, +--| +--| n -- input, Natural, number of +--| characters to be read. +--| stream -- input, ASCII_TEXT, input file. +--| +--| result : string +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| USE: : +--| VARIABLE str_buf : string(1 TO 100); +--| FILE f_in : ASCII_TEXT IS IN "design.doc"; +--| +--| fgets(str_buf, 50, f_in); +--| +--| Will read in at most 50 characters from the file +--| design.doc and place them in str_buf. +--|----------------------------------------------------------------------------- + PROCEDURE fgets ( VARIABLE l_str : OUT STRING; + CONSTANT n : IN NATURAL; + VARIABLE stream : IN ASCII_TEXT + ) IS + VARIABLE ch : CHARACTER; + VARIABLE lstr_cpy : STRING(1 TO n); + VARIABLE index : NATURAL := 0; + BEGIN + IF (n=0) THEN + if (l_str'LENGTH > 0 ) then + l_str(l_str'LEFT) := NUL; + end if; + return; + ELSE + assert ( not (WarningsON and ENDFILE(stream)) ) + report "fgets (ASCII_TEXT) -- attempt to read past end of file" + severity WARNING; + + while ( NOT ENDFILE(stream) ) LOOP + READ(stream, ch); + index := index + 1; + lstr_cpy(index) := ch; + EXIT when ((index >= n) OR (ch = END_OF_LINE_MARKER(1))); + END LOOP; + END IF; + + -- determine the length of string and place charcaters + IF (l_str'LENGTH <= n) THEN + l_str := lstr_cpy(1 TO l_str'LENGTH); + ELSE + l_str(1 TO n) := lstr_cpy; + l_str(n+1) := NUL; + END IF; + + RETURN; + END; + +--+----------------------------------------------------------------------------- +--| Function Name : fgets +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To read, at most, the next n characters from a file +--| of type TEXT and save them to a string. +--| +--| Parameters : +--| l_str -- output, STRING, +--| n -- input, Natural, number of +--| characters to be read. +--| stream -- input, TEXT, input file. +--| line_ptr -- inout LINE, +--| +--| result : string +--| +--| Note: : The TEXT is defined in the package TEXTIO to be +--| a file of string. +--| +--| USE: : +--| VARIABLE str_buf : string(1 TO 100); +--| FILE f_in : TEXT IS IN "design.doc"; +--| +--| fgets(str_buf, 50, f_in); +--| +--| Will read in at most 50 characters from the file +--| design.doc and place them in str_buf. +--|----------------------------------------------------------------------------- + PROCEDURE fgets ( VARIABLE l_str : OUT STRING; + CONSTANT n : IN NATURAL; + VARIABLE stream : IN TEXT; + VARIABLE line_ptr : INOUT LINE + ) IS + + VARIABLE ch : character; + VARIABLE str : STRING( 1 TO n+1); + VARIABLE counter : integer := 0; + + BEGIN + -- + if ( (line_ptr = NULL) or (line_ptr'LENGTH = 0) ) then + if (ENDFILE(stream)) then + assert (not WarningsON) + report "fgets (text) -- attempt to read past end of file" + severity WARNING; + str(1) := NUL; + strcpy(l_str, str); + return; + else + READLINE(stream, line_ptr); + end if; + end if; + for i IN 1 to n loop + exit when ( (line_ptr = NULL) or (line_ptr'LENGTH = 0) ); + READ(line_ptr, ch); + str(i) := ch; + counter := counter + 1; + end loop; + str(counter + 1) := NUL; + strcpy(l_str, str); + RETURN; + END; + +--+--------------------------------------------------------------------------- +--| Function Name : fgetline +--| +--| Overloading : None +--| +--| Purpose : To read a line from the input ASCII_TEXT file and +--| save into a string. +--| +--| Parameters : +--| l_str -- output, STRING, +--| stream -- input, ASCII_TEXT, input file +--| +--| result : string. +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| USE: : +--| VARIABLE line_buf : string(1 TO 256); +--| FILE in_file : ASCII_TEXT IS IN "file_ascii_in.dat"; +--| +--| fgetline(line_buf, in_file); +--| +--| Will read a line from the file +--| file_ascii_in.dat and place into line_buf. +--|----------------------------------------------------------------------------- + PROCEDURE fgetline ( VARIABLE l_str : OUT STRING; + VARIABLE stream : IN ASCII_TEXT + ) IS + VARIABLE ch : character := ' '; + VARIABLE indx : integer := 0; + VARIABLE str_copy : STRING(1 TO max_string_len); + BEGIN + -- + IF ENDFILE(stream) THEN + assert Not WarningsOn + report " fgetline (ASCII_TEXT) --- end of file, nothing to read." + severity WARNING; + if (l_str'LENGTH > 0 ) then + l_str(l_str'LEFT) := NUL; + end if; + return; + ELSE + while ( (not ENDFILE(stream)) and (ch /= END_OF_LINE_MARKER(1)) ) loop + READ(stream, ch); + indx := indx + 1; + str_copy(indx) := ch; + end loop; + -- determine the length and place characters + IF (l_str'LENGTH <= indx) THEN + l_str := str_copy(1 TO l_str'LENGTH); + ELSE + l_str(1 TO indx) := str_copy(1 TO indx); + l_str(indx+1) := NUL; + END IF; + RETURN; + END IF; + + END; + +--+--------------------------------------------------------------------------- +--| Function Name : fgetline +--| +--| Overloading : None +--| +--| Purpose : To read a line from the input TEXT file and +--| save into a string. +--| +--| Parameters : +--| l_str -- output, STRING, +--| stream -- input, TEXT, input file +--| +--| result : string. +--| +--| Note: : The TEXT is defined in the package TEXTIO to be +--| a file of string. +--| USE: : +--| VARIABLE line_buf : string(1 TO 256); +--| FILE in_file : TEXT IS IN "file_text_in.dat"; +--| +--| fgetline(line_buf, in_file); +--| +--| Will read a line from the file +--| file_text_in.dat and place into line_buf. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fgetline ( VARIABLE l_str : OUT STRING; + VARIABLE stream : IN TEXT; + VARIABLE line_ptr : INOUT LINE + ) IS + VARIABLE str_copy : STRING(1 TO max_string_len + 1); + VARIABLE ch : character; + VARIABLE indx : NATURAL := 0; + BEGIN + If ( (line_ptr /= NULL) and (line_ptr'LENGTH > 0) ) then + NULL; + elsif ( not ENDFILE(stream) ) then + READLINE(stream, line_ptr); + else + assert NOT WarningsOn + report " fgetline (TEXT) --- end of file, nothing to read." + severity WARNING; + l_str(l_str'left) := NUL; + return; + end if; + while ( (line_ptr /= NULL) and (line_ptr'length /= 0) ) loop + READ(line_ptr,ch); + indx := indx + 1; + str_copy(indx) := ch; + end loop; + str_copy(indx + 1) := NUL; + strcpy(l_str, str_copy); + return; + END; + +--+----------------------------------------------------------------------------- +--| Function Name : fputc +--| 1.2.4 +--| Overloading : None +--| +--| Purpose :To write a character to an ASCII_TEXT file. +--| +--| Parameters : +--| c -- input, CHARACTER, +--| stream -- output ASCII_TEXT, +--| +--| Result : +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| This procedure is equivalent to VHDL WRITE(stream, c). +--| +--| USE: : +--| VARIABLE str12 : string(1 TO 12); +--| FILE out_file : ASCII_TEXT IS OUT "file_ascii_out.dat"; +--| +--| str12 := "0123456789ab"; +--| FOR i IN 1 TO 12 LOOP +--| fputc(str12(i), out_file); +--| END LOOP; +--| +--| Will write all the 12 characters to file +--| file_ascii_out.dat +--|----------------------------------------------------------------------------- + PROCEDURE fputc ( CONSTANT c : IN CHARACTER; + VARIABLE stream : OUT ASCII_TEXT + ) IS + BEGIN + WRITE(stream, c); -- built_in write + END; + +--+----------------------------------------------------------------------------- +--| Function Name : fputc +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To write a character to a TEXT file. +--| +--| Parameters : +--| c -- input, CHARACTER, +--| stream -- output, TEXT, +--| line_ptr -- INOUT LINE +--| +--| Result : +--| +--| Note: : The STD TEXTIO package has declared TEXT as a +--| file of STRING. This is not same as file of CHARACTERS. +--| +--| USE: : +--| VARIABLE str12 : string(1 TO 12); +--| VARIABLE l : LINE; +--| FILE out_file : TEXT IS OUT "file_text_out.dat"; +--| +--| str12 := "0123456789ab"; +--| FOR i IN 1 TO 12 LOOP +--| fputc(str12(i), out_file, l); +--| END LOOP; +--| fputc(LF, out_file, l); -- line feed +--| +--| Will write contents of the str12 to file +--| file_text_out.dat. The characters will be kept in +--| the line pointer l untill line feed character is +--| encouneterd. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fputc ( CONSTANT c : IN character; + VARIABLE stream : OUT TEXT; + VARIABLE line_ptr : INOUT LINE + ) IS + + BEGIN + if ( (c = LF) or (c = CR) ) THEN + WRITELINE(stream, line_ptr); + DEALLOCATE(line_ptr); + else + write(line_ptr, c); + END IF; + RETURN; + END; + +--+----------------------------------------------------------------------------- +--| Function Name : fputs +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To write a string to an ASCII_ TEXT file. +--| +--| Parameters : +--| l_str -- input, string +--| stream -- output, ASCII_TEXT, +--| +--| Result : +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| USE: : +--| VARIABLE str_buf : string(1 TO 256); +--| FILE out_file : ASCII_TEXT IS OUT "file_ascii_out.dat"; +--| +--| fputs(str_buf, out_file); +--| +--| Will write contents of str_buf to the file +--| file_ascii_out.dat +--| +--|----------------------------------------------------------------------------- + PROCEDURE fputs ( CONSTANT l_str : IN STRING; + VARIABLE stream : OUT ASCII_TEXT + ) IS + VARIABLE str_copy : String (1 TO l_str'LENGTH) := l_str; + VARIABLE ch : character; + BEGIN + FOR i IN 1 TO l_str'LENGTH LOOP + ch := str_copy(i); + exit when (ch = NUL); + write (stream, ch); + END LOOP; + + write (stream, END_OF_LINE_MARKER(1)); + return; + + END fputs; + +--+----------------------------------------------------------------------------- +--| Function Name : fputs +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To write a string to a TEXT file. +--| +--| Parameters : +--| l_str -- input, string, +--| stream -- output, TEXT, +--| line_ptr -- INOUT LINE, +--| +--| Result : +--| +--| Note: : The STD TEXTIO package has declared TEXT as a +--| file of STRING. This is not same as file of CHARACTERS. +--| USE: : +--| VARIABLE str_buf : string(1 TO 256); +--| VARIABLE lptr : LINE; +--| FILE out_file : TEXT IS OUT "file_text_out.dat"; +--| +--| fputs(str_buf, out_file, lptr); +--| +--| Will write contents of str_buf to the file +--| file_text_out.dat +--| +--|----------------------------------------------------------------------------- + PROCEDURE fputs ( CONSTANT l_str : IN STRING; + VARIABLE stream : OUT TEXT; + VARIABLE line_ptr : INOUT LINE + ) IS + + + BEGIN + FOR i IN l_str'RANGE LOOP + exit when (l_str(i)= NUL); + WRITE(line_ptr, l_str(i)); + END LOOP; + WRITELINE(stream, line_ptr); + DEALLOCATE(line_ptr); + RETURN; + END fputs; + +--+----------------------------------------------------------------------------- +--| Function Name : Find_Char +--| +--| Overloading : None +--| +--| Purpose : TO find a given character in a string and +--| return its position. +--| +--| Parameters : +--| l_str - input STRING, +--| c - input Character, +--| +--| Result : NATURAL number representing the position of character +--| in the string. returns 0 if character not found in the +--| string. +--| +--| USE: : +--| VARIABLE str14 : string(1 TO 14); +--| VARIABLE indx : integer; +--| +--| str14 :="This is a test"; +--| indx := Fid_Char(str14, 'i'); +--| +--| Will assign value of 3 to the variable indx. +--|----------------------------------------------------------------------------- + FUNCTION Find_Char ( CONSTANT l_str : IN STRING; + CONSTANT c : IN CHARACTER + ) RETURN NATURAL IS + VARIABLE result : NATURAL := 0; + VARIABLE index : INTEGER := 0; + VARIABLE lstr_cpy : STRING(1 TO l_str'LENGTH) := l_str; + BEGIN + While ( index < l_str'LENGTH) LOOP + index := index + 1; + IF (lstr_cpy(index) = NUL) THEN + EXIT; + END IF; + IF ( c = lstr_cpy(index)) THEN + result := index; + EXIT; + END IF; + END LOOP; + RETURN result; + END; +--+----------------------------------------------------------------------------- +--| Function Name : Sub_Char +--| +--| Overloading : None +--| +--| Purpose : To subtitute a new character at a given position +--| of the input string. +--| +--| Parameters : +--| l_str - input STRING, +--| c - input Character, +--| n - input Natural, position at which character +--| is to be substituted. +--| Result : STRING +--| +--| USE: : +--| VARIABLE str14 : string(1 TO 14); +--| VARIABLE indx : integer; +--| +--| str14 :="This is a test"; +--| IF ((indx = Find_Char(str14, 't')) /= 0) THEN +--| str14 := Sub_Char(str14, 'T', indx); +--| END IF; +--| +--| Will assign the value "This is a Test" to str14. +--|----------------------------------------------------------------------------- + FUNCTION Sub_Char ( CONSTANT l_str : IN STRING; + CONSTANT c : IN CHARACTER; + CONSTANT n : IN NATURAL + ) RETURN STRING IS + VARIABLE result : STRING(1 TO l_str'LENGTH) := l_str; + BEGIN + IF (n <= l_str'LENGTH) THEN + result(n) := c; + ELSE + ASSERT NOT WarningsOn + REPORT " Sub_Char --- n out of range " + SEVERITY WARNING; + END IF; + RETURN result; + END Sub_Char; + + + + + + + + + + + + + + + + + + + + + + + + +--+----------------------------------------------------------------------------- +--| Function Name : T_Machine +--| hidden +--| Overloading : None +--| +--| Purpose : Finite State automaton to recognise a time format. +--| format will be broken into field width, precision +--| and justification (left or right) and time_unit (tu); +--| +--| Parameters : fwidth -- output, INTEGER, field width +--| precision -- output, INTEGER, precison +--| justify -- OUTPUT, BIT +--| '0' right justified, +--| '1' left justified +--| t_unit -- output, STRING, time unit of +--| result +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : +--| +--| NOTE : +--| This procedure is +--| called in the function To_String. +--| +--| Use : +--| VARIABLE fmt : STRING(1 TO format'LENGTH) := format; +--| VARIABLE fw : INTEGER; +--| VARIABLE precis : INTEGER; +--| VARIABLE justfy : BIT; +--| VARIABLE tu : STRING(1 TO 2); +--| +--| T_Machine(fw, precis, justy,i tu, fmt); +--| +--|----------------------------------------------------------------------------- + + PROCEDURE T_Machine ( VARIABLE fwidth : OUT INTEGER; + VARIABLE precison : OUT INTEGER; + VARIABLE justify : OUT BIT; + VARIABLE t_unit : OUT time_unit_type; + CONSTANT format : IN STRING + ) IS + VARIABLE state : INT8 := 0; + VARIABLE fmt : STRING(1 TO format'LENGTH); + VARIABLE ch : CHARACTER; + VARIABLE index : INTEGER := 1; + VARIABLE fw : INTEGER := 0; + VARIABLE pr : INTEGER := -1; + VARIABLE tu : STRING(1 TO 3) := (others =>' '); + VARIABLE tu_indx : INTEGER := 0; + VARIABLE e_flag : boolean := false; + + BEGIN + fmt := To_Lower(format); + -- make sure first character is '%' if not error + ch := fmt(index); + IF (fmt(index) /= '%') THEN + ASSERT false + REPORT " Format Error --- first character of format " & + " is not '%' as expected." + SEVERITY ERROR; + return; + END IF; + justify := '0'; -- default is right justification + WHILE (state /= 3) LOOP + if (index < format'LENGTH) THEN + index := index + 1; + ch := fmt(index); + CASE state IS + WHEN 0 => IF (ch ='-') THEN + state := 1; -- justify + ELSIF (ch >= '0' AND ch <= '9') THEN -- to_digit + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); + state := 2; -- digits state + ELSIF (ch = 't') THEN + state := 3; -- end state + ELSIF (ch = '.') THEN + state := 4; + ELSIF (ch = '%') THEN + state := 5; + ELSE + state := 6; -- error + END IF; + + WHEN 1 => justify := '1'; -- left justfy + IF (ch >= '0' AND ch <= '9') THEN -- to_digit + fw := CHARACTER'POS(ch) - CHARACTER'POS('0'); + state := 2; + ELSIF (ch = '.') THEN + state := 4; + ELSIF (ch = 't') THEN + justify := '0'; -- %-t is equivalent to %t + state := 3; + ELSE + state := 6; -- error + END IF; + + WHEN 2 => -- digits-state + IF (ch >= '0' AND ch <= '9') THEN + fw := fw * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); + state := 2; + ELSIF (ch = 't') THEN + state := 3; + ELSIF (ch = '.') THEN + state := 4; + ELSE + state := 6; + END IF; + + WHEN 3 => -- t state + -- fromat successfully recognized, exit now. + EXIT; + + WHEN 4 => -- . state + IF (ch >= '0' AND ch <= '9') THEN -- to_digit + pr := CHARACTER'POS(ch) - CHARACTER'POS('0'); + state := 7; + ELSE + state := 6; -- error + END IF; + + WHEN 5 => -- print % + EXIT; + + WHEN 6 => -- error state + -- print error message + ASSERT false + REPORT " Format Error --- expected %t format. " + SEVERITY ERROR; + EXIT; + + WHEN 7 => -- precision + IF (ch >= '0' AND ch <= '9') THEN + pr := pr * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); -- to_digit + state := 7; + ELSIF (ch = 't') THEN + state := 3; + ELSE + state := 6; -- error + END IF; + END CASE; + ELSE + assert false + report " Format Error: Observed =" & fmt &LF + & " Expected = %t unit (detected by T_Machine) " + severity ERROR; + e_flag := true; + exit; + END IF; + END LOOP; + + IF (Not e_flag) THEN + index := index + 1; + if (index < format'LENGTH) then + ch := fmt(index); + end if; + while ((index < format'LENGTH) AND Is_Space(ch)) LOOP + index := index + 1; + ch := fmt(index); + END LOOP; + + if (index < format'LENGTH) then + If (ch >='a' AND ch <='z') THEN + tu(1) := ch; + tu(2) := fmt(index + 1); + if (format'Length >= index + 2) then + tu(3) := fmt(index+2); + end if; + END IF; + end if; + -- this case statement decides the time unit. + CASE tu IS + WHEN "fs " => t_unit := t_fs; + WHEN "ps " => t_unit := t_ps; + WHEN "ns " => t_unit := t_ns; + WHEN "us " => t_unit := t_us; + WHEN "ms " => t_unit := t_ms; + WHEN "sec" => t_unit := t_sec; + WHEN "min" => t_unit := t_min; + WHEN "hr " => t_unit := t_hr; + WHEN OTHERS => ASSERT false + REPORT " Format error --- time unit is not specified " + & "correctly in the format string " + SEVERITY ERROR; + END CASE; + END IF; + -- decide field width (fwidth) + IF (fw > max_string_len) THEN + fwidth := max_string_len; + ELSE + fwidth := fw; + END IF; + -- decide precision + IF (pr = -1) THEN + precison := 6; -- use default precision + ELSE + precison := pr; + END IF; + RETURN; + END T_Machine; + +--+----------------------------------------------------------------------------- +--| Function Name : Default_Time +--| hidden +--| Overloading : None +--| + +--| Purpose : Convert 64 bit Time value to a String with +--| default length of 12. + + +--| +--| Parameters : +--| val - input, TIME, +--| +--| Result : STRING representation of TIME. +--| +--| NOTE : This function converts input time to an appropriate +--| time units such that it can be represented in a string +--| length 7 (xxx.xxx). Then 4 places for unit + +--| ( hr, min, sec, ms ps etc.) are needed and one more for + +--| sign ( -/+ ). IF time is positive then sign position is +--| left blank. This way this function will return a string +--| of length 12. +--| signXXX.XXX Unit ( sign takes one location and units 3). +--| +--| +--|----------------------------------------------------------------------------- + + + FUNCTION Default_Time ( CONSTANT val : IN TIME + ) RETURN STRING IS + VARIABLE tval : time; + VARIABLE ival : integer := 0; + VARIABLE fval : integer := 0; + VARIABLE same_unit : Boolean := false; + VARIABLE sign : character := ' '; + VARIABLE prefix : string(1 to 7) := " . "; + VARIABLE suffix : string(1 to 4) := " "; + VARIABLE digit : integer range 0 to 9; + type char10 is array (Integer range 0 to 9) of character; + CONSTANT lookup : char10 := ( '0','1','2','3','4','5','6','7','8','9'); + BEGIN + -- Handling sign + IF ( val < 0 ns ) THEN + sign := '-'; + tval := - val; + ELSE + sign := ' '; + tval := val; + END IF; + -- selecting proper unit dynamically + + -- check for 0 time (whether input time is 0 fs, 0 ps, 0 ns etc) + + -- it will be treated as 0 ns / 1000000 internally. We will provide default + -- time as 0.000 ns. + -- + IF (tval = 0 ns) then + ival := 0; + suffix := " ns "; + + ELSIF ( tval >= 1 hr ) then + ival := (tval / 1 min ); -- gives it in terms of 60's + -- of min + suffix := " hr "; + fval := (ival mod 60); + ival := (1000 * (ival/60)) + ( fval * 1000 / 60); + ELSIF ( tval >= 1 min ) then + ival := (tval / 1 sec); -- gives it in terms of 60's of sec + suffix := " min"; + fval := ival mod 60; + ival := (1000 * (ival/60)) + (fval * 1000 / 60); + + ELSIF ( tval >= 1 sec ) then + ival := tval / 1 ms; -- gives it in terms of 1000's of ms + suffix := " sec"; + ELSIF ( tval >= 1 ms ) then + ival := tval / 1 us; -- gives it in terms of 1000's of us + suffix := " ms "; + + + ELSIF (tval >= 1 us) then + ival := tval / 1 ns; -- gives it in terms of 1000s of ns + suffix := " us "; + + + ELSIF ( tval >= 1 ns) THEN + suffix := " ns "; + if ( (1 ns / 1000) = 0 ns ) then + ival := tval / (1 ns); + same_unit := TRUE; + else + ival := tval / (1 ns / 1000); -- gives it in terms of 1000s of 1 ns / 1000 + end if; + + + + ELSIF ( tval >= (1 ns / 1000) ) THEN + suffix := " ps "; + if ( (1 ns / 1000000) = 0 ns ) then + ival := tval / (1 ns / 1000); + same_unit := TRUE; + else + ival := tval / (1 ns / 1000000); -- gives it in terms of 1000s of 1 ns / 1000000 + end if; + + ELSIF ( tval >= (1 ns / 1000000) ) THEN + ival := tval / (1 ns / 1000000); + suffix := " fs "; + same_unit := TRUE; + END IF; + -- converting to XXX.XXX format + IF ( same_unit ) THEN + prefix(5 TO 7) := (OTHERS => '0'); + ELSE + FOR i IN 7 DOWNTO 5 LOOP + digit := ival mod 10; + ival := ival / 10; + prefix (i) := lookup(digit); + END LOOP; + END IF; + FOR i IN 3 DOWNTO 1 LOOP + digit := ival mod 10; + ival := ival / 10; + prefix (i) := lookup(digit); + END LOOP; + -- get rid of leading zero's + leading_zero_kill : FOR i IN 1 to 2 LOOP + exit leading_zero_kill WHEN (prefix(i) /= '0'); + IF (prefix(i) = '0') THEN + prefix (i) := ' '; + END IF; + END LOOP; + if (prefix(2) = ' ') then + return ( " " & sign & prefix(3 to 7) & suffix); + elsif (prefix(1) = ' ') then + return ( ' ' & sign & prefix(2 to 7) & suffix); + else + RETURN (sign & prefix & suffix); + end if; + END Default_Time; + +--+----------------------------------------------------------------------------- +--| Function Name : Time_String +--| hidden +--| Overloading : None +--| + +--| Purpose : Convert 64 bit Time value to a String based upon fs + +--| +--| Parameters : val - input, TIME positive val, +--| + +--| Result : A STRING of length 20 representing TIME. + +--| +--| +--|----------------------------------------------------------------------------- + FUNCTION Time_String ( CONSTANT val : IN TIME ) RETURN STRING IS + + + CONSTANT buf_len : INTEGER := 20; + + TYPE t_to_int_type is array (1 to 6) of integer; + + VARIABLE t_to_int : t_to_int_type := (others => 0); + VARIABLE tbuf : STRING(1 to buf_len) := (others => '0'); + VARIABLE ival : integer; + VARIABLE tval : time := val; + VARIABLE i, index : integer; + VARIABLE min_str_index : integer; + VARIABLE time_unit : time; + VARIABLE min_time_unit : time; + VARIABLE start_int_ind : integer; + VARIABLE num, counter : integer; + + BEGIN + -- identify minimum time unit + min_time_unit := 1 ns / 1000000; + if ( min_time_unit > 0 ns ) then -- fs + start_int_ind := 1; + else + min_time_unit := 1 ns / 1000; + if ( min_time_unit > 0 ns ) then -- ps + start_int_ind := 2; + else -- ns + min_time_unit := 1 ns; + start_int_ind := 3; + end if; + end if; + + -- get minimum string index + min_str_index := 1; + + if (min_time_unit = (1 ns / 1000)) then + min_str_index := 4; + elsif (min_time_unit = 1 ns) then + min_str_index := 7; + end if; + + + -- get starting time_unit and starting integer array index + time_unit := min_time_unit; + for i in 1 to (((buf_len - min_str_index)/3)-1) loop + time_unit := time_unit * 1000; + start_int_ind := start_int_ind + 1; + end loop; + -- start_int_ind now is at the maximum value + + -- get integer equivalent + -- start with maximum time_unit and work down to minimum + i := start_int_ind; + while time_unit > 0 ns loop + t_to_int(i) := tval / time_unit; + tval := tval - t_to_int(i) * time_unit; + time_unit := time_unit/1000; + i := i - 1; + end loop; + index := i + 1; + + -- convert intpeger array to a string + i := buf_len - min_str_index + 1; + counter := 0; + while i > 0 loop + if (counter mod 3 = 0) and (index <= start_int_ind) then + num := t_to_int(index); + index := index + 1; + end if; + tbuf(i) := CHARACTER'VAL(CHARACTER'POS('0') + (num mod 10)); + num := num/10; + i := i - 1; + counter := counter + 1; + end loop; + return tbuf; + END Time_String; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a time. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : Time +--| +--| NOTE : +--| +--| Use : +--| VARIABLE t : time ; +--| +--| t := From_String (" 893.56 ns"); +--| This statement will set t to time 893.56 ns. +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN TIME IS + VARIABLE result : TIME; + VARIABLE fract_t : TIME; + VARIABLE state : INT8; + VARIABLE str_copy : STRING (1 TO str'LENGTH):= To_Upper(str); + VARIABLE index : Natural; + VARIABLE power : Natural := 0; + VARIABLE num : Integer := 0; + VARIABLE fract_num : Integer := 0; + VARIABLE ch : character; + VARIABLE neg_sign : boolean := false; + VARIABLE tu : string(1 To 3) := (OTHERS => ' '); + VARIABLE tu_indx : INTEGER := 0; + VARIABLE parse_err : BOOLEAN := FALSE; + + BEGIN + -- Check for null input + IF (str'LENGTH = 0) THEN + assert false + report " From_String --- input string has a null range " + severity ERROR; + RETURN TIME'LEFT; + END IF; + -- find the position of the first non_white character + index := Find_NonBlank(str_copy); + IF (index > str'length) THEN + assert false + report " From_String --- input string is empty "; + RETURN TIME'LEFT; + ELSIF (str_copy(index)=NUL) THEN + assert false + report " From_String -- first non_white character is a NUL "; + RETURN TIME'LEFT; + END IF; + ch := str_copy(index); + -- check for - sign or + sign + IF (ch = '-') Then + neg_sign := NOT neg_sign; + index := index + 1; + ch := str_copy(index); -- get_char + elsif (ch = '+') then + index := index + 1; + ch := str_copy(index); -- get_char + END IF; + + -- Strip off leading zero's + While ( (ch = '0') AND (index < str'LENGTH)) LOOP + index := index + 1; + ch := str_copy(index); -- get_char + END LOOP; + -- if all zero's make sure that final zero remains + if ( (NOT Is_Digit(ch)) and (index > 1) and (str_copy(index - 1) = '0') ) then + index := index - 1; + ch := str_copy(index); + end if; + WHILE (true) LOOP + CASE state IS + WHEN 0 => IF (ch >= '0' AND ch <= '9') THEN -- to_digit + num := CHARACTER'POS(ch) - CHARACTER'POS('0'); + state := 1; + ELSIF (ch = '.') THEN + state := 2; + ELSE + state := 4; -- error + END IF; + + WHEN 1 => -- + IF (ch >= '0' AND ch <= '9') THEN + num := num * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); + state := 1; + ELSIF (ch = '.') THEN + state := 2; + ELSIF ((Is_White(ch)) OR (ch = NUL)) THEN + state := 3; + ELSE + state := 4; -- error + END IF; + + WHEN 2 => -- . state + IF (ch >= '0' AND ch <= '9') THEN + fract_num := fract_num * 10 + CHARACTER'POS(ch) + - CHARACTER'POS('0'); + power := power + 1; + state := 2; + + ELSIF ((Is_White(ch)) OR (ch = NUL)) THEN + state := 3; + ELSE + state := 6; -- error + END IF; + + WHEN 3 => -- space between time value and unit + IF ((Is_White(ch)) OR (ch=NUL)) THEN + state := 3; + ELSIF (ch >= 'A' AND ch <= 'Z') THEN + tu_indx := tu_indx + 1; + tu(tu_indx) := ch; + state := 5; + ELSE + state := 4; + END IF; + + WHEN 4 => -- error state + ASSERT false + REPORT " From_String --- invalid character encountered " + SEVERITY ERROR; + parse_err := TRUE; + EXIT; + + WHEN 5 => -- end state + IF ((ch >= 'A' AND ch <= 'Z') AND (tu_indx < 3)) THEN + tu_indx := tu_indx + 1; + tu(tu_indx) := ch; + state := 5; + ELSIF ( IS_White(ch) OR (tu_indx = 3) OR (ch=NUL)) THEN + exit; + ELSE + state := 4; + END IF; + WHEN OTHERS => ASSERT false + REPORT " From_String(time) --- time string in incorrect format" + SEVERITY ERROR; + parse_err := TRUE; + exit; + + END CASE; + index := index + 1; + EXIT when index > str'LENGTH; + ch := str_copy(index); + END LOOP; + + if (parse_err) then + return TIME'LEFT; + end if; + + IF (neg_sign) THEN + num := - num; + fract_num := - fract_num; + END IF; + -- this case statement decides the time unit. + CASE tu IS + + WHEN "FS " => + if (1 ns / 1000000) /= 0 ns then + fract_t := (fract_num * (1 ns / 1000000)) / (10 ** power); + result := (num * (1 ns / 1000000)) + fract_t; + else + if (1 ns / 1000) /= 0 ns then + result := num / 1000 * (1 ns / 1000); + else + result := num / 1000000 * 1 ns; + end if; + end if; + + + WHEN "PS " => + if ( 1 ns / 1000) /= 0 ns then + fract_t := (fract_num * (1 ns / 1000)) / (10 ** power); + result := (num * (1 ns / 1000)) + fract_t; + else + result := num / 1000 * 1 ns; + end if; + + WHEN "NS " => + fract_t := (fract_num * 1 NS) / (10 ** power); + result := (num * 1 NS) + fract_t; + WHEN "US " => + fract_t := (fract_num * 1 US) / (10 ** power); + + result := (num * 1 US) + fract_t; + + + WHEN "MS " => + fract_t := (fract_num * 1 MS) / (10 ** power); + result := (num * 1 MS) + fract_t; + + + WHEN "SEC" => + fract_t := (fract_num * 1 SEC) / (10 ** power); + result := (num * 1 SEC) + fract_t; + WHEN "MIN" => + fract_t := (fract_num * 1 MIN) / (10 ** power); + result := (num * 1 MIN) + fract_t; + WHEN "HR " => + fract_t := (fract_num * 1 HR) / (10 ** power); + result := (num * 1 HR) + fract_t; + + + WHEN OTHERS => + + ASSERT false + REPORT "From_String --- time base not specified or incorrectly specified" + SEVERITY ERROR; + + + return TIME'LEFT; + END CASE; + return result; + END From_String; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.7 +--| Overloading : None +--| +--| Purpose : Convert Time to a String. +--| +--| Parameters : +--| val - input, TIME, +--| +--| Result : STRING representation of TIME. +--| +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN TIME; + CONSTANT format : IN STRING := "" + ) RETURN STRING IS + + VARIABLE tbuf : STRING(max_string_len DOWNTO 1) ; -- implicitly == NUL + VARIABLE str_len : NATURAL; -- actual length of time string + VARIABLE rbuf : STRING(max_string_len DOWNTO 1); + VARIABLE result : string(1 TO max_string_len); + VARIABLE r_index : Natural := 0; + VARIABLE t_index : Natural := 0; + VARIABLE str_index : Natural := 0; + VARIABLE tval : TIME; + VARIABLE ival : INTEGER; + VARIABLE period_loc : NATURAL; + VARIABLE left_digits : NATURAL; + VARIABLE format_cpy : string(1 TO format'length) := format; + VARIABLE pr_actual : integer; -- actual precision + VARIABLE indx : integer; + VARIABLE fw : integer; -- field width + VARIABLE precis : integer; -- precision + VARIABLE justy : BIT := '0'; -- justification + VARIABLE tunit : time_unit_type; + VARIABLE suffix : STRING(1 TO 4); + VARIABLE neg_sign : BOOLEAN := false ; + BEGIN + + -- IF no format is specified then the result will be provided + -- in the dynamic default time unit. + IF (format = "") THEN + return(Default_Time(val)); + END IF; + -- handle sign + IF ( val < 0 ns ) THEN + neg_sign := NOT neg_sign; + tval := - val; + ELSE + tval := val; + END IF; + -- convert time to string without any format + -- by calling Time_String(). first determine the length + + str_index := 20; + + tbuf(str_index downto 1) := Time_String(tval); + + -- call procedure T-Machine to split format string into field width fw + -- precision, justification and desired time unit ( time unit in which + -- the result string is to be represented). + T_Machine(fw, precis, justy, tunit, format); + + -- determine the desired output time unit and insert the decimal point + -- at proper location in the string and save the result int rbuf. + CASE tunit is + + WHEN t_sec | t_min | t_hr => + period_loc := 16; + + rbuf(period_loc - 1 DOWNTO 1) := tbuf(period_loc -1 DOWNTO 1); + rbuf(period_loc) := '.'; + rbuf(str_index + 1 DOWNTO period_loc + 1) := + tbuf(str_index DOWNTO period_loc); + + suffix := " sec"; + + WHEN t_ms => + period_loc := 13; + + rbuf(period_loc - 1 DOWNTO 1) := tbuf(period_loc -1 DOWNTO 1); + rbuf(period_loc) := '.'; + rbuf(str_index + 1 DOWNTO period_loc + 1) := + tbuf(str_index DOWNTO period_loc); + + suffix := " ms "; + WHEN t_us => + period_loc := 10; + rbuf(period_loc - 1 DOWNTO 1) := tbuf(period_loc -1 DOWNTO 1); + rbuf(period_loc) := '.'; + rbuf(str_index + 1 DOWNTO period_loc + 1) := + tbuf(str_index DOWNTO period_loc); + suffix := " us "; + + WHEN t_ns => + period_loc := 7; + + rbuf(period_loc - 1 DOWNTO 1) := tbuf(period_loc -1 DOWNTO 1); + + rbuf(period_loc) := '.'; + rbuf(str_index + 1 DOWNTO period_loc + 1) := + tbuf(str_index DOWNTO period_loc); + suffix := " ns "; + + WHEN t_ps => + period_loc := 4; + + + rbuf(period_loc - 1 DOWNTO 1) := tbuf(period_loc -1 DOWNTO 1); + + rbuf(period_loc) := '.'; + rbuf(str_index + 1 DOWNTO period_loc + 1) := + tbuf(str_index DOWNTO period_loc); + + suffix := " ps "; + + WHEN t_fs => + period_loc := 1; + rbuf(period_loc) := '.'; + + rbuf(str_index + 1 DOWNTO period_loc + 1) := + tbuf(str_index DOWNTO period_loc); + + suffix := " fs "; + + WHEN OTHERS => null; + END CASE; + str_index := str_index + 1; -- to take care of decimal point + + -- kill leading zero's + Kill_ZERO : LOOP + EXIT Kill_ZERO WHEN (rbuf(str_index) /= '0'); + IF (rbuf(str_index) = '0') THEN + str_index := str_index - 1; + END IF; + END LOOP; + + -- keep one zero before the decimal point + IF (rbuf(str_index) = '.') THEN + str_index := str_index + 1; + rbuf(str_index) := '0'; + END IF; + + -- insert the negative sign if it exists + IF neg_sign THEN + str_index := str_index + 1; + rbuf(str_index) := '-'; + END IF; + + -- calculate the number of digits including negative sign in the + -- string to the left of decimal point + left_digits := str_index - period_loc; + IF (precis /= 0) THEN + str_len := left_digits + 1 + precis; + ELSE + str_len := left_digits; + END IF; + + -- copy rbuf to tbuf according to the desired format + -- first copy the precison part + -- check if precision > period_loc -1 + IF (precis > period_loc - 1) THEN + t_index := precis + 1; + FOR i IN period_loc downto 1 LOOP + tbuf(t_index) := rbuf(i); + t_index := t_index - 1; + END LOOP; + tbuf(t_index downto 1) := (OTHERS => '0'); + ELSIF (precis = period_loc - 1) THEN + tbuf(precis + 1 downto 1) := rbuf(period_loc downto 1); + ELSE -- copy as much portion you can + r_index := period_loc; + FOR i IN precis + 1 downto 1 LOOP + tbuf(i) := rbuf(r_index); + r_index := r_index - 1; + END LOOP; + END IF; + -- copy the part to the left of period + tbuf(str_len DOWNTO str_len - left_digits + 1) := + rbuf(str_index DOWNTO period_loc + 1); + + -- match the desired field width + -- ** was (fw > str_index) + IF (fw > str_len) THEN + case justy IS + WHEN '0' => -- right justification + tbuf(fw DOWNTO str_len + 1) := (OTHERS => ' '); + result( 1 TO fw) := tbuf(fw DOWNTO 1); + return (result(1 TO fw) & suffix); + WHEN '1' => + result( 1 TO str_len) := tbuf(str_len DOWNTO 1); + result(str_len + 1 TO str_len + 4) := suffix; + indx := str_len + 4; + for i IN fw - str_len DOWNTO 1 LOOP + indx := indx + 1; + result(indx) := ' '; + end LOOP; + return result(1 TO indx); + WHEN OTHERS => -- left justification + ASSERT NOT WarningsOn + report " To_String --- error in justification " + SEVERITY WARNING; + result(1 TO str_len) := tbuf(str_len DOWNTO 1); + return (result(1 TO str_len) & suffix); + end case; + ELSE -- fw is lessthan or equal to std_len + result(1 TO str_len) := tbuf(str_len DOWNTO 1); + return (result(1 TO str_len) & suffix); + END IF; + -- That's all + END To_String; +-- +-- end of the std_iopak body +END std_iopak; diff --git a/src/hdl/pkg/iopakp.vhd b/src/hdl/pkg/iopakp.vhd new file mode 100644 index 0000000..9542fde --- /dev/null +++ b/src/hdl/pkg/iopakp.vhd @@ -0,0 +1,2596 @@ +-- ---------------------------------------------------------------------------- +-- +-- Copyright (c) Mentor Graphics Corporation, 1982-1996, All Rights Reserved. +-- UNPUBLISHED, LICENSED SOFTWARE. +-- CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE +-- PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS. +-- +-- +-- PackageName : std_iopak +-- Title : Package for STD_IOPAK +-- Purpose : This package contains additional support for +-- : performing text IO. +-- : +-- Comments : +-- : +-- Assumptions : none +-- Limitations : none +-- Known Errors: none +-- ---------------------------------------------------------------------------- +-- >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<< +-- ---------------------------------------------------------------------------- +-- Mentor Graphics Corporation owns the sole copyright to this software. +-- Under International Copyright laws you (1) may not make a copy of this +-- software except for the purposes of maintaining a single archive copy, +-- (2) may not derive works herefrom, (3) may not distribute this work to +-- others. These rights are provided for information clarification, +-- other restrictions of rights may apply as well. +-- +-- This is an "Unpublished" work. +-- ---------------------------------------------------------------------------- +-- >>>>>>>>>>>>>>>>>>>>>>> License NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<< +-- ---------------------------------------------------------------------------- +-- This software is further protected by specific source code and/or +-- object code licenses provided by Mentor Graphics Corporation. Use of this +-- software other than as provided in the licensing agreement constitues +-- an infringement. No modification or waiver of any right(s) shall be +-- given other than by the written authorization of an officer of The +-- Mentor Graphics Corporation. +-- ---------------------------------------------------------------------------- +-- >>>>>>>>>>>>>>>>>>>>>>> Proprietary Information <<<<<<<<<<<<<<<<<<<< +-- ---------------------------------------------------------------------------- +-- This source code contains proprietary information of Mentor Graphics +-- Corporation and shall not be disclosed other than as provided in the software +-- licensing agreement. +-- ---------------------------------------------------------------------------- +-- >>>>>>>>>>>>>>>>>>>>>>>>>>>>> Warrantee <<<<<<<<<<<<<<<<<<<<<<<<<<<< +-- ---------------------------------------------------------------------------- +-- Mentor Graphics Corporation MAKES NO WARRANTY OF ANY KIND WITH REGARD TO +-- THE USE OF THIS SOFTWARE, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS +-- FOR A PARTICULAR PURPOSE. +-- ---------------------------------------------------------------------------- +-- Modification History : +-- ---------------------------------------------------------------------------- +-- Version No: | Author: | Mod. Date: | Changes Made: +-- v1.000 | M.K.Dhodhi | 10/26/91 | Production Release +-- v1.100 | M.K.Dhodhi | 11/19/91 | Compatible w/ vantage 3.650 Release +-- v1.110 | wdb | 01/27/92 | compatible w/Intermetrics +-- v1.111 | M.K.Dhodhi | 02/13/92 | fixing bug in T0_String input time +-- | fixing comment in SOX_Machine +-- v1.111 | M.K.Dhodhi | 03/06/92 | production release +-- v1.200 | M.K.Dhodhi | 04/21/92 | stand alone version +-- v1.300 | M.K.Dhodhi | 08/03/92 | production release +-- v1.140 | M.K.Dhodhi | 11/05/92 | fixing real 0.0 case for To_String +-- | | and an extra loop in default time. +-- v1.150 | M.K.Dhodhi | 11/17/92 | extending fscan upto 20 arguments. +-- | fixing default 0 time. +-- v1.160 | M.K.Dhodhi | 02/11/93 | Fixing Find_char +-- v1.700 B | W.R. Migatz | 05/03/93 | Beta release - changes to all f routines (not fprint) +-- | modified str*cpy and str*cmp +-- | fixed memory leak +-- v1.700 | W.R. Migatz | 05/25/93 | production release - change to fscan with %t to allow time unit +-- v1.800 | W.R. Migatz | 07/28/93 | combining into 1 file, mentor support, and From_String(time) bug fix +-- v2.000 | W.R. Migatz | 07/21/94 | production release - fix bug in fprint, fs ps ns timing changes +-- v2.100 | W.R. Migatz | 01/10/96 | production release +-- | Initialization banner removed +-- v2.110 | W.R. Migatz | 04/02/96 | Fixed Find_Char and To_String(TIME) bugs +-- | Find_char did not stop at a NUL character +-- | To_String(TIME) did not handle a precision of 0 +-- v2.2 | B. Caslis | 07/25/96 | Updated for Mentor Graphics Release +-- ---------------------------------------------------------------------------- + +Library ieee; +Use ieee.std_logic_1164.all; -- Reference the STD_Logic system +Use STD.TEXTIO.all; + +PACKAGE std_iopak is + + -- ************************************************************************ + -- Display Banner + -- ************************************************************************ + CONSTANT StdIOpakBanner : BOOLEAN; + + + + TYPE ASCII_TEXT IS file of CHARACTER; + + TYPE time_unit_type is (t_fs, t_ps, t_ns, t_us, t_ms, t_sec, t_min, t_hr); + + CONSTANT max_token_len : INTEGER := 32; + CONSTANT max_string_len : INTEGER := 256; + CONSTANT END_OF_LINE_MARKER : STRING(1 TO 2); + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a boolean. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : A boolean true or false. +--| +--| NOTE : +--| +--| Use : +--| VARIABLE s_flag : String(1 TO 5) := " TRUE"; +--| VARIABLE good : BOOLEAN +--| +--| good := From_String (s_flag); +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN boolean; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a bit. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : bit. +--| +--| NOTE : +--| +--| Use : +--| VARIABLE b_val : bit; +--| +--| b_val := From_String (" 100"); +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN bit; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a Severity_Level. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : Severity_Level +--| +--| NOTE : +--| +--| Use : +--| VARIABLE str10 : String(1 TO 10) := " WARNING"; +--| VARIABLE sev : severity_level; +--| +--| sev := From_String (str10); +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN severity_level; +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a character. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : Character +--| +--| NOTE : +--| +--| Use : +--| VARIABLE str10 : String(1 TO 10) := "WARNING "; +--| VARIABLE ch : character; +--| +--| ch := From_String (str10); +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN character; +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to an Integer. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : Integer +--| +--| NOTE : +--| +--| Use : +--| VARIABLE n : Integer; +--| +--| n := From_String ("32 56"); +--| This statement will set n to integer 32. +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN INTEGER; +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a real. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : real value +--| +--| NOTE : +--| +--| Use : +--| VARIABLE n : real ; +--| +--| n := From_String (" -354.78"); +--| This statement will set n to real value -354.78. +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN REAL; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to an std_ulogic. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : std_ulogic +--| +--| NOTE : +--| +--| Use : +--| VARIABLE u_val : std_ulogic ; +--| +--| u_val := From_String (" 100"); +--| This statement will set u_val equal to the value '1'. +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN std_ulogic; +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to an std_ulogic_vector. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : std_ulogic_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE u_vector : std_ulogic_vector( 7 DOWNTO 0) ; +--| +--| u_vector := From_String (" 0-ZU1010 1010"); +--| This statement will set u_vector equal to "0-ZU1010". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN std_ulogic_vector; + +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to an std_logic_vector. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : std_logic_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE logic_vect : std_logic_vector( 7 DOWNTO 0) ; +--| +--| logic_vect := From_String (" 0-ZU1010 1010"); +--| This statement will set logic_vect equal to "0-ZU1010". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN std_logic_vector; + +--+----------------------------------------------------------------------------- +--| Function Name : From_BinString +--| +--| Overloading : None +--| +--| Purpose : Convert from a Binary String to a bit_vector. +--| +--| Parameters : +--| str - input , binary string to be converted, +--| +--| Result : bit_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE b_vect : bit_vector( 7 DOWNTO 0) ; +--| +--| b_vect := From_BinString (" 01101111 1010"); +--| This statement will set b_vect equal to "01101111". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_BinString ( CONSTANT str : IN STRING + ) RETURN bit_vector; +--+----------------------------------------------------------------------------- +--| Function Name : From_OctString +--| +--| Overloading : None +--| +--| Purpose : Convert from an Octal String to a bit_vector. +--| +--| Parameters : +--| str - input , Octal string to be converted, +--| +--| Result : bit_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE b_vect : bit_vector( 15 DOWNTO 4) ; +--| +--| b_vect := From_OctString (" 1735 1010"); +--| This statement will set b_vect equal to "001111011101". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_OctString ( CONSTANT str : IN STRING + ) RETURN bit_vector; +--+----------------------------------------------------------------------------- +--| Function Name : From_HexString +--| +--| Overloading : None +--| +--| Purpose : Convert from a Hex String to a bit_vector. +--| +--| Parameters : +--| str - input , Hex string to be converted, +--| +--| Result : bit_vector +--| +--| NOTE : +--| +--| Use : +--| VARIABLE b_vect : bit_vector( 15 DOWNTO 4) ; +--| +--| b_vect := From_HexString (" 3DD 1010"); +--| This statement will set b_vect equal to "001111011101". +--| +--|----------------------------------------------------------------------------- + FUNCTION From_HexString ( CONSTANT str : IN STRING + ) RETURN bit_vector; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.1 +--| Overloading : None +--| +--| Purpose : Convert a boolean to a String. +--| +--| Parameters : +--| val - input value, BOOLEAN, +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of a boolean. +--| +--| NOTE : +--| Default is right justified +--| +--| Use : +--| VARIABLE s_flag : String(1 TO 5); +--| VARIABLE good : BOOLEAN := TRUE; +--| +--| s_flag := To_String ( good, "%5s" ); +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN BOOLEAN; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.2 +--| Overloading : None +--| +--| Purpose : Convert a bit Value to a String. +--| +--| Parameters : +--| val - input bit. +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of a bit. +--| +--| +--| Use : +--| VARIABLE bit_string : String(1 TO 5); +--| +--| bit_string := To_String ( '1', "%1s"); +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN BIT; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.3 +--| Overloading : None +--| +--| Purpose : Convert a Character to a String. +--| +--| Parameters : +--| val - input character. +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Note : This function allows to see the non-printable characters. +--| +--| Result : STRING representation of a character. +--| +--| +--| Use : +--| VARIABLE ascii_char : String(1 TO 5); +--| +--| ascii_char := To_String ( d, "%3s"); +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN CHARACTER; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.4 +--| Overloading : None +--| +--| Purpose : Convert a severity-level to a string. +--| +--| Parameters : +--| val - input severity-level. +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of a severity-level. +--| +--| Use : +--| VARIABLE s_level : String(1 TO 7); +--| VARIABLE message : SEVERITY_LEVEL := NOTE; +--| +--| s_level := To_String (message, "%7s"); +--|------------------------------------------------------------------ + FUNCTION To_String ( CONSTANT val : IN SEVERITY_LEVEL; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.5 +--| Overloading : None +--| +--| Purpose : Convert an integer into a String according +--| format specification. +--| +--| Parameters : +--| val - input value, INTEGER, +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of an integer. +--| +--| NOTE : Format string has same meaning a in C language. +--| That if format is "%d " will convert an integer to +--| a string of length equal to number of digits in the +--| given inetger argument. While "%10d " return +--| a string of length 10 and if the number of digits +--| in the integer are less than 10 it will pad the +--| string with blank on the left because default +--| justification is right. if number of digits are +--| larger than 10 it will return 10 leftmost digits. +--| +--| +--| +--| USE : +--| VARIABLE str : STRING(1 TO 10); +--| VARIABLE val : INTEGER := 2750; +--| +--| str := TO_String(val, "%10d"), +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN INTEGER; + CONSTANT format : IN STRING := "%d" + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.6 +--| Overloading : None +--| +--| Purpose : Convert a real number to a String. +--| +--| Parameters : +--| val - input value, REAL, +--| format - input STRING, provides the +--| conversion specifications. +--| +--| Result : STRING representation of a real number. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 10); +--| VARIABLE val : REAL := 67.560 +--| +--| str := TO_String(val, "%10.3f"), +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN REAL; + CONSTANT format : IN STRING :="%f" + ) RETURN STRING; + +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.8 +--| Overloading : None +--| +--| Purpose : Convert a bit_vector to a String. +--| +--| Parameters : +--| val - input, BIT_VECTOR, +--| +--| Result : STRING representation of a bit_vector. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 16); +--| VARIABLE vect : BIT_VECTOR (7 DOWNTO 0); +--| +--| str := TO_String(vect, "%16s"), +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN BIT_VECTOR; + CONSTANT format : IN STRING :="%s" + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.10.2 +--| Overloading : None +--| +--| Purpose : Convert an std_ulogic to a String. +--| +--| Parameters : +--| val - input std_ulogic. +--| +--| Result : STRING representation of std_ulogic. +--| +--| Use : +--| VARIABLE str_ovf : STRING(1 TO 4); +--| VARIABLE overflow : std_ulogic; +--| +--| str_ovf := TO_String(vect, "%4s"), +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN std_ulogic; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| +--| Overloading : None +--| +--| Purpose : Convert an std_logic_vector to a String. +--| +--| Parameters : +--| val - input std_logic_vector. +--| +--| Result : STRING representation of std_logic_vector. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 16); +--| VARIABLE vect : std_logic_vector (7 DOWNTO 0); +--| +--| str := TO_String(vect, "%16s"), +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN std_logic_vector; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| +--| Overloading : None +--| +--| Purpose : Convert an std_ulogic_vector to a String. +--| +--| Parameters : +--| val - input std_ulogic_vector. +--| +--| Result : STRING representation of std_ulogic_vector. +--| +--| USE : +--| VARIABLE str : STRING(1 TO 16); +--| VARIABLE vect : std_ulogic_vector (7 DOWNTO 0); +--| +--| str := TO_String(vect, "%16s"), +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN std_ulogic_vector; + CONSTANT format : IN STRING := "%s" + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : Is_Alpha +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is a letter of the alphabet. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is a letter of the +--| alphabet, false otherwise. +--| +--| +--| Use : +--| +--| See Also : Is_Digit, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION Is_Alpha ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN; +--+----------------------------------------------------------------------------- +--| Function Name : Is_Upper +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is an upper case letter. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is an upper case letter of +--| the alphabet, false otherwise. +--| +--| +--| See Also : Is_Digit, Is_Alpha, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION Is_Upper ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN; +--+----------------------------------------------------------------------------- +--| Function Name : Is_Lower +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is a lower case letter. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is a lower case letter of +--| the alphabet, false otherwise. +--| +--| +--| See Also : Is_Digit, Is_Upper, Is_Alpha +--|----------------------------------------------------------------------------- + FUNCTION Is_Lower ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN; +--+----------------------------------------------------------------------------- +--| Function Name : Is_Digit +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is a digit 0-9. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is a digit, false +--| otherwise. +--| +--| +--| See Also : Is_Alpha, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION Is_Digit ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN; +--+----------------------------------------------------------------------------- +--| Function Name : Is_Space +--| 1. +--| Overloading : None +--| +--| Purpose : Test whether a character is a blank, tab or newline. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : True if the argument c is a blank or tab(HT), +--| false otherwise. +--| +--| +--| See Also : Is_Digit, Is_Upper, Is_Lower, Is_Alpha +--|----------------------------------------------------------------------------- + FUNCTION Is_Space ( CONSTANT c : IN CHARACTER + ) RETURN BOOLEAN; +--+----------------------------------------------------------------------------- +--| Function Name : To_Upper +--| 1. +--| Overloading : None +--| +--| Purpose :Convert a character to upper case. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : Character converted to upper case. +--| +--| +--| See Also : To_Lower, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION To_Upper ( CONSTANT c : IN CHARACTER + ) RETURN CHARACTER; +--+----------------------------------------------------------------------------- +--| Function Name : To_Upper +--| 1. +--| Overloading : None +--| +--| Purpose :Convert a string to upper case. +--| +--| Parameters : +--| val - input, string to be converted +--| +--| Result : string . +--| +--| +--| See Also : To_Lower, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION To_Upper ( CONSTANT val : IN String + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : To_Lower +--| 1. +--| Overloading : None +--| +--| Purpose : Convert a Character to lower case. +--| +--| Parameters : +--| c - input Character. +--| +--| Result : Character converted to lower case. +--| +--| See Also : To_Upper, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION To_Lower ( CONSTANT c : IN CHARACTER + ) RETURN CHARACTER; +--+----------------------------------------------------------------------------- +--| Function Name : To_Lower +--| 1. +--| Overloading : None +--| +--| Purpose : Convert a String to lower case. +--| +--| Parameters : +--| val - input string to be converted. +--| +--| Result : string +--| +--| See Also : To_Upper, Is_Upper, Is_Lower +--|----------------------------------------------------------------------------- + FUNCTION To_Lower ( CONSTANT val : IN STRING + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : StrCat +--| 1.2.1 +--| Overloading : None +--| +--| Purpose : Concatenate two string. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| +--| Result : Concatenated string. +--| +--|----------------------------------------------------------------------------- + FUNCTION StrCat ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : StrNCat +--| 1.2.2 +--| Overloading : None +--| +--| Purpose : Concatenate upto n characters of r_string to l_string. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| +--| Result : Concatenated string. +--| +--|----------------------------------------------------------------------------- + FUNCTION StrNCat ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING; + CONSTANT n : INTEGER + ) RETURN STRING; +--+----------------------------------------------------------------------------- +--| Function Name : StrCpy +--| 1.2.3 +--| Overloading : None +--| +--| Purpose : Copy r_string to l_string. +--| +--| Parameters : +--| l_str - output, STRING, target string +--| r_str - input, STRING, source string +--| +--| Result : +--| +--| NOTE : If the length of target string is greater than +--| the source string, then target string is padded +--| with space characters on the right side and when +--| the length of target string is shorter than the +--| length of source string only left most characters +--| of the source string will be be copied to the target. +--| +--| +--| USE : +--| Variable s1: string(1 TO 8); +--| +--| StrCpy(s1, "123456789A"); +--| s1 will hold "12345678" +--|----------------------------------------------------------------------------- + PROCEDURE StrCpy ( VARIABLE l_str : OUT STRING; + CONSTANT r_str : IN STRING + ); +--+----------------------------------------------------------------------------- +--| Function Name : StrNCpy +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : Copy at most n characters of r_string to l_string. +--| +--| Parameters : +--| l_str - output, STRING, target +--| r_str - input, STRING, source +--| n - input, Natural, number of characters to +--| to be copied. +--| +--| Result : l_string holds the result. +--| +--| NOTE : If n is less than or equal to zero then a srting +--| filled with blanks is returned. +--| +--| +--|----------------------------------------------------------------------------- + PROCEDURE StrNCpy ( VARIABLE l_str : OUT STRING; + CONSTANT r_str : IN STRING; + CONSTANT n : IN NATURAL + ); +--+----------------------------------------------------------------------------- +--| Function Name : StrCmp +--| +--| Overloading : None +--| +--| Purpose : Compare left input string to right input string. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| +--| Result : INTEGER, returns an integer less than 0 if the left string +--| is less than the right string, returns integer 0 if the +--| the string are equal and returns an integer greater than +--| 0 if the left string is greater than the right string. +--| +--| +--|----------------------------------------------------------------------------- + FUNCTION StrCmp ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING + ) RETURN INTEGER; +--+----------------------------------------------------------------------------- +--| Function Name : StrNCmp +--| +--| Overloading : None +--| +--| Purpose : Compare at most n characters of left input string +--| to right input string. Returns an Integer. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| n - input, Natural, +--| +--| Result : Returns an integer less than 0 if left_most n +--| characters of the left string is less than the +--| right string, returns integer 0 if both strings +--| are equal, and returns an integer greater than 0 +--| if the left string is greater than the right string. +--| +--|----------------------------------------------------------------------------- + FUNCTION StrNCmp ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING; + CONSTANT n : IN Natural + ) RETURN INTEGER; +--+----------------------------------------------------------------------------- +--| Function Name : StrNcCmp +--| +--| Overloading : None +--| +--| Purpose : Compare to strings and determine whether left input +--| string is less than, equal to or greater than right +--| input string. The comparison is Not case sensitive. +--| +--| Parameters : +--| l_str - input, STRING, +--| r_str - input, STRING, +--| +--| Result : Returns an integer less than 0 if left_most n +--| characters of the left string is less than the +--| right string, returns integer 0 if both strings +--| are equal, and returns an integer greater than 0 +--| if the left string is greater than the right string. +--| +--|----------------------------------------------------------------------------- + FUNCTION StrNcCmp ( CONSTANT l_str : IN STRING; + CONSTANT r_str : IN STRING + ) RETURN INTEGER; +--+----------------------------------------------------------------------------- +--| Function Name : StrLen +--| +--| Overloading : None +--| +--| Purpose : Returns length of a string. +--| +--| Parameters : +--| l_str - input, STRING, +--| +--| Result : Natural +--| +--| NOTE : +--| This is in fact same as String'LENGTH provided +--| by VHDL. +--| +--| +--|----------------------------------------------------------------------------- + FUNCTION StrLen ( CONSTANT l_str : IN STRING + ) RETURN NATURAL; + +--+----------------------------------------------------------------------------- +--| Function Name :Copyfile +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : Copy one ASCII_TEXT file to an other ASCII_TEXT file. +--| +--| Parameters : +--| in_fptr -- input, ASCII_TEXT, source file +--| out_fptr -- output, ASCII_TEXT, destination file +--| +--| NOTE : +--| +--| USE : +--| file romdata : ASCII_TEXT IS IN "NEW_ROM.dat"; +--| file dest_file : ASCII_TEXT IS OUT "SAVE_ROM.dat"; +--| +--| Copyfile(romdata, dest_file); +--|----------------------------------------------------------------------------- + PROCEDURE Copyfile ( VARIABLE in_fptr : IN ASCII_TEXT; + VARIABLE out_fptr : OUT ASCII_TEXT + ); + +--+----------------------------------------------------------------------------- +--| Function Name :Copyfile +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : Copy one TEXT file to an other TEXT file. +--| +--| Parameters : +--| in_fptr -- input, TEXT, +--| out_fptr -- output, TEXT +--| +--| NOTE : +--| This is combination of READLINE() and WRITELINE() +--| procedures provided in the standard +--| TEXTIO package. +--| +--| USE : +--| file in_f : TEXT IS IN "data_in"; +--| file out_f : TEXT IS OUT "save_data"; +--| +--| Copyfile(in_f, out_f); +--|----------------------------------------------------------------------------- + PROCEDURE Copyfile ( VARIABLE in_fptr : IN TEXT; + VARIABLE out_fptr : OUT TEXT + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fprint +--| 1.2.1 +--| Overloading : None +--| +--| Purpose : Convert up to 10 arguments to a file according to +--| the format specifications give by a format string. +--| +--| Parameters : +--| file_ptr - output ASCII_TEXT, destination file +--| format - input STRING, format control specifications. +--| arg1 - input STRING, +--| arg2 - input STRING, +--| arg3 - input STRING, +--| arg4 - input STRING, +--| arg5 - input STRING, +--| arg6 - input STRING, +--| arg7 - input STRING, +--| arg8 - input STRING, +--| arg9 - input STRING, +--| arg10 - input STRING +--| +--| Result : formated TEXT. +--| +--| Note: This procedure provides formated output +--| of upto 10 arguments. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fprint ( VARIABLE file_ptr : OUT ASCII_TEXT; + CONSTANT format : IN STRING; + CONSTANT arg1 : IN STRING := ""; + CONSTANT arg2 : IN STRING := ""; + CONSTANT arg3 : IN STRING := ""; + CONSTANT arg4 : IN STRING := ""; + CONSTANT arg5 : IN STRING := ""; + CONSTANT arg6 : IN STRING := ""; + CONSTANT arg7 : IN STRING := ""; + CONSTANT arg8 : IN STRING := ""; + CONSTANT arg9 : IN STRING := ""; + CONSTANT arg10 : IN STRING := "" + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fprint +--| 1.2.1 +--| Overloading : None +--| +--| Purpose : Print up to 10 arguments to a file according to +--| the specifications given by a format string. +--| +--| Parameters : +--| file_ptr - output TEXT, destination file +--| line_ptr - INOUT LINE, pointer to a string. +--| format - input STRING, format control specifications. +--| arg1 - input STRING, +--| arg2 - input STRING, +--| arg3 - input STRING, +--| arg4 - input STRING, +--| arg5 - input STRING, +--| arg6 - input STRING, +--| arg7 - input STRING, +--| arg8 - input STRING, +--| arg9 - input STRING, +--| arg10 - input STRING +--| +--| Result : formated TEXT. +--| +--| Note: This procedure provides formated output +--| of upto 10 arguments. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fprint ( VARIABLE file_ptr : OUT TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + CONSTANT arg1 : IN STRING := ""; + CONSTANT arg2 : IN STRING := ""; + CONSTANT arg3 : IN STRING := ""; + CONSTANT arg4 : IN STRING := ""; + CONSTANT arg5 : IN STRING := ""; + CONSTANT arg6 : IN STRING := ""; + CONSTANT arg7 : IN STRING := ""; + CONSTANT arg8 : IN STRING := ""; + CONSTANT arg9 : IN STRING := ""; + CONSTANT arg10 : IN STRING := "" + ); +--+----------------------------------------------------------------------------- +--| Function Name : fprint +--| 1.2.2 +--| Overloading : None +--| +--| Purpose : Print up to 10 arguments to a string buffer according to +--| the specifications given by a format string. +--| +--| Parameters : +--| string_buf - output STRING, +--| format - input STRING +--| arg1 - input STRING, +--| arg2 - input STRING, +--| arg3 - input STRING, +--| arg4 - input STRING, +--| arg5 - input STRING, +--| arg6 - input STRING, +--| arg7 - input STRING, +--| arg8 - input STRING, +--| arg9 - input STRING, +--| arg10 - input STRING +--| +--| Result : STRING representation of arguments. +--| +--| Note: This procedure provides formated output +--| of upto 10 arguments. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fprint ( VARIABLE string_buf : OUT STRING; + CONSTANT format : IN STRING; + CONSTANT arg1 : IN STRING := ""; + CONSTANT arg2 : IN STRING := ""; + CONSTANT arg3 : IN STRING := ""; + CONSTANT arg4 : IN STRING := ""; + CONSTANT arg5 : IN STRING := ""; + CONSTANT arg6 : IN STRING := ""; + CONSTANT arg7 : IN STRING := ""; + CONSTANT arg8 : IN STRING := ""; + CONSTANT arg9 : IN STRING := ""; + CONSTANT arg10 : IN STRING := "" + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fscan +--| +--| Overloading : None +--| +--| Purpose : To read text from a file according to specifications +--| given by a format string and save the results into +--| the corresponding arguments. +--| +--| Parameters : +--| file_ptr - input ASCII_TEXT, input file +--| format - input STRING, format control specifications. +--| arg1 - output STRING, +--| arg2 - output STRING, +--| arg3 - output STRING, +--| arg4 - output STRING, +--| arg5 - output STRING, +--| arg6 - output STRING, +--| arg7 - output STRING, +--| arg8 - output STRING, +--| arg9 - output STRING, +--| arg10 - output STRING +--| arg11 - output STRING, +--| arg12 - output STRING, +--| arg13 - output STRING, +--| arg14 - output STRING, +--| arg15 - output STRING, +--| arg16 - output STRING, +--| arg17 - output STRING, +--| arg18 - output STRING, +--| arg19 - output STRING, +--| arg20 - output STRING, +--| arg_count - number of arguments passed to fscan +--| +--| Result : STRING representation of given text. +--| +--| +--| Note: This procedure extracts upto twenty arguments +--| from a line in a file. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING; + VARIABLE arg19 : OUT STRING; + VARIABLE arg20 : OUT STRING; + CONSTANT arg_count : IN INTEGER := 20 + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING; + VARIABLE arg19 : OUT STRING + ); +--|----------------------------------------------------------------------------- + + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING + ); +--|----------------------------------------------------------------------------- + + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING + ); +--|----------------------------------------------------------------------------- + + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN ASCII_TEXT; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fscan +--| 1.2.3 +--| Overloading : None +--| +--| Purpose : To read text from a file according to specifications +--| given by the format string and save the results into +--| the corresponding arguments. +--| +--| Parameters : +--| file_ptr - input TEXT, +--| line_ptr - input_output LINE, +--| format - input STRING, +--| arg1 - output STRING, +--| arg2 - output STRING, +--| arg3 - output STRING, +--| arg4 - output STRING, +--| arg5 - output STRING, +--| arg6 - output STRING, +--| arg7 - output STRING, +--| arg8 - output STRING, +--| arg9 - output STRING, +--| arg10 - output STRING +--| arg11 - output STRING, +--| arg12 - output STRING, +--| arg13 - output STRING, +--| arg14 - output STRING, +--| arg15 - output STRING, +--| arg16 - output STRING, +--| arg17 - output STRING, +--| arg18 - output STRING, +--| arg19 - output STRING, +--| arg20 - output STRING, +--| arg_count - input INTEGER +--| +--| Result : STRING representation of given text. +--| +--| Algorithm : +--| Read a line from the file into variable l ( which is aline). +--| split the format string into small tokens consisting of +--| printable characters and control format. +--| depending on control format read from l. Read an other line +--| from the file when length of l has become zero. and format +--| +--| +--| Note: This procedure extracts upto twenty arguments +--| from a line in a file. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING; + VARIABLE arg19 : OUT STRING; + VARIABLE arg20 : OUT STRING; + CONSTANT arg_count : IN INTEGER := 20 + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING; + VARIABLE arg19 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( VARIABLE file_ptr : IN TEXT; + VARIABLE line_ptr : INOUT LINE; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fscan +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To read text from a string buffer according to +--| specifications given by a format string and save +--| the result into corresponding arguments. +--| +--| Parameters : +--| string_buf - input String, +--| format - input STRING, +--| arg1 - output STRING, +--| arg2 - output STRING, +--| arg3 - output STRING, +--| arg4 - output STRING, +--| arg5 - output STRING, +--| arg6 - output STRING, +--| arg7 - output STRING, +--| arg8 - output STRING, +--| arg9 - output STRING, +--| arg10 - output STRING +--| arg11 - output STRING, +--| arg12 - output STRING, +--| arg13 - output STRING, +--| arg14 - output STRING, +--| arg15 - output STRING, +--| arg16 - output STRING, +--| arg17 - output STRING, +--| arg18 - output STRING, +--| arg19 - output STRING, +--| arg20 - output STRING, +--| arg_count - input INTEGER - the number of arguments passed to fscan +--| +--| Result : STRING representation given TEXT. +--| +--| Note: This procedure extracts upto twenty arguments +--| from a string buffer. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING; + VARIABLE arg19 : OUT STRING; + VARIABLE arg20 : OUT STRING; + CONSTANT arg_count : IN INTEGER := 20 + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING; + VARIABLE arg19 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING; + VARIABLE arg18 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING; + VARIABLE arg17 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING; + VARIABLE arg16 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING; + VARIABLE arg15 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING; + VARIABLE arg14 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING; + VARIABLE arg13 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING; + VARIABLE arg12 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING; + VARIABLE arg11 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING; + VARIABLE arg2 : OUT STRING; + VARIABLE arg3 : OUT STRING; + VARIABLE arg4 : OUT STRING; + VARIABLE arg5 : OUT STRING; + VARIABLE arg6 : OUT STRING; + VARIABLE arg7 : OUT STRING; + VARIABLE arg8 : OUT STRING; + VARIABLE arg9 : OUT STRING; + VARIABLE arg10 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING ; + VARIABLE arg9 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING ; + VARIABLE arg8 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING ; + VARIABLE arg7 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING ; + VARIABLE arg6 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING ; + VARIABLE arg5 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING ; + VARIABLE arg4 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING ; + VARIABLE arg3 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING ; + VARIABLE arg2 : OUT STRING + ); +--|----------------------------------------------------------------------------- + PROCEDURE fscan ( CONSTANT string_buf : IN STRING; + CONSTANT format : IN STRING; + VARIABLE arg1 : OUT STRING + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fgetc +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To read the next character from a file of type +--| ASCII_TEXT. +--| +--| Parameters : +--| stream - input ASCII_TEXT, +--| +--| Result : Returns the ordinate value of the character read. If +--| end of file is reached then return - 1 +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| USE: : +--| VARIABLE n : Integer; +--| FILE f_in : ASCII_TEXT IS IN "design.doc"; +--| +--| fgetc(n, f_in); +--| +--| Will return ordinal value of character in integer n +--|----------------------------------------------------------------------------- + PROCEDURE fgetc ( VARIABLE result : OUT INTEGER; + VARIABLE stream : IN ASCII_TEXT + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fgetc +--| +--| Overloading : None +--| +--| Purpose : To read the next character from a file of type TEXT. +--| +--| Parameters : +--| stream - input TEXT, +--| ptr - INOUT, LINE +--| Result :Integer, the ordinate value of the character being read. +--| -1 when end of file (EOF). +--| +--| Note: : The TEXT is defined in the package TEXTIO to be +--| a file of string. +--| +--| USE: : +--| VARIABLE n : Integer; +--| FILE f_in : TEXT IS IN "design.doc"; +--| +--| fgetc(n, f_in); +--| +--| Will return ordinal value of character in integer n +--|----------------------------------------------------------------------------- + PROCEDURE fgetc ( VARIABLE result : OUT INTEGER; + VARIABLE stream : IN TEXT; + VARIABLE ptr : INOUT LINE + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fgets +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To read, at most, the next n characters from a file +--| of type ASCII_TEXT and save them to a string. +--| +--| Parameters : +--| l_str -- output, STRING, +--| +--| n -- input, Natural, number of +--| characters to be read. +--| stream -- input, ASCII_TEXT, input file. +--| +--| result : string +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| USE: : +--| VARIABLE str_buf : string(1 TO 100); +--| FILE f_in : ASCII_TEXT IS IN "design.doc"; +--| +--| fgets(str_buf, 50, f_in); +--| +--| Will read in at most 50 characters from the file +--| design.doc and place them in str_buf. +--|----------------------------------------------------------------------------- + PROCEDURE fgets ( VARIABLE l_str : OUT STRING; + CONSTANT n : IN NATURAL; + VARIABLE stream : IN ASCII_TEXT + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fgets +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To read, at most, the next n characters from a file +--| of type TEXT and save them to a string. +--| +--| Parameters : +--| l_str -- output, STRING, +--| n -- input, Natural, number of +--| characters to be read. +--| stream -- input, TEXT, input file. +--| line_ptr -- inout LINE, +--| +--| result : string +--| +--| Note: : The TEXT is defined in the package TEXTIO to be +--| a file of string. +--| +--| USE: : +--| VARIABLE str_buf : string(1 TO 100); +--| FILE f_in : TEXT IS IN "design.doc"; +--| +--| fgets(str_buf, 50, f_in); +--| +--| Will read in at most 50 characters from the file +--| design.doc and place them in str_buf. +--|----------------------------------------------------------------------------- + PROCEDURE fgets ( VARIABLE l_str : OUT STRING; + CONSTANT n : IN NATURAL; + VARIABLE stream : IN TEXT; + VARIABLE line_ptr : INOUT LINE + ); + +--+--------------------------------------------------------------------------- +--| Function Name : fgetline +--| +--| Overloading : None +--| +--| Purpose : To read a line from the input ASCII_TEXT file and +--| save into a string. +--| +--| Parameters : +--| l_str -- output, STRING, +--| stream -- input, ASCII_TEXT, input file +--| +--| result : string. +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| USE: : +--| VARIABLE line_buf : string(1 TO 256); +--| FILE in_file : ASCII_TEXT IS IN "file_ascii_in.dat"; +--| +--| fgetline(line_buf, in_file); +--| +--| Will read a line from the file +--| file_ascii_in.dat and place into line_buf. +--|----------------------------------------------------------------------------- + PROCEDURE fgetline ( VARIABLE l_str : OUT STRING; + VARIABLE stream : IN ASCII_TEXT + ); + +--+--------------------------------------------------------------------------- +--| Function Name : fgetline +--| +--| Overloading : None +--| +--| Purpose : To read a line from the input TEXT file and +--| save into a string. +--| +--| Parameters : +--| l_str -- output, STRING, +--| stream -- input, TEXT, input file +--| +--| result : string. +--| +--| Note: : The TEXT is defined in the package TEXTIO to be +--| a file of string. +--| USE: : +--| VARIABLE line_buf : string(1 TO 256); +--| FILE in_file : TEXT IS IN "file_text_in.dat"; +--| +--| fgetline(line_buf, in_file); +--| +--| Will read a line from the file +--| file_text_in.dat and place into line_buf. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fgetline ( VARIABLE l_str : OUT STRING; + VARIABLE stream : IN TEXT; + VARIABLE line_ptr : INOUT LINE + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fputc +--| 1.2.4 +--| Overloading : None +--| +--| Purpose :To write a character to an ASCII_TEXT file. +--| +--| Parameters : +--| c -- input, CHARACTER, +--| stream -- output ASCII_TEXT, +--| +--| Result : +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| This procedure is equivalent to VHDL WRITE(stream, c). +--| +--| USE: : +--| VARIABLE str12 : string(1 TO 12); +--| FILE out_file : ASCII_TEXT IS OUT "file_ascii_out.dat"; +--| +--| str12 := "0123456789ab"; +--| FOR i IN 1 TO 12 LOOP +--| fputc(str12(i), out_file); +--| END LOOP; +--| +--| Will write all the 12 characters to file +--| file_ascii_out.dat +--|----------------------------------------------------------------------------- + PROCEDURE fputc ( CONSTANT c : IN CHARACTER; + VARIABLE stream : OUT ASCII_TEXT + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fputc +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To write a character to a TEXT file. +--| +--| Parameters : +--| c -- input, CHARACTER, +--| stream -- output, TEXT, +--| line_ptr -- INOUT LINE +--| +--| Result : +--| +--| Note: : The STD TEXTIO package has declared TEXT as a +--| file of STRING. This is not same as file of CHARACTERS. +--| +--| USE: : +--| VARIABLE str12 : string(1 TO 12); +--| VARIABLE l : LINE; +--| FILE out_file : TEXT IS OUT "file_text_out.dat"; +--| +--| str12 := "0123456789ab"; +--| FOR i IN 1 TO 12 LOOP +--| fputc(str12(i), out_file, l); +--| END LOOP; +--| fputc(LF, out_file, l); -- line feed +--| +--| Will write contents of the str12 to file +--| file_text_out.dat. The characters will be kept in +--| the line pointer l untill line feed character is +--| encouneterd. +--| +--|----------------------------------------------------------------------------- + PROCEDURE fputc ( CONSTANT c : IN character; + VARIABLE stream : OUT TEXT; + VARIABLE line_ptr : INOUT LINE + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fputs +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To write a string to an ASCII_ TEXT file. +--| +--| Parameters : +--| l_str -- input, string +--| stream -- output, ASCII_TEXT, +--| +--| Result : +--| +--| Note: : The ASCII_TEXT is defined in the package Std_IOpak to +--| be a file of CHARACTERS. +--| +--| USE: : +--| VARIABLE str_buf : string(1 TO 256); +--| FILE out_file : ASCII_TEXT IS OUT "file_ascii_out.dat"; +--| +--| fputs(str_buf, out_file); +--| +--| Will write contents of str_buf to the file +--| file_ascii_out.dat +--| +--|----------------------------------------------------------------------------- + PROCEDURE fputs ( CONSTANT l_str : IN STRING; + VARIABLE stream : OUT ASCII_TEXT + ); + +--+----------------------------------------------------------------------------- +--| Function Name : fputs +--| 1.2.4 +--| Overloading : None +--| +--| Purpose : To write a string to a TEXT file. +--| +--| Parameters : +--| l_str -- input, string, +--| stream -- output, TEXT, +--| line_ptr -- INOUT LINE, +--| +--| Result : +--| +--| Note: : The STD TEXTIO package has declared TEXT as a +--| file of STRING. This is not same as file of CHARACTERS. +--| USE: : +--| VARIABLE str_buf : string(1 TO 256); +--| VARIABLE lptr : LINE; +--| FILE out_file : TEXT IS OUT "file_text_out.dat"; +--| +--| fputs(str_buf, out_file, lptr); +--| +--| Will write contents of str_buf to the file +--| file_text_out.dat +--| +--|----------------------------------------------------------------------------- + PROCEDURE fputs ( CONSTANT l_str : IN STRING; + VARIABLE stream : OUT TEXT; + VARIABLE line_ptr : INOUT LINE + ); +--+----------------------------------------------------------------------------- +--| Function Name : Find_Char +--| +--| Overloading : None +--| +--| Purpose : TO find a given character in a string and +--| return its position. +--| +--| Parameters : +--| l_str - input STRING, +--| c - input Character, +--| +--| Result : NATURAL number representing the position of character +--| in the string. returns 0 if character not found in the +--| string. +--| +--| USE: : +--| VARIABLE str14 : string(1 TO 14); +--| VARIABLE indx : integer; +--| +--| str14 :="This is a test"; +--| indx := Fid_Char(str14, 'i'); +--| +--| Will assign value of 3 to the variable indx. +--|----------------------------------------------------------------------------- + FUNCTION Find_Char ( CONSTANT l_str : IN STRING; + CONSTANT c : IN CHARACTER + ) RETURN NATURAL; +--+----------------------------------------------------------------------------- +--| Function Name : Sub_Char +--| +--| Overloading : None +--| +--| Purpose : To subtitute a new character at a given position +--| of the input string. +--| +--| Parameters : +--| l_str - input STRING, +--| c - input Character, +--| n - input Natural, position at which character +--| is to be substituted. +--| Result : STRING +--| +--| USE: : +--| VARIABLE str14 : string(1 TO 14); +--| VARIABLE indx : integer; +--| +--| str14 :="This is a test"; +--| IF ((indx = Find_Char(str14, 't')) /= 0) THEN +--| str14 := Sub_Char(str14, 'T', indx); +--| END IF; +--| +--| Will assign the value "This is a Test" to str14. +--|----------------------------------------------------------------------------- + FUNCTION Sub_Char ( CONSTANT l_str : IN STRING; + CONSTANT c : IN CHARACTER; + CONSTANT n : IN NATURAL + ) RETURN STRING; +-- +-- related to time +-- +--+----------------------------------------------------------------------------- +--| Function Name : From_String +--| +--| Overloading : None +--| +--| Purpose : Convert from a String to a time. +--| +--| Parameters : +--| str - input , string to be converted, +--| +--| Result : Time +--| +--| NOTE : +--| +--| Use : +--| VARIABLE t : time ; +--| +--| t := From_String (" 893.56 us"); +--| This statement will set t to time 893.56 us. +--| +--|----------------------------------------------------------------------------- + FUNCTION From_String ( CONSTANT str : IN STRING + ) RETURN TIME; +--+----------------------------------------------------------------------------- +--| Function Name : To_String +--| 1.1.7 +--| Overloading : None +--| +--| Purpose : Convert Time to a String. +--| +--| Parameters : +--| val - input, TIME, +--| format - input string +--| +--| Result : STRING representation of TIME. +--| +--| +--|----------------------------------------------------------------------------- + FUNCTION To_String ( CONSTANT val : IN TIME; + CONSTANT format : IN STRING := "" + ) RETURN STRING; + +END std_iopak; + + + + diff --git a/src/hdl/pkg/qlaser_dac_dc_pkg.vhd b/src/hdl/pkg/qlaser_dac_dc_pkg.vhd new file mode 100644 index 0000000..eef161e --- /dev/null +++ b/src/hdl/pkg/qlaser_dac_dc_pkg.vhd @@ -0,0 +1,30 @@ +---------------------------------------------------------------------------------------- +-- Project : qlaser FPGA +-- File : qlaser_dac_dc_pkg.vhd +-- Description : Version package file. +-- Author : akozyra +---------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +package qlaser_dac_dc_pkg is + +---------------------------------------------------------------------------------------- +-- Constants +---------------------------------------------------------------------------------------- + +-- Addresses +constant C_ADDR_SPI0 : std_logic_vector(2 downto 0) := "000"; +constant C_ADDR_SPI1 : std_logic_vector(2 downto 0) := "001"; +constant C_ADDR_SPI2 : std_logic_vector(2 downto 0) := "010"; +constant C_ADDR_SPI3 : std_logic_vector(2 downto 0) := "011"; +constant C_ADDR_SPI_ALL : std_logic_vector(2 downto 0) := "100"; +constant C_ADDR_INTERNAL_REF : std_logic_vector(2 downto 0) := "101"; +constant C_ADDR_POWER_ON : std_logic_vector(2 downto 0) := "110"; + +-- Commands +constant C_CMD_DAC_DC_WR : std_logic_vector(3 downto 0) := "0011"; +constant C_CMD_DAC_DC_INTERNAL_REF : std_logic_vector(3 downto 0) := "1000"; +constant C_CMD_DAC_DC_POWER : std_logic_vector(3 downto 0) := "0100"; + +end package qlaser_dac_dc_pkg; diff --git a/src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd b/src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd new file mode 100644 index 0000000..cc330b7 --- /dev/null +++ b/src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd @@ -0,0 +1,38 @@ +---------------------------------------------------------------------------------------- +-- Project : qlaser FPGA +-- File : qlaser_dacs_pulse_channel.vhd +-- Description : Pulse Channel package file specifying constants +-- Author : eyhc +---------------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; + +package qlaser_dacs_pulse_channel_pkg is +-- Constants declearations +constant C_RAM_SELECT : integer := 11; -- Select bit for which RAM for CPU read/write +-- constant C_NUM_PULSE : integer := 16; -- Number of output data values from pulse RAM (16x24-bit) + +constant C_START_TIME : integer := 24; -- Start time for pulse generation +constant C_BITS_ADDR_START : integer := 12; -- Number of bits for starting address +constant C_BITS_ADDR_LENGTH : integer := 10; -- Number of bits for length address used by an edge of a pulse +constant C_BITS_GAIN_FACTOR : integer := 16; -- Number of bits in gain table +constant C_BITS_TIME_FACTOR : integer := 16; -- Number of bits in time table +constant C_BITS_TIME_INT : integer := 14; -- Starting bit for time integer part of the time factor, counting from MSB +constant C_BITS_TIME_FRAC : integer := 5; -- Starting bit for time fractional part of the time factor, counting from MSB +constant C_BITS_ADDR_TOP : integer := 17; -- Number of bits for the "flat top", the top of the pulse +constant C_BITS_ADDR_FULL : integer := 20; -- Number of bits for the untruncated address, should be C_BITS_ADDR_LENGTH + fractional bits of time factor + +constant C_LENGTH_WAVEFORM : integer := 4096; -- Number of output data values from waveform RAM (4kx16-bit) +constant C_BITS_ADDR_WAVE : integer := 16; -- Number of bits in address for waveform RAM + +constant C_BITS_ADDR_PULSE : integer := 10; -- Number of bits in address for pulse definition RAM +constant C_LEN_PULSE : integer := 2**C_BITS_ADDR_PULSE; -- Numbers of address for pulse definition RAM +constant C_PC_INCR : integer := 4; + -- Width of pulse counter increment + + +constant BIT_FRAC : integer := 8; -- Define the number of fractional bits +constant BIT_FRAC_GAIN : integer := C_BITS_GAIN_FACTOR - 1; -- Define the number of fractional bits of the gain +type real_array is array (natural range <>) of real; +type int_array is array (natural range <>) of integer; +end package qlaser_dacs_pulse_channel_pkg; \ No newline at end of file diff --git a/src/hdl/pkg/qlaser_pkg.vhd b/src/hdl/pkg/qlaser_pkg.vhd new file mode 100644 index 0000000..89bd4ab --- /dev/null +++ b/src/hdl/pkg/qlaser_pkg.vhd @@ -0,0 +1,146 @@ +------------------------------------------------------------------------------- +-- Filename : qlaser_pkg.vhd +------------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.qlaser_dac_dc_pkg.all; +-- use work.qlaser_dac_ac_pkg.all; + +-------------------------------------------------------------------------------- +-- FPGA constant definitions +------------------------------------------------------------------------------- +package qlaser_pkg is + +-- FPGA internal (PLL) clock freq expressed in MHz +constant C_CLK_FREQ_MHZ : real := 100.0; +-- Clock period +constant C_CLK_PERIOD : time := integer(1.0E+6/(C_CLK_FREQ_MHZ)) * 1 ps; + +constant C_NUM_CHAN_DC : integer := 32; -- Number of DC channels +constant C_NUM_CHAN_AC : integer := 32; -- Number of AC (pulse) channels + +-------------------------------------------------------------------------------- +-- FPGA Addresses +-- Main blocks. Decoded from upper 4 bits of address [15:12] +-------------------------------------------------------------------------------- +constant ADR_BASE_DC : std_logic_vector( 3 downto 0) := X"0"; -- Registers to load DC DAC values +constant ADR_BASE_PULSE : std_logic_vector( 3 downto 0) := X"1"; -- RAMs for Pulse output start/stop times +constant ADR_BASE_MISC : std_logic_vector( 3 downto 0) := X"2"; -- Misc, LEDs, switches, power control + +-------------------------------------------------------------------------------- +-- Define the number of internal blocks that are addressed by the CPU +-------------------------------------------------------------------------------- +constant C_NUM_BLOCKS : integer := 3; +type t_arr_cpu_dout is array (0 to C_NUM_BLOCKS-1) of std_logic_vector(31 downto 0); +type t_arr_dout_ac is array (0 to C_NUM_CHAN_AC-1) of std_logic_vector(15 downto 0); + + +-------------------------------------------------------------------------------------------------------------------------- +-- 'DC' DAC block registers. 32 16-bit DAC outputs [5:3] +constant C_ADDR_CH_SPI0 : std_logic_vector(2 downto 0) := "000"; +constant C_ADDR_CH_SPI1 : std_logic_vector(2 downto 0) := "001"; +constant C_ADDR_CH_SPI2 : std_logic_vector(2 downto 0) := "010"; +constant C_ADDR_CH_SPI3 : std_logic_vector(2 downto 0) := "011"; +constant C_ADDR_CH_SPI_ALL : std_logic_vector(2 downto 0) := "100"; +constant C_ADDR_INTERNAL_REF : std_logic_vector(2 downto 0) := "101"; +constant C_ADDR_POWER_ON : std_logic_vector(2 downto 0) := "110"; + +-------------------------------------------------------------------------------------------------------------------------- +-- Individual DAC data registers +constant ADR_DAC_DC0 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "000"; -- +constant ADR_DAC_DC1 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "001"; -- +constant ADR_DAC_DC2 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "010"; -- +constant ADR_DAC_DC3 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "011"; -- +constant ADR_DAC_DC4 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "100"; -- +constant ADR_DAC_DC5 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "101"; -- +constant ADR_DAC_DC6 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "110"; -- +constant ADR_DAC_DC7 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI0 & "111"; -- + +constant ADR_DAC_DC8 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI1 & "000"; -- +constant ADR_DAC_DC9 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI1 & "001"; -- + +-- constant ADR_DAC_DC6 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI2 & "000"; -- +-- constant ADR_DAC_DC7 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI2 & "001"; -- +-- etc. etc. +-- constant ADR_DAC_DC6 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI3 & "110"; -- +-- constant ADR_DAC_DC7 : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_SPI3 & "111"; -- +constant ADR_DAC_DC30 : std_logic_vector(15 downto 0) := ADR_BASE_DC & X"01E"; -- +constant ADR_DAC_DC31 : std_logic_vector(15 downto 0) := ADR_BASE_DC & X"01F"; -- + +constant ADR_DAC_DC_ALL : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_CH_SPI_ALL & "000"; -- Write all channels +constant ADR_DAC_DC_IREF : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_INTERNAL_REF & "000"; -- +constant ADR_DAC_DC_POWER_ON : std_logic_vector(15 downto 0) := ADR_BASE_DC & "000000" & C_ADDR_POWER_ON & "000"; -- +constant ADR_DAC_DC_STATUS : std_logic_vector(15 downto 0) := ADR_BASE_DC & X"000"; -- Reading any address returns SPI interface busy status (this was 32 bit, but decleared as 16, so I changed to 16) + + +-------------------------------------------------------------------------------------------------------------------------- +-- 'Pulse' DAC block registers. +-- The block has a set of block registers and contains 16 'channels' +-- Each channel has a 40-bit memory to specify 24-bit time and a 16-bit level. +-- Initially just using the MSB of the level to drive a single pin output +-- +-------------------------------------------------------------------------------------------------------------------------- +-- Block-level registers +-- CPU_ADDR(11) = '0' selects local regs +-- CPU_ADDR(11) = '1' selects the channel specified in reg_ctrl(3 :0) +-- Then CPU_ADDR(10:1) selects RAM word address (1024 address MAX) +-- CPU_ADDR(0) selects MSB or LSB of 40-bit RAM word (time or amplitude) +-------------------------------------------------------------------------------------------------------------------------- +-- Addresses for block-level registers. +------------------------------------------------------------------------------------------------------------------------- +constant ADR_DAC_PULSE_CTRL : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"800"; -- 4:0 select channel RAM for CPU read/write. Bit 8 is rising edge internal trigger +constant ADR_DAC_PULSE_STATUS : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"801"; -- R/O Level status for output of each channel +constant ADR_DAC_PULSE_RUNTIME : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"802"; -- Max time for pulse train +constant ADR_DAC_PULSE_CH_EN : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"803"; -- Enable bit for each individual channel +constant ADR_DAC_PULSE_TIMER : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"804"; -- R/O Current timer value (used by all channels) +------------------------------------------------------------------------------------------------------------------------- + +-------------------------------------------------------------------------------------------------------------------------- +-- Pulse Channel offsets +-------------------------------------------------------------------------------------------------------------------------- +constant ADR_DAC_PULSE0 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"000"; -- Base address of a 16-word x 40-bit RAM +constant ADR_DAC_PULSE1 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"040"; -- +constant ADR_DAC_PULSE2 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"080"; -- +constant ADR_DAC_PULSE3 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"0C0"; -- +-- +constant ADR_DAC_PULSE4 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"100"; -- +constant ADR_DAC_PULSE5 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"140"; -- +constant ADR_DAC_PULSE6 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"180"; -- +constant ADR_DAC_PULSE7 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"1C0"; -- +-- +constant ADR_DAC_PULSE8 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"200"; -- +constant ADR_DAC_PULSE9 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"240"; -- +constant ADR_DAC_PULSE10 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"280"; -- +constant ADR_DAC_PULSE11 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"2C0"; -- +-- +constant ADR_DAC_PULSE12 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"300"; -- +constant ADR_ADC_PULSE13 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"340"; -- +constant ADR_DAC_PULSE14 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"380"; -- +constant ADR_DAC_PULSE15 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"3C0"; -- +-- +-- etc. etc. +constant ADR_DAC_PULSE28 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"700"; -- +constant ADR_DAC_PULSE29 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"740"; -- +constant ADR_DAC_PULSE30 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"780"; -- +constant ADR_DAC_PULSE31 : std_logic_vector(15 downto 0) := ADR_BASE_PULSE & X"7C0"; -- + + + +-------------------------------------------------------------------------------------------------------------------------- +-- Misc block registers +-------------------------------------------------------------------------------------------------------------------------- +constant ADR_MISC_VERSION : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"000"; -- HDL code version +constant ADR_MISC_LEDS : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"001"; -- LEDs +constant ADR_MISC_LEDS_EN : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"002"; -- LEDs enable +constant ADR_MISC_SW_IN : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"003"; -- Read board switch settings (if present) +constant ADR_MISC_DEBUG_CTRL : std_logic_vector(15 downto 0) := ADR_BASE_MISC & X"004"; -- Select debug output from top level to pins + + +end package; + +package body qlaser_pkg is + +end package body; + diff --git a/src/hdl/tb/poly_gen_nonsynth.vhdl b/src/hdl/tb/poly_gen_nonsynth.vhdl new file mode 100644 index 0000000..b741ff4 --- /dev/null +++ b/src/hdl/tb/poly_gen_nonsynth.vhdl @@ -0,0 +1,44 @@ +----------------------------------------------------------- +-- File : poly_gen_nonsynth.vhdl +----------------------------------------------------------- +-- +-- Simulation-only module of a floating point polynomial calculator +-- +-- Description : Calculates the value of a polynomial at a given time, using the coefficients +-- +---------------------------------------------------------- +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; +use std.textio.all; + +use ieee.math_real.uniform; +use ieee.math_real.floor; + + +use work.std_iopak.all; +use work.qlaser_dacs_pulse_channel_pkg.all; +entity poly_gen is + generic ( + degrees : natural := 5 -- n-th degree polynomial + ); + port ( + clk : in std_logic; + direction : in std_logic; -- 0 = rising, 1 = falling + times : in integer; -- time stamp + coeffs : in real_array(0 to degrees-1); -- coefficients coeffs_array : real_array(0 to degrees-1); + poly_out : out real + ); +end entity poly_gen; + +architecture nonsynth of poly_gen is + -- type real_array is array (0 to degrees-1) of real; + -- signal coeffs_array : real_array; + -- variable poly_sum : real := 0.0; +begin + -- wait until clk'event and clk='0'; + -- for i in 0 to degrees loop + -- poly_sum := poly_sum + coeffs_array(i) * times**i; + -- end loop; + -- poly_out <= poly_sum; +end architecture nonsynth; \ No newline at end of file diff --git a/src/hdl/tb/qlaser_dacs_pulse_tb.vhdl b/src/hdl/tb/qlaser_dacs_pulse_tb.vhdl new file mode 100644 index 0000000..4f4f11d --- /dev/null +++ b/src/hdl/tb/qlaser_dacs_pulse_tb.vhdl @@ -0,0 +1,487 @@ +----------------------------------------------------------- +-- File : tb_cpubus_dacs_pulse_channel.vhd +----------------------------------------------------------- +-- +-- Testbench for CPU bus peripheral. +-- +-- Description : Pulse output control of Qlaser FPGA +-- Block drives AXI-stream to JESD DACs +-- +---------------------------------------------------------- +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; +use std.textio.all; + +use work.std_iopak.all; +use work.qlaser_dacs_pulse_channel_pkg.all; + + +entity tb_cpubus_dacs_pulse_channel is +end tb_cpubus_dacs_pulse_channel; + +architecture behave of tb_cpubus_dacs_pulse_channel is + +signal clk : std_logic; +signal reset : std_logic; +signal enable : std_logic; +signal start : std_logic; +signal cnt_time : std_logic_vector(23 downto 0); +signal busy : std_logic; +signal done_seq : std_logic; +signal cpu_wr : std_logic; +signal cpu_sel : std_logic; +signal cpu_addr : std_logic_vector(15 downto 0); +signal cpu_wdata : std_logic_vector(31 downto 0); +signal cpu_rdata : std_logic_vector(31 downto 0); +signal cpu_rdata_dv : std_logic; + +-- AXI-stream output interface +signal axis_tready : std_logic := '1'; -- Always ready +signal axis_tdata : std_logic_vector(15 downto 0); +signal axis_tvalid : std_logic; +signal axis_tlast : std_logic; + +-- Halts simulation by stopping clock when set true +signal sim_done : boolean := false; + +-- Crystal clock freq expressed in MHz +constant CLK_FREQ_MHZ : real := 100.0; +-- Clock period +constant CLK_PER : time := integer(1.0E+6/(CLK_FREQ_MHZ)) * 1 ps; + +-- Block registers +-- constant ADR_RAM_PULSE : integer := to_integer(unsigned(X"0000")); -- TODO: Modelsim cannot compile this +-- constant ADR_RAM_WAVE : integer := to_integer(unsigned(X"0200")); -- TODO: Modelsim cannot compile this +constant ADR_RAM_PULSE : integer := 0; -- TODO: Modelsim cannot compile this +constant ADR_RAM_WAVE : integer := 2048; -- TODO: Modelsim cannot compile this + + +------------------------------------------------------------- +-- CPU write procedure. Address in decimal. Data in hex +------------------------------------------------------------- +procedure cpu_write( + signal clk : in std_logic; + constant a : in integer; + constant d : in std_logic_vector(31 downto 0); + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +begin + wait until clk'event and clk='0'; + cpu_sel <= '1'; + cpu_wr <= '1'; + cpu_addr <= std_logic_vector(to_unsigned(a, 16)); + cpu_wdata <= std_logic_vector(d); + wait until clk'event and clk='0'; + cpu_sel <= '0'; + cpu_wr <= '0'; + cpu_addr <= (others=>'0'); + cpu_wdata <= (others=>'0'); + wait until clk'event and clk='0'; +end; + + +------------------------------------------------------------- +-- CPU write procedure. Address and Data in decimal +------------------------------------------------------------- +procedure cpu_write( + signal clk : in std_logic; + constant a : in integer; + constant d : in integer; + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +begin + cpu_write(clk, a , std_logic_vector(to_unsigned(d,32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata); +end; + +------------------------------------------------------------- +-- CPU write pulse definition RAM +-- Make fore 32-bit data write +------------------------------------------------------------- +procedure cpu_write_pulsedef( + signal clk : in std_logic; + + constant num_entry : in integer; + + -- TODO: Partial ? list of parameters, there could be more if need more features + constant pulsetime : in integer; -- Pulse time in clock cycles + constant timefactor : in real; -- Fixed point time scale factor + constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000" + constant wavestartaddr : in integer; -- Start address in waveform RAM + constant wavesteps : in integer; -- Number of steps in waveform rise and fall + constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall + + + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +-- Vectors for converted values +variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time +variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep +variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain +variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM +variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points +variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform + +-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg +-- Define the number of fractional bits +begin + + -- Convert each field into its std_logic_vector equivalent + slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24)); + slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12)); + slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10)); + slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17)); + + + --etc, etc. + -- 4 writes. (Address is an integer) + cpu_write(clk, ADR_RAM_PULSE+num_entry , x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"0" & slv_wavesteps & x"0" & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+2) , slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + +end; + +------------------------------------------------------------- +-- CPU read procedure +------------------------------------------------------------- +procedure cpu_read( + signal clk : in std_logic; + constant a : in integer; + constant exp_d : in std_logic_vector(31 downto 0); + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0); + signal cpu_rdata : in std_logic_vector(31 downto 0); + signal cpu_rdata_dv : in std_logic +) is +variable v_bdone : boolean := false; +variable str_out : string(1 to 256); +begin + wait until clk'event and clk='0'; + cpu_sel <= '1'; + cpu_wr <= '0'; + cpu_addr <= std_logic_vector(to_unsigned(a, 16)); + cpu_wdata <= (others=>'0'); + while (v_bdone = false) loop + wait until clk'event and clk='0'; + cpu_sel <= '1'; + if (cpu_rdata_dv = '1') then + if (cpu_rdata /= exp_d) then + fprint(str_out, "Read exp: 0x%s actual: 0x%s\n", to_string(to_bitvector(exp_d),"%08X"), to_string(to_bitvector(cpu_rdata),"%08X")); + report str_out severity error; + end if; + v_bdone := true; + cpu_sel <= '0'; + cpu_addr <= (others=>'0'); + end if; + end loop; + wait until clk'event and clk='0'; + wait until clk'event and clk='0'; +end; + +------------------------------------------------------------- +-- CPU read pulse definition RAM +-- make four 32-bit reads +------------------------------------------------------------- +procedure cpu_read_pulsedef( + signal clk : in std_logic; + + constant num_entry : in integer; + + -- TODO: Partial ? list of parameters, there could be more if need more features + constant pulsetime : in integer; -- Pulse time in clock cycles + constant timefactor : in real; -- Fixed point time scale factor + constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000" + constant wavestartaddr : in integer; -- Start address in waveform RAM + constant wavesteps : in integer; -- Number of steps in waveform rise and fall + constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall + + + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +-- Vectors for converted values +variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time +variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep +variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain +variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM +variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points +variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform + +-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg +-- Define the number of fractional bits +begin + + -- Convert each field into its std_logic_vector equivalent + slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24)); + slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12)); + slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10)); + slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17)); + + + --etc, etc. + -- 4 writes. (Address is an integer) + cpu_read(clk, ADR_RAM_PULSE+num_entry, x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + cpu_read(clk, ADR_RAM_PULSE+(num_entry+1), "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + cpu_read(clk, ADR_RAM_PULSE+(num_entry+2), slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + cpu_read(clk, ADR_RAM_PULSE+(num_entry+3), "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + +end; + + +------------------------------------------------------------- +-- Delay +------------------------------------------------------------- +procedure clk_delay( + constant nclks : in integer +) is +begin + for I in 0 to nclks loop + wait until clk'event and clk ='0'; + end loop; +end; + + +---------------------------------------------------------------- +-- Print a string with no time or instance path. +---------------------------------------------------------------- +procedure cpu_print_msg( + constant msg : in string +) is +variable line_out : line; +begin + write(line_out, msg); + writeline(output, line_out); +end procedure cpu_print_msg; + + +begin + + ------------------------------------------------------------- + -- Unit Under Test + ------------------------------------------------------------- + u_dac_pulse : entity work.qlaser_dacs_pulse_channel + port map ( + clk => clk , -- in std_logic; + reset => reset , -- in std_logic; + + enable => enable , -- out std_logic; + start => start , -- out std_logic; + cnt_time => cnt_time , -- out std_logic_vector(23 downto 0); -- Set to '1' while SPI interface is busy + + busy => busy , -- out std_logic; -- Set to '1' while SPI interface is busy + done_seq => done_seq , -- in std_logic; -- Set to '1' when SPI sequence is done + + -- CPU interface + cpu_wr => cpu_wr , -- in std_logic; + cpu_sel => cpu_sel , -- in std_logic; + cpu_addr => cpu_addr(11 downto 0) , -- in std_logic_vector(11 downto 0); + cpu_wdata => cpu_wdata , -- in std_logic_vector(31 downto 0); + + cpu_rdata => cpu_rdata , -- out std_logic_vector(31 downto 0); + cpu_rdata_dv => cpu_rdata_dv , -- out std_logic; + + + -- AXI-Stream interface + axis_tready => axis_tready , -- in std_logic; -- Clock (50 MHz max) + axis_tdata => axis_tdata , -- out std_logic_vector(15 downto 0); + axis_tvalid => axis_tvalid , -- out std_logic; -- Master out, Slave in. (Data to DAC) + axis_tlast => axis_tlast -- out std_logic; -- Active low chip select (sync_n) + ); + + + ------------------------------------------------------------- + -- Generate system clock. Halt when sim_done is true. + ------------------------------------------------------------- + pr_clk : process + begin + clk <= '0'; + wait for (CLK_PER/2); + clk <= '1'; + wait for (CLK_PER-CLK_PER/2); + if (sim_done=true) then + wait; + end if; + end process; + + + ------------------------------------------------------------- + -- Reset and drive CPU bus + ------------------------------------------------------------- + pr_main : process + variable v_ndata32 : integer := 0; + variable v_ndata16 : integer := 0; + + -- "global" variables for base definitions of each pulses, all pulses are based on these but scaled/offset a bit + variable v_pulseaddr : integer := 0; -- manually set the pulse address, 0 to 255 + variable v_waveaddr : integer := 0; -- manually set the wave address, 0 to 2047 + variable v_pulsetime : integer := 0; -- For 24-bit pulse time + variable v_timefactor : real := 0.0; -- For 16-bit fixed point timestep + variable v_gainfactor : real := 0.0; -- For 16-bit fixed point gain + variable v_wavestartaddr : integer := 0; -- For 12-bit address i.e. 1024 point waveform RAM + variable v_wavesteps : integer := 0; -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points + variable v_wavetopwidth : integer := 0; -- For 17-bit number of clock cycles in top of waveform + + begin + -- Reset + reset <= '1'; + enable <= '0'; + start <= '0'; + done_seq <= '0'; + cnt_time <= (others=>'0'); + + cpu_sel <= '0'; + cpu_wr <= '0'; + cpu_wdata <= (others=>'0'); + cpu_addr <= (others=>'0'); + + cpu_print_msg("Simulation start"); + clk_delay(5); + reset <= '0'; + + clk_delay(5); + enable <= '1'; + + + clk_delay(20); + + + ---------------------------------------------------------------- + -- Load pulse RAM with a series of pulse start times + ---------------------------------------------------------------- + -- v_ndata32 := 128; -- Time for first pulse + v_pulsetime := 128; + cpu_print_msg("Load pulse RAM"); + -- for NADDR in 0 to 255 loop + -- -- TODO: In the real setting should we have the python script to check those parameters to make sure they are valid and non-overlapping? + -- -- v_pulsetime := v_ndata32 + (NADDR*(1024+32)); -- todo: what is this math doing? + + -- v_timefactor := 1.0; + -- v_gainfactor := 1.0; + -- v_wavestartaddr := v_wavesteps + v_wavestartaddr; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right? + -- v_wavesteps := NADDR; + -- v_wavetopwidth := 114; + -- v_pulsetime := (v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3); + -- -- cpu_write_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + -- cpu_write_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + -- end loop; + + ---------------------------------------------------------------- + -- Load pulse RAM with a series of pulse start times MANUALLY + --------------------------------------------------------------- + v_pulseaddr := 0; + v_pulsetime := 4; + v_timefactor := 1.0; + v_gainfactor := 1.0; + v_wavestartaddr := 1; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right? + v_wavesteps := 4; + v_wavetopwidth := 1; + cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + + + v_pulseaddr := 1; + v_timefactor := 1.0; + v_gainfactor := 1.0; + v_wavestartaddr := 4; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right? + v_wavesteps := 6; + v_wavetopwidth := 9; + v_pulsetime := v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3; + cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + + + cpu_print_msg("Pulse RAM loaded"); + clk_delay(20); + + ---------------------------------------------------------------- + -- Load waveform RAM with a simple ramp + -- Write two 16-bit values with each write + ---------------------------------------------------------------- + cpu_print_msg("Load waveform RAM"); + v_ndata16 := 1; -- first waveform value + for NADDR in 0 to 2047 loop + v_ndata32 := (((v_ndata16) * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1)); -- Write two 16-bit values with each write + cpu_write(clk, (ADR_RAM_WAVE + NADDR) , v_ndata32, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + v_ndata16 := v_ndata16 + 2; + end loop; + + + -- ---------------------------------------------------------------- + -- -- Read back Pulse RAM. + -- -- Comment out if not needed to check CPU R/W + -- ---------------------------------------------------------------- + -- v_ndata32 := 128; -- Time for first pulse + -- for NADDR in 0 to 255 loop + -- v_pulsetime := v_ndata32 + (NADDR*(1024+32)); + -- v_timefactor := 1.0; + -- v_gainfactor := 1.0; + -- v_wavestartaddr := 0; + -- v_wavesteps := NADDR*32; + -- v_wavetopwidth := 0; + -- cpu_read_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + -- end loop; + -- clk_delay(20); + + -- ---------------------------------------------------------------- + -- -- Read back Waveform RAM + -- ---------------------------------------------------------------- + -- v_ndata16 := 1; -- first waveform value + -- for NADDR in 0 to 2047 loop + -- v_ndata32 := (((v_ndata16) * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1)); + -- cpu_read (clk, ADR_RAM_WAVE + NADDR , std_logic_vector(to_unsigned(v_ndata32, 32)) , cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + -- v_ndata16 := v_ndata16 + 2; + -- end loop; + + -- -- Done reg write/read check + -- cpu_print_msg("RAM readback completed"); + -- clk_delay(20); + + + ---------------------------------------------------------------- + -- Start the pulse outputs + ---------------------------------------------------------------- + done_seq <= '0'; + clk_delay(5); + start <= '1'; + clk_delay(5); + start <= '0'; + + -- TODO: we may need to modify the for loop to make sure the simulation time is long enough to cover all the pulses + -- Wait for cnt_time to reach last pulse start time + waveform size + for NCNT in 1 to v_pulsetime + 100 loop -- TODO: EricToGeoff/Sara: in the real settings do we have a constant amount of time or the total time also vary? if so, how much? + -- for NCNT in 1 to 128 loop -- count the time shorter for now so it won't take too long to simulate + cnt_time <= std_logic_vector(unsigned(cnt_time) + 1); + -- if (NCNT = v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 8) then -- Stop simulation when last pulse is done + -- done_seq <= '1'; + -- end if; + clk_delay(0); + end loop; + + wait for 10 us; + + cpu_print_msg("Simulation done"); + clk_delay(5); + + sim_done <= true; + wait; + + end process; + +end behave; + diff --git a/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl b/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl new file mode 100644 index 0000000..ebe8979 --- /dev/null +++ b/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl @@ -0,0 +1,514 @@ +----------------------------------------------------------- +-- File : tb_cpubus_dacs_pulse_channel.vhd +----------------------------------------------------------- +-- +-- Testbench for CPU bus peripheral. +-- +-- Description : Pulse output control of Qlaser FPGA +-- Block drives AXI-stream to JESD DACs +-- +---------------------------------------------------------- +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; +use std.textio.all; + +use ieee.math_real.uniform; +use ieee.math_real.floor; + + +use work.std_iopak.all; +use work.qlaser_dacs_pulse_channel_pkg.all; + + +entity tb_cpubus_dacs_pulse_channel is +end tb_cpubus_dacs_pulse_channel; + +architecture behave of tb_cpubus_dacs_pulse_channel is + +signal clk : std_logic; +signal reset : std_logic; +signal enable : std_logic; +signal start : std_logic; +signal cnt_time : std_logic_vector(23 downto 0); +signal busy : std_logic; +signal done_seq : std_logic; +signal cpu_wr : std_logic; +signal cpu_sel : std_logic; +signal cpu_addr : std_logic_vector(15 downto 0); +signal cpu_wdata : std_logic_vector(31 downto 0); +signal cpu_rdata : std_logic_vector(31 downto 0); +signal cpu_rdata_dv : std_logic; + +-- AXI-stream output interface +signal axis_tready : std_logic := '1'; -- Always ready +signal axis_tdata : std_logic_vector(15 downto 0); +signal axis_tvalid : std_logic; +signal axis_tlast : std_logic; + +-- Halts simulation by stopping clock when set true +signal sim_done : boolean := false; + +-- Crystal clock freq expressed in MHz +constant CLK_FREQ_MHZ : real := 100.0; +-- Clock period +constant CLK_PER : time := integer(1.0E+6/(CLK_FREQ_MHZ)) * 1 ps; + +-- Block registers +-- constant ADR_RAM_PULSE : integer := to_integer(unsigned(X"0000")); -- TODO: Modelsim cannot compile this +-- constant ADR_RAM_WAVE : integer := to_integer(unsigned(X"0200")); -- TODO: Modelsim cannot compile this +constant ADR_RAM_PULSE : integer := 0; -- TODO: Modelsim cannot compile this +constant ADR_RAM_WAVE : integer := 2048; -- TODO: Modelsim cannot compile this + + +------------------------------------------------------------- +-- CPU write procedure. Address in decimal. Data in hex +------------------------------------------------------------- +procedure cpu_write( + signal clk : in std_logic; + constant a : in integer; + constant d : in std_logic_vector(31 downto 0); + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +begin + wait until clk'event and clk='0'; + cpu_sel <= '1'; + cpu_wr <= '1'; + cpu_addr <= std_logic_vector(to_unsigned(a, 16)); + cpu_wdata <= std_logic_vector(d); + wait until clk'event and clk='0'; + cpu_sel <= '0'; + cpu_wr <= '0'; + cpu_addr <= (others=>'0'); + cpu_wdata <= (others=>'0'); + wait until clk'event and clk='0'; +end; + + +------------------------------------------------------------- +-- CPU write procedure. Address and Data in decimal +------------------------------------------------------------- +procedure cpu_write( + signal clk : in std_logic; + constant a : in integer; + constant d : in integer; + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +begin + cpu_write(clk, a , std_logic_vector(to_unsigned(d,32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata); +end; + +------------------------------------------------------------- +-- CPU write pulse definition RAM +-- Make fore 32-bit data write +------------------------------------------------------------- +procedure cpu_write_pulsedef( + signal clk : in std_logic; + + constant num_entry : in integer; + + -- TODO: Partial ? list of parameters, there could be more if need more features + constant pulsetime : in integer; -- Pulse time in clock cycles + constant timefactor : in real; -- Fixed point time scale factor + constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000" + constant wavestartaddr : in integer; -- Start address in waveform RAM + constant wavesteps : in integer; -- Number of steps in waveform rise and fall + constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall + + + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +-- Vectors for converted values +variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time +variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep +variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain +variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM +variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points +variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform + +-- Define the number of fractional bits +begin + + -- Convert each field into its std_logic_vector equivalent + slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24)); + slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12)); + slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10)); + slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17)); + + + --etc, etc. + -- 4 writes. (Address is an integer) + cpu_write(clk, ADR_RAM_PULSE+num_entry , x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"0" & slv_wavesteps & x"0" & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+2) , slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + +end; + +------------------------------------------------------------- +-- CPU read procedure +------------------------------------------------------------- +procedure cpu_read( + signal clk : in std_logic; + constant a : in integer; + constant exp_d : in std_logic_vector(31 downto 0); + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0); + signal cpu_rdata : in std_logic_vector(31 downto 0); + signal cpu_rdata_dv : in std_logic +) is +variable v_bdone : boolean := false; +variable str_out : string(1 to 256); +variable diff : integer; +begin + wait until clk'event and clk='0'; + cpu_sel <= '1'; + cpu_wr <= '0'; + cpu_addr <= std_logic_vector(to_unsigned(a, 16)); + cpu_wdata <= (others=>'0'); + while (v_bdone = false) loop + wait until clk'event and clk='0'; + cpu_sel <= '1'; + if (cpu_rdata_dv = '1') then + if (cpu_rdata /= exp_d) then + diff := abs(to_integer(unsigned(exp_d)) - to_integer(unsigned(cpu_rdata))); + fprint(str_out, "Read exp: 0x%s actual: 0x%s\n", to_string(to_bitvector(exp_d),"%08X"), to_string(to_bitvector(cpu_rdata),"%08X")); + report str_out severity warning; + -- TODO: this is not working, need to fix it + -- fprint(str_out, "Absolute difference: 0x%s\n", to_string(to_bitvector(diff),"%08X")); + report str_out severity warning; + end if; + v_bdone := true; + cpu_sel <= '0'; + cpu_addr <= (others=>'0'); + end if; + end loop; + wait until clk'event and clk='0'; + wait until clk'event and clk='0'; +end; + +-- TODO: implement the checker method for the the output of the entier wave + +------------------------------------------------------------- +-- CPU read pulse definition RAM +-- make four 32-bit reads +------------------------------------------------------------- +procedure cpu_read_pulsedef( + signal clk : in std_logic; + + constant num_entry : in integer; + + -- TODO: Partial ? list of parameters, there could be more if need more features + constant pulsetime : in integer; -- Pulse time in clock cycles + constant timefactor : in real; -- Fixed point time scale factor + constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000" + constant wavestartaddr : in integer; -- Start address in waveform RAM + constant wavesteps : in integer; -- Number of steps in waveform rise and fall + constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall + + + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +-- Vectors for converted values +variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time +variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep +variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain +variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM +variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points +variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform + +-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg +-- Define the number of fractional bits +begin + + -- Convert each field into its std_logic_vector equivalent + slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24)); + slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12)); + slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10)); + slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17)); + + + --etc, etc. + -- 4 writes. (Address is an integer) + cpu_read(clk, ADR_RAM_PULSE+num_entry, x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + cpu_read(clk, ADR_RAM_PULSE+(num_entry+1), "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + cpu_read(clk, ADR_RAM_PULSE+(num_entry+2), slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + cpu_read(clk, ADR_RAM_PULSE+(num_entry+3), "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + +end; + + +------------------------------------------------------------- +-- Delay +------------------------------------------------------------- +procedure clk_delay( + constant nclks : in integer +) is +begin + for I in 0 to nclks loop + wait until clk'event and clk ='0'; + end loop; +end; + + +---------------------------------------------------------------- +-- Print a string with no time or instance path. +---------------------------------------------------------------- +procedure cpu_print_msg( + constant msg : in string +) is +variable line_out : line; +begin + write(line_out, msg); + writeline(output, line_out); +end procedure cpu_print_msg; + + +begin + + ------------------------------------------------------------- + -- Unit Under Test + ------------------------------------------------------------- + u_dac_pulse : entity work.qlaser_dacs_pulse_channel + port map ( + clk => clk , -- in std_logic; + reset => reset , -- in std_logic; + + enable => enable , -- out std_logic; + start => start , -- out std_logic; + cnt_time => cnt_time , -- out std_logic_vector(23 downto 0); -- Set to '1' while SPI interface is busy + + busy => busy , -- out std_logic; -- Set to '1' while SPI interface is busy + done_seq => done_seq , -- in std_logic; -- Set to '1' when SPI sequence is done + + -- CPU interface + cpu_wr => cpu_wr , -- in std_logic; + cpu_sel => cpu_sel , -- in std_logic; + cpu_addr => cpu_addr(11 downto 0) , -- in std_logic_vector(11 downto 0); + cpu_wdata => cpu_wdata , -- in std_logic_vector(31 downto 0); + + cpu_rdata => cpu_rdata , -- out std_logic_vector(31 downto 0); + cpu_rdata_dv => cpu_rdata_dv , -- out std_logic; + + + -- AXI-Stream interface + axis_tready => axis_tready , -- in std_logic; -- Clock (50 MHz max) + axis_tdata => axis_tdata , -- out std_logic_vector(15 downto 0); + axis_tvalid => axis_tvalid , -- out std_logic; -- Master out, Slave in. (Data to DAC) + axis_tlast => axis_tlast -- out std_logic; -- Active low chip select (sync_n) + ); + + + ------------------------------------------------------------- + -- Generate system clock. Halt when sim_done is true. + ------------------------------------------------------------- + pr_clk : process + begin + clk <= '0'; + wait for (CLK_PER/2); + clk <= '1'; + wait for (CLK_PER-CLK_PER/2); + if (sim_done=true) then + wait; + end if; + end process; + + + ------------------------------------------------------------- + -- Reset and drive CPU bus + ------------------------------------------------------------- + pr_main : process + variable v_ndata32 : integer := 0; + variable v_ndata16 : integer := 0; + + -- "global" variables for base definitions of each pulses, all pulses are based on these but scaled/offset a bit + variable v_pulseaddr : integer := 0; -- manually set the pulse address, 0 to 255 + variable v_waveaddr : integer := 0; -- manually set the wave address, 0 to 2047 + variable v_pulsetime : integer := 0; -- For 24-bit pulse time + variable v_timefactor : real := 0.0; -- For 16-bit fixed point timestep + variable v_gainfactor : real := 0.0; -- For 16-bit fixed point gain + variable v_wavestartaddr : integer := 0; -- For 12-bit address i.e. 1024 point waveform RAM + variable v_wavesteps : integer := 0; -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points + variable v_wavetopwidth : integer := 0; -- For 17-bit number of clock cycles in top of waveform + + variable seed1 : positive; + variable seed2 : positive; + variable x : real; + variable y : real; + + + begin + -- Reset + reset <= '1'; + enable <= '0'; + start <= '0'; + done_seq <= '0'; + cnt_time <= (others=>'0'); + + cpu_sel <= '0'; + cpu_wr <= '0'; + cpu_wdata <= (others=>'0'); + cpu_addr <= (others=>'0'); + + cpu_print_msg("Simulation start"); + clk_delay(5); + reset <= '0'; + + clk_delay(5); + enable <= '1'; + + + clk_delay(20); + + seed1 := 2045; + seed2 := 1024; + ---------------------------------------------------------------- + -- Load pulse RAM with a series of pulse start times + ---------------------------------------------------------------- + -- v_ndata32 := 128; -- Time for first pulse + v_pulsetime := 128; + cpu_print_msg("Load pulse RAM"); + -- for NADDR in 0 to 255 loop + -- -- TODO: In the real setting should we have the python script to check those parameters to make sure they are valid and non-overlapping? + -- -- v_pulsetime := v_ndata32 + (NADDR*(1024+32)); -- todo: what is this math doing? + + -- v_timefactor := 1.0; + -- v_gainfactor := 1.0; + -- v_wavesteps := NADDR; + -- v_wavetopwidth := 114; + -- v_wavestartaddr := v_wavesteps + v_wavestartaddr; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right? + -- v_pulsetime := (v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3 + 1); + -- -- cpu_write_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + -- cpu_write_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + -- end loop; + ---------------------------------------------------------------- + -- Load pulse RAM with a series of pulse start times MANUALLY + --------------------------------------------------------------- + v_pulseaddr := 0; + v_timefactor := 1.0; + v_gainfactor := 1.0; + v_wavestartaddr := 4; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right? + v_wavesteps := 10; + v_wavetopwidth := 6; + v_pulsetime := 4; + cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + + -- Same pulse but scaled addr + v_pulseaddr := 1; + v_timefactor := 2.25; + v_gainfactor := 1.0; + v_wavestartaddr := 4; + v_wavesteps := 10; + v_wavetopwidth := 9; + v_pulsetime := v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3 + 1; + cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + + -- Same pulse but scaled gain + v_pulseaddr := 2; + v_timefactor := 1.0; + v_gainfactor := 0.25; + v_wavestartaddr := 4; + v_wavesteps := 10; + v_wavetopwidth := 0; + v_pulsetime := v_pulsetime + v_wavesteps + v_wavetopwidth + v_wavesteps + 4 + 3 + 1; + cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + + cpu_print_msg("Pulse RAM loaded"); + clk_delay(20); + + ---------------------------------------------------------------- + -- Load waveform RAM with a simple ramp + -- Write two 16-bit values with each write + ---------------------------------------------------------------- + cpu_print_msg("Load waveform RAM"); + v_ndata16 := 1; -- first waveform value + + for NADDR in 0 to 2047 loop + uniform(seed1, seed2, x); + uniform(seed1, seed2, y); + v_ndata32 := ((v_ndata16 * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1)); -- Write two 16-bit values with each write + cpu_write(clk, (ADR_RAM_WAVE + NADDR) , v_ndata32, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + v_ndata16 := v_ndata16 + 2; + end loop; + + + -- ---------------------------------------------------------------- + -- -- Read back Pulse RAM. + -- -- Comment out if not needed to check CPU R/W + -- ---------------------------------------------------------------- + -- v_ndata32 := 128; -- Time for first pulse + -- for NADDR in 0 to 255 loop + -- v_pulsetime := v_ndata32 + (NADDR*(1024+32)); + -- v_timefactor := 1.0; + -- v_gainfactor := 1.0; + -- v_wavestartaddr := 0; + -- v_wavesteps := NADDR*32; + -- v_wavetopwidth := 0; + -- cpu_read_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + -- end loop; + -- clk_delay(20); + + -- ---------------------------------------------------------------- + -- -- Read back Waveform RAM + -- ---------------------------------------------------------------- + -- v_ndata16 := 1; -- first waveform value + -- for NADDR in 0 to 2047 loop + -- v_ndata32 := (((v_ndata16) * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1)); + -- cpu_read (clk, ADR_RAM_WAVE + NADDR , std_logic_vector(to_unsigned(v_ndata32, 32)) , cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + -- v_ndata16 := v_ndata16 + 2; + -- end loop; + + -- -- Done reg write/read check + -- cpu_print_msg("RAM readback completed"); + -- clk_delay(20); + + + ---------------------------------------------------------------- + -- Start the pulse outputs + ---------------------------------------------------------------- + clk_delay(5); + start <= '1'; + clk_delay(5); + start <= '0'; + + -- TODO: we may need to modify the for loop to make sure the simulation time is long enough to cover all the pulses + -- Wait for cnt_time to reach last pulse start time + waveform size + for NCNT in 1 to v_pulsetime loop -- TODO: EricToGeoff/Sara: in the real settings do we have a constant amount of time or the total time also vary? if so, how much? + -- for NCNT in 1 to 128 loop -- count the time shorter for now so it won't take too long to simulate + cnt_time <= std_logic_vector(unsigned(cnt_time) + 1); + -- if (NCNT = 32) then -- Stop simulation at some point + -- done_seq <= '1'; + -- end if; + clk_delay(0); + end loop; + + wait for 10 us; + + cpu_print_msg("Simulation done"); + clk_delay(5); + done_seq <= '1'; + sim_done <= true; + wait; + + end process; + +end behave; + diff --git a/src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl b/src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl new file mode 100644 index 0000000..3ce3007 --- /dev/null +++ b/src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl @@ -0,0 +1,422 @@ +----------------------------------------------------------- +-- File : tb_pulse_channel_random_polynomials.vhd +----------------------------------------------------------- +-- +-- More complex testbench for the pulse channel. +-- +-- Description : Generates random polynomials and tests the pulse channel +-- Compare the output of the pulse channel with the output of a +-- floating-point reference model. +-- +---------------------------------------------------------- +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; +use ieee.std_logic_textio.all; +use std.textio.all; + +use ieee.math_real.all; + + +use work.std_iopak.all; +use work.qlaser_dacs_pulse_channel_pkg.all; + + +entity tb_pulse_channel_random_polynomials is +end tb_pulse_channel_random_polynomials; + +architecture verify of tb_pulse_channel_random_polynomials is + +------------------------------------------------------------------------ +-- Pulse Channel DUT signals +------------------------------------------------------------------------ +signal clk : std_logic; +signal reset : std_logic; +signal enable : std_logic; +signal start : std_logic; +signal cnt_time : std_logic_vector(23 downto 0); +signal busy : std_logic; +signal done_seq : std_logic; +signal cpu_wr : std_logic; +signal cpu_sel : std_logic; +signal cpu_addr : std_logic_vector(15 downto 0); +signal cpu_wdata : std_logic_vector(31 downto 0); +signal cpu_rdata : std_logic_vector(31 downto 0); +signal cpu_rdata_dv : std_logic; + +-- AXI-stream output interface +signal axis_tready : std_logic := '1'; -- Always ready +signal axis_tdata : std_logic_vector(15 downto 0); +signal axis_tvalid : std_logic; +signal axis_tlast : std_logic; + +------------------------------------------------------------------------ +-- Simulation signals +------------------------------------------------------------------------ +-- Halts simulation by stopping clock when set true +signal sim_done : boolean := false; + +-- Crystal clock freq expressed in MHz +constant CLK_FREQ_MHZ : real := 100.0; +-- Clock period +constant CLK_PER : time := integer(1.0E+6/(CLK_FREQ_MHZ)) * 1 ps; + +-- Block registers +constant ADR_RAM_PULSE : integer := 0; +constant ADR_RAM_WAVE : integer := 2048; + +signal direction : std_logic := '0'; +signal degrees : integer := 0; +signal times : integer := 0; +-- signal wave_values : real_array(0 to degrees-1); +signal wave_values : real; +signal wave_values_next : real; + + + +------------------------------------------------------------- +-- Delay +------------------------------------------------------------- +procedure clk_delay( + constant nclks : in integer +) is +begin + for I in 0 to nclks loop + wait until clk'event and clk ='0'; + end loop; +end; +---------------------------------------------------------------- +-- Print a string with no time or instance path. +---------------------------------------------------------------- +procedure cpu_print_msg( + constant msg : in string +) is +variable line_out : line; +begin + write(line_out, msg); + writeline(output, line_out); +end procedure cpu_print_msg; +------------------------------------------------------------- +-- CPU write procedure. Address in decimal. Data in hex +------------------------------------------------------------- +procedure cpu_write( + signal clk : in std_logic; + constant a : in integer; + constant d : in std_logic_vector(31 downto 0); + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +begin + wait until clk'event and clk='0'; + cpu_sel <= '1'; + cpu_wr <= '1'; + cpu_addr <= std_logic_vector(to_unsigned(a, 16)); + cpu_wdata <= std_logic_vector(d); + wait until clk'event and clk='0'; + cpu_sel <= '0'; + cpu_wr <= '0'; + cpu_addr <= (others=>'0'); + cpu_wdata <= (others=>'0'); + wait until clk'event and clk='0'; +end; +------------------------------------------------------------- +-- CPU write procedure. Address and Data in decimal +------------------------------------------------------------- +procedure cpu_write( + signal clk : in std_logic; + constant a : in integer; + constant d : in integer; + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +begin + cpu_write(clk, a , std_logic_vector(to_unsigned(d,32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata); +end; + +------------------------------------------------------------- +-- CPU write pulse definition RAM +-- Make fore 32-bit data write +------------------------------------------------------------- +procedure cpu_write_pulsedef( + signal clk : in std_logic; + + constant num_entry : in integer; + + -- TODO: Partial ? list of parameters, there could be more if need more features + constant pulsetime : in integer; -- Pulse time in clock cycles + constant timefactor : in real; -- Fixed point time scale factor + constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000" + constant wavestartaddr : in integer; -- Start address in waveform RAM + constant wavesteps : in integer; -- Number of steps in waveform rise and fall + constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall + + + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +-- Vectors for converted values +variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time +variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep +variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain +variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM +variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points +variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform +begin + -- Convert each field into its std_logic_vector equivalent + slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24)); + slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC_GAIN)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12)); + slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10)); + slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17)); + + + --etc, etc. + -- 4 writes. (Address is an integer) + cpu_write(clk, ADR_RAM_PULSE+num_entry , x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"0" & slv_wavesteps & x"0" & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+2) , slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + +end; + +------------------------------------------------------------- +-- Output comparison +------------------------------------------------------------- +procedure pulse_check( + signal clk : in std_logic; + + -- TODO: should this be real so that it can take the floating point value from the reference model? + constant exp_d : in real; + + signal axis_tdata : in std_logic_vector(15 downto 0); -- axi stream output data + signal axis_tvalid : in std_logic; -- axi_stream output data valid + signal axis_tlast : in std_logic; -- axi_stream output set on last data + signal axis_tready : out std_logic -- axi_stream ready from downstream module + +) is +variable v_bdone : boolean := false; +variable str_out : string(1 to 256); +variable diff : integer; +begin + wait until clk'event and clk='0'; + -- TODO: determine if we need any additional signals here + while (v_bdone = false) loop + wait until clk'event and clk='0'; + if (axis_tvalid = '1') then + if (real(to_integer(unsigned(axis_tdata))) /= exp_d) then + -- diff := abs(exp_d - real(to_integer(unsigned(axis_tdata)))); + fprint(str_out, "Read exp: 0x%s actual: 0x%s\n", to_string(exp_d,"%08X"), to_string(to_bitvector(axis_tdata),"%08X")); + report str_out severity error; + end if; + end if; + end loop; + wait until clk'event and clk='0'; + wait until clk'event and clk='0'; +end; + + +-- TODO: Add reference model for pulse channel + +-- TODO: write polynomial generator/solver +------------------------------------------------------------- +-- Polynomial Solver +-- Given a set of random coefficients and time stamps, output values for the polynomial +-- Assume the numbers of coefficients is the same as the number of time stamps which is the degrees number +------------------------------------------------------------- +-- procedure poly_gen( +-- signal clk : in std_logic; + +-- constant degrees : in integer; -- number of coefficients +-- signal direction : in std_logic; -- 0 = rising, 1 = falling +-- constant times : in integer; -- time stamp +-- constant coeff : in real -- coefficient + +-- -- signal coeffs : real_array(0 to degrees-1); +-- ) is +-- variable poly_sum : real := 0.0; +-- begin +-- -- wait until clk'event and clk='0'; +-- -- for i in 0 to degrees loop +-- -- poly_sum := poly_sum + coeffs(i) * times**i; +-- -- end loop; +-- -- poly_out <= poly_sum; +-- end; + +procedure poly_gen( + signal clk : in std_logic; + signal direction : in std_logic; -- 0 = rising, 1 = falling + constant degrees : in integer; -- number of coefficients + constant times : in integer; -- time stamp (should be real?) + constant coeff : in real_array; -- coefficient + constant offset : in real; -- offset, or the constant C in the polynomial. This value should be 0.0 for the first term + signal wave_values : out real +) is + variable poly_sum : real := 0.0; + variable time_prime : real := real(times) / 4096.0; -- x' = x/4096 +begin + wait until rising_edge(clk); + -- add from first to the Nth term. We always assume the zeroth term is 0 + for i in 1 to degrees loop + -- poly_sum := poly_sum + coeff(i - 1)*real(times)**i; + poly_sum := poly_sum + coeff(i - 1)*time_prime**i; + end loop; + -- wave_values <= poly_sum; + -- wave_values <= ((coeff(2)*real(times**2) + coeff(1)*real(times))/(real(degrees-1))) * real(2**16); -- for smaller test + wave_values <= ((poly_sum)/(real(degrees-1))) * real(2**16); -- out = (f{x'} / (N-1)) * ADC height + + -- wave_values <= SIN(real(times)); -- possible to use sine wave for testing +end; + +begin + ------------------------------------------------------------- + -- Unit Under Test + ------------------------------------------------------------- + u_dac_pulse : entity work.qlaser_dacs_pulse_channel + port map ( + clk => clk , -- in std_logic; + reset => reset , -- in std_logic; + + enable => enable , -- out std_logic; + start => start , -- out std_logic; + cnt_time => cnt_time , -- out std_logic_vector(23 downto 0); -- Set to '1' while SPI interface is busy + + busy => busy , -- out std_logic; -- Set to '1' while SPI interface is busy + done_seq => done_seq , -- in std_logic; -- Set to '1' when SPI sequence is done + + -- CPU interface + cpu_wr => cpu_wr , -- in std_logic; + cpu_sel => cpu_sel , -- in std_logic; + cpu_addr => cpu_addr(11 downto 0) , -- in std_logic_vector(11 downto 0); + cpu_wdata => cpu_wdata , -- in std_logic_vector(31 downto 0); + + cpu_rdata => cpu_rdata , -- out std_logic_vector(31 downto 0); + cpu_rdata_dv => cpu_rdata_dv , -- out std_logic; + + + -- AXI-Stream interface + axis_tready => axis_tready , -- in std_logic; -- Clock (50 MHz max) + axis_tdata => axis_tdata , -- out std_logic_vector(15 downto 0); + axis_tvalid => axis_tvalid , -- out std_logic; -- Master out, Slave in. (Data to DAC) + axis_tlast => axis_tlast -- out std_logic; -- Active low chip select (sync_n) + ); + + ------------------------------------------------------------- + -- Generate system clock. Halt when sim_done is true. + ------------------------------------------------------------- + pr_clk : process + begin + clk <= '0'; + wait for (CLK_PER/2); + clk <= '1'; + wait for (CLK_PER-CLK_PER/2); + if (sim_done=true) then + wait; + end if; + end process; + ------------------------------------------------------------- + -- Reset and drive CPU bus + ------------------------------------------------------------- + pr_main : process + -- Write to files + file f_out : text open write_mode is "wave_values.txt"; + variable line_var : line; + + -- "global" variables for base definitions of each pulses, all pulses are based on these but scaled/offset a bit + variable v_pulseaddr : integer := 0; -- manually set the pulse address, 0 to 255 + variable v_waveaddr : integer := 0; -- manually set the wave address, 0 to 2047 + variable v_pulsetime : integer := 0; -- For 24-bit pulse time + variable v_timefactor : real := 0.0; -- For 16-bit fixed point timestep + variable v_gainfactor : real := 0.0; -- For 16-bit fixed point gain + variable v_wavestartaddr : integer := 0; -- For 12-bit address i.e. 1024 point waveform RAM + variable v_wavesteps : integer := 0; -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points + variable v_wavetopwidth : integer := 0; -- For 17-bit number of clock cycles in top of waveform + + -- for RNG's + variable seed1 : positive; + variable seed2 : positive; + variable x : real; + variable y : real; + + variable offset : real; + variable v_coeffs : real_array(0 to 4095); + + begin + -- Reset + reset <= '1'; + enable <= '0'; + start <= '0'; + done_seq <= '0'; + cnt_time <= (others=>'0'); + + cpu_sel <= '0'; + cpu_wr <= '0'; + cpu_wdata <= (others=>'0'); + cpu_addr <= (others=>'0'); + + wave_values <= 0.0; + wave_values_next <= 0.0; + + cpu_print_msg("Simulation start"); + clk_delay(5); + reset <= '0'; + + clk_delay(5); + enable <= '1'; + + clk_delay(20); + + v_coeffs := (others => 0.0); + seed1 := 2045; + seed2 := 1024; + -- TODO: write to the pulse definition RAM + degrees <= 2; + -- construct an array contains random coefficients + for i in 0 to 4095 loop + uniform(seed1, seed2, x); + v_coeffs(i) := x; + end loop; + + offset := 0.0; + for i in 0 to 2047 loop + times <= i; + poly_gen(clk, direction, degrees, times, v_coeffs, offset, wave_values); + + write(line_var, real'image(wave_values)); + writeline(f_out, line_var); + end loop; + + degrees <= 3; + clk_delay(1); + poly_gen(clk, direction, degrees, times + 1, v_coeffs, offset, wave_values_next); + -- clk_delay(5); + -- -- construct an array contains random coefficients + -- for i in 0 to degrees loop + -- uniform(seed1, seed2, x); + -- v_coeffs(i) := x; + -- end loop; + + offset := wave_values - wave_values_next; -- offset is the difference between the last two values + -- offset := 0; + for i in 2048 to 4095 loop + times <= i; + poly_gen(clk, direction, degrees, times, v_coeffs, offset, wave_values); + + write(line_var, real'image(wave_values)); + writeline(f_out, line_var); + end loop; + + -- End of test + cpu_print_msg("Simulation done"); + clk_delay(5); + done_seq <= '1'; + sim_done <= true; + wait; + end process; +end verify; diff --git a/src/python/genwave.py b/src/python/genwave.py new file mode 100644 index 0000000..e11ec5b --- /dev/null +++ b/src/python/genwave.py @@ -0,0 +1,26 @@ +import matplotlib.pyplot as plt +import numpy as np + +def generate_wave(length=100, amplitude=1, num_waves=3): + x = np.linspace(0, 10, length) # Create a linearly spaced array + wave = np.zeros(length) # Initialize wave array + + for _ in range(num_waves): + phase = np.random.rand() * 2 * np.pi # Random phase + frequency = np.random.rand() * 2 # Random frequency + amplitude = np.random.rand() * amplitude # Random amplitude + + wave += amplitude * np.sin(2 * np.pi * frequency * x + phase) # Add random sine wave + + return wave + +def plot_wave(wave): + plt.plot(wave) + plt.xlabel('Time') + plt.ylabel('Amplitude') + plt.title('Randomly Generated Wave') + plt.show() + +if __name__ == "__main__": + wave = generate_wave() + plot_wave(wave) diff --git a/src/python/polytest.py b/src/python/polytest.py new file mode 100644 index 0000000..4ed6c6b --- /dev/null +++ b/src/python/polytest.py @@ -0,0 +1,48 @@ +import matplotlib +import matplotlib.pyplot as plt +import numpy as np +matplotlib.use("WXAgg") # force use wxPython as backend UI for plotting + +def generate_polynomial(coefficients, times, degree): + """Generate polynomial values. + + Args: + coefficients (list): List of coefficients for the polynomial, from highest degree to constant term. + times (list): List of x-values at which to evaluate the polynomial. + degree (int): Degree of the polynomial (not used in computation but included for clarity). + + Returns: + list: Polynomial values at the given times. + """ + + # Calculate polynomial value for each time + polynomial_values = [] + for t in times: + value = 0 + for i, coeff in enumerate(coefficients): + value += coeff * (t ** (degree - i)) + polynomial_values.append(value) + + return polynomial_values + + +def plot_wave(wave): + plt.plot(wave) + plt.xlabel('Time') + plt.ylabel('Amplitude') + plt.title('Randomly Generated Wave') + plt.show() + + +wavesize = 10 + +inputData = np.random.rand(wavesize)*10 + +times = np.arange(0, wavesize, 1) + +degree = 3 + + + +# plot_wave(inputData) + diff --git a/src/python/scalecheck.py b/src/python/scalecheck.py new file mode 100644 index 0000000..b554c39 --- /dev/null +++ b/src/python/scalecheck.py @@ -0,0 +1,34 @@ +# simple calculation of the scale factor +import numpy as np + +START = 1 +LENGTH = 10 +FACTOR = 2.25 + +END = START+LENGTH +addr_raw = np.arange(START, END) + +addr_scaled = np.zeros(len(addr_raw)) + +addr = START + +# for i in range(len(addr_raw)): +# addr_scaled[i] = addr_raw[i] * FACTOR + +# print(np.floor(addr_scaled)) + +for i in range(LENGTH): + print(i * FACTOR, end=" ") + # addr_scaled[i] = (addr + i) * FACTOR + # addr += 1 + +print() + +# now decrement it back +for i in range(LENGTH - 1, 0, -1): + # addr -= 1 + # addr_scaled[i] = (addr - i) * FACTOR + print(i * FACTOR, end=" ") + + +print() diff --git a/src/sandbox/qlaser_dacs_pulse_channel..vhdl.other b/src/sandbox/qlaser_dacs_pulse_channel..vhdl.other new file mode 100644 index 0000000..260f72a --- /dev/null +++ b/src/sandbox/qlaser_dacs_pulse_channel..vhdl.other @@ -0,0 +1,530 @@ +--------------------------------------------------------------- +-- File : qlaser_dacs_pulse_channel.vhd +-- Description : Single channel of pulse output +---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.qlaser_pkg.all; +use work.qlaser_dacs_pulse_channel_pkg.all; + +entity qlaser_dacs_pulse_channel is +port ( + reset : in std_logic; + clk : in std_logic; + + enable : in std_logic; -- Set when DAC interface is running + start : in std_logic; -- Set when pulse generation sequence begins (trigger) + cnt_time : in std_logic_vector(23 downto 0); -- Time since trigger. + + busy : out std_logic; -- Status signal + + -- CPU interface + cpu_addr : in std_logic_vector(11 downto 0); -- Address input + cpu_wdata : in std_logic_vector(31 downto 0); -- Data input + cpu_wr : in std_logic; -- Write enable + cpu_sel : in std_logic; -- Block select + cpu_rdata : out std_logic_vector(31 downto 0); -- Data output + cpu_rdata_dv : out std_logic; -- Acknowledge output + + -- AXI-stream output + axis_tready : in std_logic; -- axi_stream ready from downstream module + axis_tdata : out std_logic_vector(15 downto 0); -- axi stream output data + axis_tvalid : out std_logic; -- axi_stream output data valid + axis_tlast : out std_logic -- axi_stream output set on last data +); +end entity; + +--------------------------------------------------------------------------- +-- Single channel pulse generator with two RAMs +--------------------------------------------------------------------------- +architecture channel of qlaser_dacs_pulse_channel is +-- Signal declarations for pulse RAM +signal ram_pulse_we : std_logic_vector( 0 downto 0); -- Write enable for pulse RAM +signal ram_pulse_addra : std_logic_vector( 9 downto 0); -- Address for pulse RAM +signal ram_pulse_dina : std_logic_vector(31 downto 0); -- Data for pulse RAM +signal ram_pulse_douta : std_logic_vector(31 downto 0); -- Data out from pulse RAM +signal ram_pulse_addrb : std_logic_vector( 9 downto 0); -- Address for pulse RAM +signal ram_pulse_doutb : std_logic_vector(31 downto 0); -- Data out from pulse RAM + +-- Signal declarations for waveform RAM +signal ram_waveform_wea : std_logic_vector( 0 downto 0); -- Write enable for waveform RAM +signal ram_waveform_addra : std_logic_vector(10 downto 0); -- Address for waveform RAM +signal ram_waveform_dina : std_logic_vector(31 downto 0); -- Data for waveform RAM +signal ram_waveform_douta : std_logic_vector(31 downto 0); -- Data out from waveform RAM +signal ram_waveform_addrb : std_logic_vector(11 downto 0); -- Address for waveform RAM +signal ram_waveform_doutb : std_logic_vector(15 downto 0); -- Data out from waveform RAM + +-- State variable type declaration for main state machine +-- TODO: add a fetch state to get four address from pd ram? +type t_sm_state is ( + S_RESET, -- Wait for 'enable'. Stay here until JESD interface is up and running, + S_IDLE, -- Wait for 'start' + S_WAIT, -- Wait for cnt_time, external input, to match pulse position RAM output + S_LOAD, -- Load the pulse channel RAM addresses and start the waveform output + S_HOLD, -- Hold the last pulse definition address and output its data + S_WAVE_UP, -- Output the rising edge of a waveform + S_WAVE_FLAT,-- Output the flat top part of a waveform + S_WAVE_DOWN -- Output the falling edge of a waveform +); +signal sm_state : t_sm_state; +signal sm_wavedata : std_logic_vector(15 downto 0); -- Waveform RAM data +signal sm_wavedata_dv : std_logic; -- Signal to indicate that waveform RAM data is valid +signal sm_busy : std_logic; -- Signal to indicate that s.m. is not idle +signal cnt_wave_len : unsigned(C_BITS_ADDR_LENGTH - 1 downto 0); -- Counter used for incremnet/decrement wave table addresses +signal cnt_wave_top : unsigned(C_BITS_ADDR_TOP - 1 downto 0); -- Counter for the flat top of the waveform + +-- Misc signals +signal cpu_rdata_dv_e1 : std_logic; +signal cpu_rdata_dv_e2 : std_logic; +signal cpu_rdata_ramsel_d1 : std_logic; +signal cpu_rdata_ramsel_d2 : std_logic; + +signal pc : std_logic_vector(C_BITS_ADDR_PULSE - 1 downto 0); -- pulse counter, used to count the number of pulses generated + +---------------------------------------------------------------- +-- Assign values from the pulse definition ram to regfiles (?) with the following: +-- 1. Start time 24 bits. [23:0] +-- 2. Wave start addr 12 bit at [11:0] +-- Wave length 10-bit at [25:16] +-- 3. Scale factors 16, 16. [31:16] [15:0] +-- 4. Flat-top 17-bit. [16:0] +---------------------------------------------------------------- +signal reg_start_time : std_logic_vector(23 downto 0); -- first register which stores the pulse's start time +signal reg_pulse_sizes : std_logic_vector(31 downto 0); -- second register which stores the pulse's length, the bit width should increase with the amount of addresses the wavetable has, and its start address +-- TODO: replace the above one w/ below two +signal reg_wave_start_addr : std_logic_vector(11 downto 0); -- the start address of the wavetable +signal reg_wave_length : unsigned(9 downto 0); -- the length of the wavetable + +signal reg_pulse_factors : std_logic_vector(31 downto 0); -- third register which stores the pulse's amplitude and time scale factors +-- TODO: replace the above one w/ below two +signal reg_scale_gain : unsigned(15 downto 0); -- scale factor for the gain, amplitude +signal reg_scale_time : unsigned(15 downto 0); -- scale factor for the time, length + +signal reg_flattop : std_logic_vector(16 downto 0); -- fourth register which stores the pulse's flat top value + + + +-- Pipeline delays +signal start_d1 : std_logic; +signal enable_d1 : std_logic; + +begin + + ---------------------------------------------------------------- + -- Pulse Definition Block RAM. + -- Synch write, Synch read + -- Port A is for CPU read/write. 1024x32-bit + -- Port B is for pulse time data output. 1024x32-bit + ---------------------------------------------------------------- + u_ram_pulse : entity work.bram_pulse_definition + port map( + -- Port A CPU Bus + clka => clk, -- input std_logic + wea => ram_pulse_we, -- input slv( 0 to 0 ) + addra => ram_pulse_addra, -- input slv( 9 downto 0 ) + dina => ram_pulse_dina, -- input slv( 31 downto 0 ) + douta => ram_pulse_douta, -- output slv( 31 downto 0 ), + -- Port B waveform input + clkb => clk, + web => (others=>'0'), + addrb => ram_pulse_addrb, -- input slv( 9 downto 0 ) + dinb => (others=>'0'), + doutb => ram_pulse_doutb -- output slv( 31 downto 0 ) + ); + + + ---------------------------------------------------------------- + -- Waveform table Block RAM. + -- Synch write, Synch read + -- Port A is for CPU read/write. 2048x32-bit + -- Port B is for waveform data. 4096x16-bit + ---------------------------------------------------------------- + u_ram_waveform : entity work.bram_waveform + port map ( + -- Port A CPU Bus + clka => clk , -- input std_logic + wea => ram_waveform_wea , -- input slv(0 downto 0) + addra => ram_waveform_addra , -- input slv(10 downto 0) + dina => ram_waveform_dina , -- input slv(31 downto 0) + douta => ram_waveform_douta , -- output slv(31 downto 0) + + -- Port B waveform output + clkb => clk , -- input std_logic + web => (others=>'0') , -- input slv(0 downto 0) + addrb => ram_waveform_addrb , -- input slv(11 downto 0) + dinb => (others=>'0') , -- input slv(15 downto 0) + doutb => ram_waveform_doutb -- output slv(15 downto 0) + ); + + ---------------------------------------------------------------- + -- CPU Read/Write RAM + -- MSB of cpu_addr is used to select one of the two RAMs + -- to read/write, and the remainder are a 9-bit or 4-bit RAM address. + ---------------------------------------------------------------- + pr_ram_rw : process (reset, clk) + begin + if (reset = '1') then + + ram_pulse_addra <= (others=>'0'); + ram_pulse_dina <= (others=>'0'); + ram_pulse_we <= (others=>'0'); + + ram_waveform_wea <= (others=>'0'); + ram_waveform_addra <= (others=>'0'); + ram_waveform_dina <= (others=>'0'); + + cpu_rdata <= (others=>'0'); + cpu_rdata_dv <= '0'; + cpu_rdata_dv_e1 <= '0'; + cpu_rdata_dv_e2 <= '0'; + cpu_rdata_ramsel_d1 <= '0'; + cpu_rdata_ramsel_d2 <= '0'; + + elsif rising_edge(clk) then + + + ------------------------------------------------- + -- CPU writing RAM + ------------------------------------------------- + if (cpu_wr = '1') and (cpu_sel = '1') then + + -- 0 for pulse definition, 1 for waveform table + if (cpu_addr(C_RAM_SELECT) = '1') then + + ram_pulse_addra <= (others=>'0'); + ram_pulse_dina <= (others=>'0'); + ram_pulse_we <= (others=>'0'); + + ram_waveform_wea(0) <= '1'; + ram_waveform_addra <= cpu_addr(10 downto 0); + ram_waveform_dina <= cpu_wdata; + + else + + ram_pulse_addra <= cpu_addr(9 downto 0); + ram_pulse_dina <= cpu_wdata; + ram_pulse_we(0) <= '1'; + ram_waveform_wea <= (others=>'0'); + ram_waveform_addra <= (others=>'0'); + ram_waveform_dina <= (others=>'0'); + + end if; + + cpu_rdata_dv_e1 <= '0'; + cpu_rdata_dv_e2 <= '0'; + cpu_rdata_ramsel_d1 <= '0'; + cpu_rdata_ramsel_d2 <= '0'; + + + ------------------------------------------------- + -- CPU read + ------------------------------------------------- + elsif (cpu_wr = '0') and (cpu_sel = '1') then + + if (cpu_addr(C_RAM_SELECT) = '1') then -- Waveform + ram_pulse_addra <= (others=>'0'); + ram_waveform_addra <= cpu_addr(10 downto 0); + else -- Pulse + ram_pulse_addra <= cpu_addr(9 downto 0); + ram_waveform_addra <= (others=>'0'); + end if; + + ram_pulse_we <= (others=>'0'); + ram_waveform_wea(0) <= '0'; + + cpu_rdata_dv_e2 <= '1'; -- DV for cycle, when RAM output occurs + cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle + cpu_rdata_ramsel_d1 <= cpu_addr(C_RAM_SELECT); -- Save the select bit one cycle later + cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1; + + else + ram_pulse_addra <= (others=>'0'); + ram_pulse_we <= (others=>'0'); + ram_waveform_addra <= (others=>'0'); + ram_waveform_wea(0) <= '0'; + + cpu_rdata_dv_e2 <= '0'; + cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle + cpu_rdata_ramsel_d1 <= '0'; + cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1; + + end if; + + ------------------------------------------------- + -- Output the delayed RAM data + -- This adds a pipeline delay to the cpu_rdata_dv to account for + -- the delay in reading data from the RAM + ------------------------------------------------- + if (cpu_rdata_dv_e1 = '1') then + + cpu_rdata_dv <= '1'; + + -- Select source of output data + if (cpu_rdata_ramsel_d2 = '1') then -- Output is from waveform table + cpu_rdata <= ram_waveform_douta; + + elsif (cpu_rdata_ramsel_d2 = '0') then + cpu_rdata <= ram_pulse_douta; + end if; + + else + cpu_rdata <= (others=>'0'); + cpu_rdata_dv <= '0'; + end if; + + end if; + + end process; + + ---------------------------------------------------------------- + -- State machine: + -- Compares cnt_time input against current output from pulse position RAM. + -- When values match iti incremnts the pulse postion RAM address to + -- retrieve the next pulse position and also starts reading the + -- entire waveform table, one value every clock cycle, until it reaches the end. + -- Once the pulse is complete it waits for the next cnt_time match. + -- Repeat until all pulse position RAM times have triggered a pulse output + -- or until the maximum counter time has been reached. + ---------------------------------------------------------------- + pr_sm : process (reset, clk) + variable v_amp_factor : std_logic_vector(C_BITS_GAIN_FACTOR - 1 downto 0); + variable v_time_factor : std_logic_vector(C_BITS_TIME_FACTOR - 1 downto 0); + + -- Temp variables for waveform output + variable v_ram_waveform_doutb_multiplied : std_logic_vector(C_BITS_GAIN_FACTOR + 15 downto 0); + begin + if (reset = '1') then + + sm_state <= S_IDLE; -- TODO: Eric: Should this be S_RESET since we reset the JEDS interface as well? + ram_pulse_addrb <= (others=>'0'); + ram_waveform_addrb <= (others=>'0'); + + sm_wavedata <= (others=>'0'); + sm_wavedata_dv <= '0'; + sm_busy <= '0'; + + reg_start_time <= (others=>'0'); + reg_pulse_sizes <= (others=>'0'); + reg_pulse_factors <= (others=>'0'); + reg_flattop <= (others=>'0'); + reg_scale_gain <= (others=>'0'); + reg_scale_time <= (others=>'0'); + + pc <= (others=>'0'); + cnt_wave_len <= (others=>'0'); + cnt_wave_top <= (others=>'0'); + elsif rising_edge(clk) then + + + -- Pipeline delays to use for rising edge detection + enable_d1 <= enable; + start_d1 <= start; + + -- Default + sm_wavedata <= (others=>'0'); + sm_wavedata_dv <= '0'; + + + + ------------------------------------------------------------------------ + -- Main state machine + ------------------------------------------------------------------------ + case sm_state is + + ------------------------------------------------------------------------ + -- Wait for rising edge of enable + -- This is set when the JESD interface is aligned and functional. + -- Send a zero value to initialize the DAC then go to idle. + ------------------------------------------------------------------------ + when S_RESET => + + if (enable = '1') and (enable_d1 = '0') then + sm_wavedata <= (others=>'0'); + sm_wavedata_dv <= '1'; + sm_state <= S_IDLE; + end if; + sm_busy <= '0'; + + ------------------------------------------------------------------------ + -- Wait for rising edge of 'start'. + -- No data output. + ------------------------------------------------------------------------ + when S_IDLE => + + if (start = '1') and (start_d1 = '0') then + sm_state <= S_LOAD; + sm_busy <= '1'; + else + sm_busy <= '0'; + end if; + + ------------------------------------------------------------------------ + -- Load four addresses from pulse definition RAM into four 32 bits regesters + ------------------------------------------------------------------------ + when S_LOAD => + -- TODO: Eric: does is needed here? or should be inside the if-else loops + -- Load the pulse channel RAM addresses and start the waveform output + sm_busy <= '1'; + -- Pipline the pulse definition address + + -- TODO: is it better to make a counter to count the quarter or just mod 4? + -- TODO: maybe C-slow around the pulse ram to get it down to 1 cycle?? + if (unsigned(ram_pulse_addrb) mod 4 = 0) then + ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 1); + sm_state <= S_LOAD; + -- first quarter of the pulse definition, no register is loaded + -- reg_start_time <= ram_pulse_doutb; + + elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then + ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 2); + sm_state <= S_LOAD; + -- reg_pulse_sizes <= ram_pulse_doutb; + -- second quarter of the pulse definition, the start time is loaded + reg_start_time <= ram_pulse_doutb; + + + elsif (unsigned(ram_pulse_addrb) mod 4 = 2) then + ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 3); + sm_state <= S_LOAD; + -- reg_pulse_factors <= ram_pulse_doutb; + -- third quarter of the pulse definition, the length and start address of the wavetable are loaded + reg_pulse_sizes <= ram_pulse_doutb; + + + elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then + -- ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 4); + sm_state <= S_WAIT; -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state + -- hold the last pulse definition address as it will be used in the next state + -- reg_flattop <= ram_pulse_doutb; + pc <= std_logic_vector(unsigned(pc) + C_PC_INCR); -- incremnet the pulse counter and start waiting to output the wave + -- forth quarter of the pulse definition, the scale factors are loaded + reg_pulse_factors <= ram_pulse_doutb; + + reg_scale_gain <= unsigned(ram_pulse_doutb(31 downto 16)); + reg_scale_time <= unsigned(ram_pulse_doutb(15 downto 0)); + + + end if; + + -- ------------------------------------------------------------------------ + -- -- Hold the last pulse definition address and output its data for one more clock cycle + -- ------------------------------------------------------------------------ + -- when S_HOLD => + -- sm_state <= S_LOAD; + + ------------------------------------------------------------------------ + -- Wait for cnt_time, external input, to match pulse position RAM output + -- Return to idle state if max time is reached. Output waveform value zero. + ------------------------------------------------------------------------ + when S_WAIT => + -- read the last word of the pulse definition, the flat top value + reg_flattop <= ram_pulse_doutb; + -- Start to output wave and increment pulse position RAM address + if (reg_start_time(C_START_TIME - 1 downto 0) = cnt_time) then + sm_state <= S_WAVE_UP; + -- set the wavetable's address to the starting address defined from the pulse ram + ram_waveform_addrb <= reg_pulse_sizes(C_BITS_ADDR_START - 1 downto 0); + -- reset the wave lenth counter + cnt_wave_len <= (others=>'0'); + -- parse the scale factors from reg_pulse_factors register + v_time_factor := reg_pulse_factors(C_BITS_TIME_FACTOR - 1 downto 0); + v_amp_factor := reg_pulse_factors(31 downto 16); + elsif (cnt_time = X"FFFFFF") then + sm_state <= S_IDLE; + end if; + + + ------------------------------------------------------------------------ + -- Output the raising edge of a waveform + -- Hold the last address when complete + ------------------------------------------------------------------------ + when S_WAVE_UP => + -- Check if is end of rise of the waveform, and hold the address + + -- TODO: convert the numbers below to constaint. right now just make sure I'm not confused + if (cnt_wave_len = reg_wave_length) then + sm_state <= S_WAVE_FLAT; + -- reset counters for transitions + cnt_wave_len <= (others=>'0'); + cnt_wave_top <= (others=>'0'); + -- TODO: toSara: do we need to consider the even of no flat top? + else + cnt_wave_len <= cnt_wave_len + 1; + ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1); + end if; + + v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain); + sm_wavedata <= std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain)(31 downto 16); + sm_wavedata_dv <= '1'; + + ------------------------------------------------------------------------ + -- Hold the last address and output its data + -- decrement from this address when finished waiting + ------------------------------------------------------------------------ + when S_WAVE_FLAT => + -- count the 17-bit flat top, if the counter reaches the flat top value, then go to the next state + if (cnt_wave_top = reg_flattop(C_BITS_ADDR_TOP - 1 downto 0)) then + sm_state <= S_WAVE_DOWN; + -- reset the counter for the next transition + cnt_wave_top <= (others=>'0'); + else + cnt_wave_top <= std_logic_vector(unsigned(cnt_wave_top) + 1); + end if; + v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * unsigned(v_amp_factor)); + sm_wavedata <= std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain)(31 downto 16); ; + sm_wavedata_dv <= '1'; + + ------------------------------------------------------------------------ + -- Output the falling edge of a waveform + -- Hold the start address when complete + ------------------------------------------------------------------------ + when S_WAVE_DOWN => + + -- End of waveform? + -- TODO: convert the numbers below to constaint. right now just make sure I'm not confused + if (cnt_wave_len = reg_wave_length) then + + -- If the end of the pulse table is reached then go to idle, increment pulse address for the next waveform otherwise + if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_LEN_PULSE-1, C_BITS_ADDR_PULSE))) then + ram_pulse_addrb <= (others=>'0'); + pc <= (others=>'0'); + sm_state <= S_IDLE; + + else -- increment pulse address for the next waveform + ram_pulse_addrb <= pc; + -- the above line will now happen in the load state + -- pc <= std_logic_vector(unsigned(pc) + C_PC_INCR); + sm_state <= S_LOAD; + end if; + + -- Output waveform from RAM with decremented address + else + cnt_wave_len <= cnt_wave_len + 1; + ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - 1); + end if; + sm_wavedata <= std_logic_vector(unsigned(ram_waveform_doutb) * reg_scale_gain)(31 downto 16); + sm_wavedata_dv <= '1'; + + ------------------------------------------------------------------------ + -- Default + ------------------------------------------------------------------------ + when others => + sm_state <= S_IDLE; + + end case; + end if; + end process; + + -- AXI-Stream output. + -- TBD: This should come from a FIFO + -- TODO: the bits are not correct, should be top bits (C_BITS_GAIN_FACTOR + 16 downto C_BITS_GAIN_FACTOR), but for now just make it this way so modelsim can simulate + -- TODO: apply scaling factor to the output + axis_tdata <= sm_wavedata; -- axi stream output data, this output should be multiplied by the gain factor, then take the top 16 bits + axis_tvalid <= sm_wavedata_dv; -- axi_stream output data valid + + -- TBD : Generate in state machine? + axis_tlast <= '0'; -- axi_stream output last + +end channel; \ No newline at end of file diff --git a/src/sandbox/qlaser_dacs_pulse_channel.vhdl b/src/sandbox/qlaser_dacs_pulse_channel.vhdl new file mode 100644 index 0000000..3cc2ce1 --- /dev/null +++ b/src/sandbox/qlaser_dacs_pulse_channel.vhdl @@ -0,0 +1,606 @@ +--------------------------------------------------------------- +-- File : qlaser_dacs_pulse_channel.vhd +-- Description : Single channel of pulse output +---------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.qlaser_pkg.all; + +entity qlaser_dacs_pulse_channel is +port ( + reset : in std_logic; + clk : in std_logic; + + enable : in std_logic; -- Set when DAC interface is running + start : in std_logic; -- Set when pulse generation sequence begins (trigger) + cnt_time : in std_logic_vector(23 downto 0); -- Time since trigger. + + busy : out std_logic; -- Status signal + + -- CPU interface + cpu_addr : in std_logic_vector( 9 downto 0); -- Address input + cpu_wdata : in std_logic_vector(31 downto 0); -- Data input + cpu_wr : in std_logic; -- Write enable + cpu_sel : in std_logic; -- Block select + cpu_rdata : out std_logic_vector(31 downto 0); -- Data output + cpu_rdata_dv : out std_logic; -- Acknowledge output + + -- AXI-stream output + axis_tready : in std_logic; -- axi_stream ready from downstream module + axis_tdata : out std_logic_vector(15 downto 0); -- axi stream output data + axis_tvalid : out std_logic; -- axi_stream output data valid + axis_tlast : out std_logic -- axi_stream output set on last data +); +end entity; + + +---------------------------------------------------------------- +-- Single channel pulse generator with two RAMs and a FIFO +---------------------------------------------------------------- +architecture rtl of qlaser_dacs_pulse_channel is + +-- RAM, pulse position, CPU port, read/write +constant C_NUM_PULSE : integer := 16; -- Number of output data values from pulse RAM (16x24-bit) +signal ram_pulse_addra : std_logic_vector( 3 downto 0); -- 16 entry RAM +signal ram_pulse_dina : std_logic_vector(95 downto 0); +signal ram_pulse_douta : std_logic_vector(95 downto 0); +signal ram_pulse_douta_d1 : std_logic_vector(95 downto 0); -- Delay distrib RAM output to match pipeline of Block RAM +signal ram_pulse_we : std_logic; + +-- RAM, pulse position, from state machine +constant C_BITS_GAIN_FACTOR : integer := 16; -- Number of bits in gain table +constant C_BITS_TIME_FACTOR : integer := 16; -- Number of bits in time table +constant C_BITS_TIME_INT : integer := 14; -- Starting bit for time integer part of the time factor, counting from MSB +constant C_BITS_TIME_FRAC : integer := 5; -- Starting bit for time fractional part of the time factor, counting from MSB +constant C_BITS_ADDR_START : integer := 10; -- Number of bits for starting address +constant C_BITS_ADDR_LENGTH : integer := 10; -- Number of bits for length address used by an edge of a pulse +constant C_BITS_ADDR_TOP : integer := 17; -- Number of bits for the "flat top", the top of the pulse +signal cnt_wave_top : std_logic_vector( C_BITS_ADDR_TOP - 1 downto 0); -- Counter for the top of the waveform +signal ram_pulse_addrb : std_logic_vector( 3 downto 0); +signal ram_pulse_doutb : std_logic_vector(95 downto 0); + +signal cpu_rdata_dv_e1 : std_logic; +signal cpu_rdata_dv_e2 : std_logic; +signal cpu_rdata_ramsel_d1 : std_logic; +signal cpu_rdata_ramsel_d2 : std_logic; + +signal cpu_wdata_top : std_logic_vector(31 downto 0); -- Top 32 bits of CPU write data (95:64) +signal cpu_wdata_mid : std_logic_vector(31 downto 0); -- Middle 32 bits of CPU write data (63:32) + +-- Waveform RAM port connections. +-- NOTE: Port A is 32-bit data, port B is 16-bit +constant C_LENGTH_WAVEFORM : integer := 1024; -- Number of output data values from waveform RAM (1024x16-bit) +constant C_BITS_ADDR_WAVE : integer := 10; -- Number of bits in address for waveform RAM +signal ram_waveform_ena : std_logic; +signal ram_waveform_wea : std_logic_vector( 0 downto 0); +signal ram_waveform_addra : std_logic_vector( 8 downto 0); +signal ram_waveform_dina : std_logic_vector(31 downto 0); +signal ram_waveform_douta : std_logic_vector(31 downto 0); + +signal ram_waveform_enb : std_logic := '0'; +signal ram_waveform_web : std_logic_vector( 0 downto 0) := (others=>'0'); +signal ram_waveform_addrb : std_logic_vector( 9 downto 0); +signal ram_waveform_dinb : std_logic_vector(15 downto 0) := (others=>'0'); +signal ram_waveform_doutb : std_logic_vector(15 downto 0); + + +-- State variable type declaration for main state machine +type t_sm_state is ( + S_RESET, -- Wait for 'enable'. Stay here until JESD interface is up and running, + S_IDLE, -- Wait for 'start' + S_WAIT, -- Wait for cnt_time, external input, to match pulse position RAM output + S_WAVE_UP, -- Output the rising edge of a waveform + S_WAVE_FLAT,-- Output the flat top part of a waveform + S_WAVE_DOWN -- Output the falling edge of a waveform +); +signal sm_state : t_sm_state; +signal sm_wavedata : std_logic_vector(15 downto 0); -- Waveform RAM data +signal sm_wavedata_dv : std_logic; -- Signal to indicate that waveform RAM data is valid +signal sm_busy : std_logic; -- Signal to indicate that s.m. is not idle + + +---- FIFO port connections +--signal fifo_wr_en : std_logic; +--signal fifo_full : std_logic; +--signal fifo_empty : std_logic; +--signal fifo_wr_rst_busy : std_logic; +--signal fifo_rd_rst_busy : std_logic; +--signal fifo_rd_en : std_logic; +---- FIFO status signals for debug purpose +--signal fifo_wr_ack : std_logic; +--signal fifo_overflow : std_logic; +--signal fifo_valid : std_logic; +--signal fifo_underflow : std_logic; + +-- Pipeline delays +signal start_d1 : std_logic; +signal enable_d1 : std_logic; + +begin + + busy <= sm_busy; + + ---------------------------------------------------------------- + -- Distributed RAM to hold 16 24-bit Pulse start times. + -- Synch write, Asynch read + -- Port A is for CPU read/write. 16x24-bit + -- Port B is for pulse time data output. 16x24-bit + ---------------------------------------------------------------- + u_ram_pulse : entity work.bram_pulseposition + port map( + clk => clk , -- input std_logic + a => ram_pulse_addra , -- input slv[3:0] + d => ram_pulse_dina , -- input slv[95 downto 0] + we => ram_pulse_we , + spo => ram_pulse_douta , -- output slv(95 downto 0] + + dpra => ram_pulse_addrb , -- input slv[3:0] + dpo => ram_pulse_doutb -- output slv(95 downto 0) + ); + + + ---------------------------------------------------------------- + -- Waveform table Block RAM. + -- Synch write, Synch read + -- Port A is for CPU read/write. 512x32-bit + -- Port B is for waveform data. 1024x16-bit + ---------------------------------------------------------------- + u_ram_waveform : entity work.bram_waveform + port map ( + -- Port A CPU Bus + clka => clk , -- input std_logic + ena => ram_waveform_ena , -- input std_logic + wea => ram_waveform_wea , -- input slv(0 downto 0) + addra => ram_waveform_addra , -- input slv(8 downto 0) + dina => ram_waveform_dina , -- input slv(31 downto 0) + douta => ram_waveform_douta , -- output slv(31 downto 0) + + -- Port B waveform output + clkb => clk , -- input std_logic + enb => ram_waveform_enb , -- input std_logic + web => (others=>'0') , -- input slv(0 downto 0) + addrb => ram_waveform_addrb , -- input slv(9 downto 0) + dinb => (others=>'0') , -- input slv(15 downto 0) + doutb => ram_waveform_doutb -- output slv(15 downto 0) + ); + + + + ---------------------------------------------------------------- + -- State machine: + -- Compares cnt_time input against current output from pulse position RAM. + -- When values match iti incremnts the pulse postion RAM address to + -- retrieve the next pulse position and also starts reading the + -- entire waveform table, one value every clock cycle, until it reaches the end. + -- Once the pulse is complete it waits for the next cnt_time match. + -- Repeat until all pulse position RAM times have triggered a pulse output + -- or until the maximum counter time has been reached. + ---------------------------------------------------------------- + pr_sm : process (reset, clk) + -- TODO: those bitwidth are not correct, we could optimize it later and find out how many bits each variable should be. But for now just make it big + variable v_flattop : std_logic_vector(C_BITS_ADDR_TOP - 1 downto 0); -- wait times (flat_top), managed by an internal counter process sm_top_counter unter state S_WAVE_TOP + variable v_addr_length : std_logic_vector(C_BITS_ADDR_LENGTH - 1 downto 0); -- number of points/addresses used by the pulse edge, the bit width should increase with the amount of addresses the wavetable has + variable v_addr_start : std_logic_vector(C_BITS_ADDR_START - 1 downto 0); -- start address of the pulse edge data in the Waveform RAM, the bit width should increase with the amount of address the wavetable has. + variable v_addr_end : std_logic_vector(C_BITS_ADDR_START - 1 downto 0); -- end address of the pulse edge data in the Waveform RAM, the bit width should align with the bit width of v_addr_start + variable v_amplitude_factor : std_logic_vector(C_BITS_GAIN_FACTOR - 1 downto 0); -- pulse edge amplitude scale factor + variable v_time_factor : std_logic_vector(C_BITS_TIME_FACTOR - 1 downto 0); -- pulse edge time scale factor + variable v_cnt_time : std_logic_vector(23 downto 0); -- counter for the time, the bit width should increase with the amount of addresses the wavetable has + + variable v_ram_waveform_addrb : unsigned(95 downto 0); + begin + if (reset = '1') then + + sm_state <= S_IDLE; -- TODO: Eric: Should this be S_RESET since we reset the JEDS interface as well? + ram_pulse_addrb <= (others=>'0'); + ram_waveform_addrb <= (others=>'0'); + + sm_wavedata <= (others=>'0'); + sm_wavedata_dv <= '0'; + sm_busy <= '0'; + ram_waveform_enb <= '0'; + + elsif rising_edge(clk) then + + -- Pipeline delays to use for rising edge detection + enable_d1 <= enable; + start_d1 <= start; + + -- Default + sm_wavedata <= (others=>'0'); + sm_wavedata_dv <= '0'; + + -- Actively read pulse definition RAM and update the variables + v_flattop := ram_pulse_doutb(C_BITS_ADDR_TOP - 1 downto 0); + v_addr_length := ram_pulse_doutb(C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_ADDR_TOP); + v_addr_start := ram_pulse_doutb(C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP); + v_addr_end := std_logic_vector(unsigned(v_addr_start) + unsigned(v_addr_length) - 1); + v_amplitude_factor := ram_pulse_doutb(C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP); + v_time_factor := ram_pulse_doutb(C_BITS_TIME_FACTOR + C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP); + v_cnt_time := ram_pulse_doutb(24 + C_BITS_TIME_FACTOR + C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_TIME_FACTOR + C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP); + + ------------------------------------------------------------------------ + -- Main state machine + ------------------------------------------------------------------------ + case sm_state is + + ------------------------------------------------------------------------ + -- Wait for rising edge of enable + -- This is set when the JESD interface is aligned and functional. + -- Send a zero value to initialize the DAC then go to idle. + ------------------------------------------------------------------------ + when S_RESET => + + if (enable = '1') and (enable_d1 = '0') then + sm_wavedata <= (others=>'0'); + sm_wavedata_dv <= '1'; + sm_state <= S_IDLE; + end if; + sm_busy <= '0'; + ram_waveform_enb <= '0'; + + + ------------------------------------------------------------------------ + -- Wait for rising edge of 'start'. + -- No data output. + ------------------------------------------------------------------------ + when S_IDLE => + + if (start = '1') and (start_d1 = '0') then + sm_state <= S_WAIT; + sm_busy <= '1'; + else + sm_busy <= '0'; + end if; + + ram_waveform_enb <= '0'; + + ------------------------------------------------------------------------ + -- Wait for cnt_time, external input, to match pulse position RAM output + -- Return to idle state if max time is reached. Output waveform value zero. + ------------------------------------------------------------------------ + when S_WAIT => + + -- Start to output wave and increment pulse position RAM address + if (v_cnt_time = cnt_time) then + sm_state <= S_WAVE_UP; + -- set the wavetable's address to the starting address defined from the pulse ram + ram_waveform_addrb <= v_addr_start; + elsif (cnt_time = X"FFFFFF") then + sm_state <= S_IDLE; + end if; + + ram_waveform_enb <= '1'; + ------------------------------------------------------------------------ + -- Output the raising edge of a waveform + -- Hold the last address when complete + ------------------------------------------------------------------------ + when S_WAVE_UP => + -- Check if is end of rise of the waveform, and hold the address + if (ram_waveform_addrb = v_addr_end) then + sm_state <= S_WAVE_FLAT; + -- initialize the counter for the flat top of the waveform + cnt_wave_top <= std_logic_vector(to_unsigned(0, C_BITS_ADDR_TOP)); + else + -- Output waveform from RAM , and increment the address + -- TODO: apply scaling factor to the address and then to the output + ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1); + end if; + sm_wavedata <= ram_waveform_doutb; + sm_wavedata_dv <= '1'; + + ------------------------------------------------------------------------ + -- Hold the last address and output its data + -- decrement from this address when finished waiting + ------------------------------------------------------------------------ + when S_WAVE_FLAT => + if (cnt_wave_top = v_flattop) then + sm_state <= S_WAVE_DOWN; + else + cnt_wave_top <= std_logic_vector(unsigned(cnt_wave_top) + 1); + end if; + sm_wavedata <= ram_waveform_doutb; + sm_wavedata_dv <= '1'; + + ------------------------------------------------------------------------ + -- Output the falling edge of a waveform + -- Hold the start address when complete + ------------------------------------------------------------------------ + when S_WAVE_DOWN => + + -- End of waveform? + if (ram_waveform_addrb = v_addr_start) then + + -- If the end of the pulse table is reached then go to idle + if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_NUM_PULSE-1,4))) then + ram_pulse_addrb <= (others=>'0'); + sm_state <= S_IDLE; + + else -- increment pulse address for the next waveform + ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1); + sm_state <= S_WAIT; + end if; + + -- Output waveform from RAM with decremented address + else + ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - 1); + end if; + sm_wavedata <= ram_waveform_doutb; + sm_wavedata_dv <= '1'; + + ------------------------------------------------------------------------ + -- Default + ------------------------------------------------------------------------ + when others => + sm_state <= S_IDLE; + + end case; + end if; + + end process; + + -- AXI-Stream output. + -- TBD: This should come from a FIFO + -- TODO: the bits are not correct, should be top bits (C_BITS_GAIN_FACTOR + 16 downto C_BITS_GAIN_FACTOR), but for now just make it this way so modelsim can simulate + -- TODO: apply scaling factor to the output + axis_tdata <= sm_wavedata; -- axi stream output data, this output should be multiplied by the gain factor, then take the top 16 bits + axis_tvalid <= sm_wavedata_dv; -- axi_stream output data valid + + -- TBD : Generate in state machine? + axis_tlast <= '0'; -- axi_stream output last + + + ---------------------------------------------------------------- + -- **** TBD : ADD FIFO **** + ---------------------------------------------------------------- + -- FIFO for waveform data + -- connect to external output to whatever we want to connect + ---------------------------------------------------------------- + --u_data_to_stream : entity work.fifo_data_to_stream + --port map ( + -- clk => clk, -- input std_logic + -- srst => reset, -- input std_logic + -- rd_en => fifo_rd_en, -- input std_logic + -- wr_en => fifo_wr_en, -- input std_logic + -- empty => fifo_empty, -- output std_logic + -- full => fifo_full, -- output std_logic + -- din => ram_waveform_doutb, -- input slv(15 downto 0) + -- dout => fifo_dout, -- output slv(15 downto 0) + -- + -- -- FIFO signals, some of then are for debug purpose + -- wr_ack => fifo_wr_ack, -- output std_logic + -- overflow => fifo_overflow, -- output std_logic + -- valid => fifo_valid, -- output std_logic + -- underflow => fifo_underflow, -- output std_logic + -- wr_rst_busy => fifo_wr_rst_busy, -- output std_logic + -- rd_rst_busy => fifo_rd_rst_busy -- output std_logic + --); + + + ---------------------------------------------------------------- + -- CPU Read/Write RAM + -- MSB of cpu_addr is used to select one of the two RAMs + -- to read/write, and the remainder are a 9-bit or 4-bit RAM address. + ---------------------------------------------------------------- + pr_ram_rw : process (reset, clk) + begin + if (reset = '1') then + + ram_pulse_addra <= (others=>'0'); + ram_pulse_dina <= (others=>'0'); + ram_pulse_we <= '0'; + + ram_waveform_ena <= '0'; + ram_waveform_wea <= (others=>'0'); + ram_waveform_addra <= (others=>'0'); + ram_waveform_dina <= (others=>'0'); + + cpu_rdata <= (others=>'0'); + cpu_rdata_dv <= '0'; + cpu_rdata_dv_e1 <= '0'; + cpu_rdata_dv_e2 <= '0'; + cpu_rdata_ramsel_d1 <= '0'; + cpu_rdata_ramsel_d2 <= '0'; + + elsif rising_edge(clk) then + + ram_waveform_ena <= '0'; + + ------------------------------------------------- + -- CPU writing RAM + ------------------------------------------------- + if (cpu_wr = '1') and (cpu_sel = '1') then + + -- 0 for pulse position, 1 for waveform table + if (cpu_addr(9) = '1') then + + ram_pulse_addra <= (others=>'0'); + ram_pulse_dina <= (others=>'0'); + ram_pulse_we <= '0'; + + ram_waveform_wea(0) <= '1'; + ram_waveform_ena <= '1'; + ram_waveform_addra <= cpu_addr(8 downto 0); + ram_waveform_dina <= cpu_wdata; + + else + + ram_pulse_addra <= cpu_addr(5 downto 2); + -- select which part of the 96-bit data to write + if (cpu_addr(1 downto 0) = "00") then + ram_pulse_dina(31 downto 0) <= cpu_wdata; + elsif (cpu_addr(1 downto 0) = "01") then + ram_pulse_dina(63 downto 32) <= cpu_wdata; + elsif (cpu_addr(1 downto 0) = "10") then + ram_pulse_dina(95 downto 64) <= cpu_wdata; + ram_pulse_we <= '1'; -- Write on the thrid cycle + end if; + + + ram_waveform_ena <= '0'; + ram_waveform_wea <= (others=>'0'); + ram_waveform_addra <= (others=>'0'); + ram_waveform_dina <= (others=>'0'); + + end if; + + cpu_rdata_dv_e1 <= '0'; + cpu_rdata_dv_e2 <= '0'; + cpu_rdata_ramsel_d1 <= '0'; + cpu_rdata_ramsel_d2 <= '0'; + + + ------------------------------------------------- + -- CPU read + ------------------------------------------------- + elsif (cpu_wr = '0') and (cpu_sel = '1') then + + if (cpu_addr(9) = '1') then -- Waveform + ram_waveform_ena <= '1'; + ram_pulse_addra <= (others=>'0'); + ram_waveform_addra <= cpu_addr(8 downto 0); + else -- Pulse + ram_pulse_addra <= cpu_addr(5 downto 2); + ram_pulse_douta_d1 <= ram_pulse_douta; -- Delay distrib RAM output to match pipeline of Block RAM + ram_waveform_addra <= (others=>'0'); + end if; + + ram_pulse_we <= '0'; + ram_waveform_wea(0) <= '0'; + + cpu_rdata_dv_e2 <= '1'; -- DV for cycle, when RAM output occurs + cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle + cpu_rdata_ramsel_d1 <= cpu_addr(9); -- Save the select bit one cycle later + cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1; + + else + ram_pulse_addra <= (others=>'0'); + ram_pulse_we <= '0'; + ram_waveform_addra <= (others=>'0'); + ram_waveform_wea(0) <= '0'; + + cpu_rdata_dv_e2 <= '0'; + cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle + cpu_rdata_ramsel_d1 <= '0'; + cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1; + + end if; + + ------------------------------------------------- + -- Output the delayed RAM data + -- This adds a pipeline delay to the cpu_rdata_dv to account for + -- the delay in reading data from the RAM + ------------------------------------------------- + if (cpu_rdata_dv_e1 = '1') then + + cpu_rdata_dv <= '1'; + + -- Select source of output data + if (cpu_rdata_ramsel_d2 = '1') then -- Output is from waveform table + cpu_rdata <= ram_waveform_douta; + + elsif (cpu_rdata_ramsel_d2 = '0') then + -- cpu_rdata <= X"00" & ram_pulse_douta_d1; + -- select which part of the 96-bit data to read + if (cpu_addr(1 downto 0) = "00") then + cpu_rdata <= ram_pulse_douta_d1(31 downto 0); + elsif (cpu_addr(1 downto 0) = "01") then + cpu_rdata <= ram_pulse_douta_d1(63 downto 32); + elsif (cpu_addr(1 downto 0) = "10") then + cpu_rdata <= ram_pulse_douta_d1(95 downto 64); + + end if; + end if; + + else + cpu_rdata <= (others=>'0'); + cpu_rdata_dv <= '0'; + end if; + + end if; + + end process; + + +-- ---------------------------------------------------------------- +-- -- Read time from RAM to generate pulses +-- -- When input cnt_time equals RAM time output then set dout +-- -- to RAM amplitude output and read next set of RAM data. +-- -- Keep reading waveform RAM every clock cycle until the end of the RAM +-- ---------------------------------------------------------------- +-- pr_ram_pulse : process(reset, clk) +-- begin +-- if (reset = '1') then +-- +-- ram_pulse_addrb <= (others => '0'); +-- start_pulse <= '0'; +-- dout_dv <= '0'; +-- +-- elsif rising_edge(clk) then +-- +-- -- dout <= ram_amplitude; +-- +-- if (cnt_time = X"000000") then -- Not triggered +-- ram_pulse_addrb <= (others=>'0'); +-- dout_dv <= '0'; +-- start_pulse <= '0'; +-- +-- elsif (ram_time = cnt_time) then +-- +-- ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1); +-- dout_dv <= '1'; +-- start_pulse <= '1'; +-- +-- else +-- dout_dv <= '0'; +-- start_pulse <= '0'; +-- end if; +-- +-- end if; +-- +-- end process; +-- +-- +-- ---------------------------------------------------------------- +-- -- Read amplitude from Waveform RAM to generate pulses +-- -- When start_pulse is asserted, and when FIFO is not full, write +-- -- amplitude to FIFO. +-- ---------------------------------------------------------------- +-- pr_ram_wavetable : process(reset, clk) +-- begin +-- if (reset = '1') then +-- fifo_wr_en <= '0'; +-- ram_waveform_addrb <= (others => '0'); +-- ram_waveform_enb <= '0'; +-- busy <= '0'; +-- elsif rising_edge(clk) then +-- if (read_table = '1') then -- start_pulse get asserted +-- busy <= '1'; +-- -- TODO EricToGeoff : This condition may not satisfy all cases of a fifo_ready, maybe also utilize fifo_wr_ack or just a simple FSM? +-- if (fifo_full = '0') then +-- fifo_wr_en <= '1'; +-- ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1); +-- ram_waveform_enb <= '1'; +-- else +-- fifo_wr_en <= '0'; +-- -- FIFO is full, wait +-- ram_waveform_addrb <= ram_waveform_addrb; +-- ram_waveform_enb <= '0'; +-- end if; +-- else +-- fifo_wr_en <= '0'; +-- ram_waveform_addrb <= (others => '0'); +-- ram_waveform_enb <= '0'; +-- end if; +-- end if; +-- +-- end process; +-- +-- -- For new versions, ram_doutb are differnt RAMs b port outputs, ram_amplitude should go thought a FIFO first from RAM +-- ram_time <= ram_doutb; +-- read_table <= start_pulse; +-- +-- fifo_rd_en <= axi_tready and fifo_full; + +end rtl; diff --git a/src/sandbox/tb_cpubus_dacs_pulse_channel.vhdl b/src/sandbox/tb_cpubus_dacs_pulse_channel.vhdl new file mode 100644 index 0000000..541d87f --- /dev/null +++ b/src/sandbox/tb_cpubus_dacs_pulse_channel.vhdl @@ -0,0 +1,395 @@ +----------------------------------------------------------- +-- File : tb_cpubus_dacs_pulse_channel.vhd +----------------------------------------------------------- +-- +-- Testbench for CPU bus peripheral. +-- +-- Description : Pulse output control of Qlaser FPGA +-- Block drives AXI-stream to JESD DACs +-- +---------------------------------------------------------- +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; +use std.textio.all; + +use work.std_iopak.all; + + +entity tb_cpubus_dacs_pulse_channel is +end tb_cpubus_dacs_pulse_channel; + +architecture behave of tb_cpubus_dacs_pulse_channel is + +signal clk : std_logic; +signal reset : std_logic; +signal enable : std_logic; +signal start : std_logic; +signal cnt_time : std_logic_vector(23 downto 0); +signal busy : std_logic; +signal cpu_wr : std_logic; +signal cpu_sel : std_logic; +signal cpu_addr : std_logic_vector(15 downto 0); +signal cpu_wdata : std_logic_vector(31 downto 0); +signal cpu_rdata : std_logic_vector(31 downto 0); +signal cpu_rdata_dv : std_logic; + +-- AXI-stream output interface +signal axis_tready : std_logic := '1'; -- Always ready +signal axis_tdata : std_logic_vector(15 downto 0); +signal axis_tvalid : std_logic; +signal axis_tlast : std_logic; + +-- Halts simulation by stopping clock when set true +signal sim_done : boolean := false; + +-- Crystal clock freq expressed in MHz +constant CLK_FREQ_MHZ : real := 100.0; +-- Clock period +constant CLK_PER : time := integer(1.0E+6/(CLK_FREQ_MHZ)) * 1 ps; + +-- Block registers +constant ADR_RAM_PULSE : integer := 0; -- base address for pulse RAM, TODO: this constant should eventually go to qlaser_pkg +constant ADR_RAM_WAVE : integer := 512; -- + + + + +------------------------------------------------------------- +-- CPU write procedure. Address in decimal. Data in hex +------------------------------------------------------------- +procedure cpu_write( + signal clk : in std_logic; + constant a : in integer; + constant d : in std_logic_vector(31 downto 0); + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +begin + wait until clk'event and clk='0'; + cpu_sel <= '1'; + cpu_wr <= '1'; + cpu_addr <= std_logic_vector(to_unsigned(a, 16)); + cpu_wdata <= std_logic_vector(d); + wait until clk'event and clk='0'; + cpu_sel <= '0'; + cpu_wr <= '0'; + cpu_addr <= (others=>'0'); + cpu_wdata <= (others=>'0'); + wait until clk'event and clk='0'; +end; + +------------------------------------------------------------- +-- CPU write pulse definition RAM +-- Use 96 bit data to make three 32-bit writes +------------------------------------------------------------- +procedure cpu_write_pulsedef( + signal clk : in std_logic; + + constant num_entry : in integer; + + -- TODO: Partial ? list of parameters + constant pulsetime : in integer; -- Pulse time in clock cycles + constant timefactor : in real; -- Fixed point time scale factor + constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000" + constant wavestartaddr : in integer; -- Start address in waveform RAM + constant wavesteps : in integer; -- Number of steps in waveform rise and fall + constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall + + + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +-- Vectors for converted values +variable slv_pulsetime : std_logic_vector(26 downto 0); -- For 27-bit pulse time +variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep +variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain +variable slv_wavestartaddr : std_logic_vector(11 downto 0); -- For 12-bit address i.e. 1024 point waveform RAM +variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points +variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform + +variable slv_entry_data : std_logic_vector(95 downto 0); -- Vector for entire memory entry + +-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg +-- Define the number of fractional bits +constant BIT_FRAC : integer := 4; -- TODO: this should be defined in qlaser_pkg +begin + + -- Convert each field into its std_logic_vector equivalent + slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 27)); + slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 12)); + slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10)); + slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17)); + + + --etc, etc. + + -- Build full entry out of component fields. Final length should be 96 bits. + -- slv_entry_data := "000" & slv_pulsetime & slv_timefactor & slv_gainfactor & slv_wavestartaddr & slv_wavesteps & slv_wavetopwidth; -- This might not correct + + -- -- Write 96-bit entry in 3 writes. (Address is an integer) + -- cpu_write(clk, ADR_RAM_PULSE+(4*num_entry) , slv_entry_data(31 downto 0), cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + -- cpu_write(clk, ADR_RAM_PULSE+(4*num_entry)+1 , slv_entry_data(63 downto 32), cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + -- cpu_write(clk, ADR_RAM_PULSE+(4*num_entry)+2 , slv_entry_data(95 downto 64), cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + -- Write 32-bit entry in +end; + +------------------------------------------------------------- +-- CPU write procedure. Address and Data in decimal +------------------------------------------------------------- +procedure cpu_write( + signal clk : in std_logic; + constant a : in integer; + constant d : in integer; + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +begin + cpu_write(clk, a , std_logic_vector(to_unsigned(d,32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata); +end; + + +------------------------------------------------------------- +-- CPU read procedure +------------------------------------------------------------- +procedure cpu_read( + signal clk : in std_logic; + constant a : in integer; + constant exp_d : in std_logic_vector(31 downto 0); + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0); + signal cpu_rdata : in std_logic_vector(31 downto 0); + signal cpu_rdata_dv : in std_logic +) is +variable v_bdone : boolean := false; +variable str_out : string(1 to 256); +begin + wait until clk'event and clk='0'; + cpu_sel <= '1'; + cpu_wr <= '0'; + cpu_addr <= std_logic_vector(to_unsigned(a, 16)); + cpu_wdata <= (others=>'0'); + while (v_bdone = false) loop + wait until clk'event and clk='0'; + cpu_sel <= '1'; + if (cpu_rdata_dv = '1') then + if (cpu_rdata /= exp_d) then + fprint(str_out, "Read exp: 0x%s actual: 0x%s\n", to_string(to_bitvector(exp_d),"%08X"), to_string(to_bitvector(cpu_rdata),"%08X")); + report str_out severity error; + end if; + v_bdone := true; + cpu_sel <= '0'; + cpu_addr <= (others=>'0'); + end if; + end loop; + wait until clk'event and clk='0'; + wait until clk'event and clk='0'; +end; + +------------------------------------------------------------- +-- CPU read pulse definition RAM +-- Use 96 bit data to make three 32-bit writes +------------------------------------------------------------- +procedure cpu_read_pulsedef( + signal clk : in std_logic; + + constant num_entry : in integer; + + -- TODO: Partial ? list of parameters + constant pulsetime : in integer; -- Pulse time in clock cycles + constant timefactor : in real; -- Fixed point time scale factor + constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000" + constant wavestartaddr : in integer; -- Start address in waveform RAM + constant wavesteps : in integer; -- Number of steps in waveform rise and fall + constant wavetopwidth : in integer; -- Number of clock cycles in waveform top between end of rise and start of fall + + + signal cpu_sel : out std_logic; + signal cpu_wr : out std_logic; + signal cpu_addr : out std_logic_vector(15 downto 0); + signal cpu_wdata : out std_logic_vector(31 downto 0) +) is +-- Vectors for converted values +variable slv_pulsetime : std_logic_vector(23 downto 0); -- For 24-bit pulse time +variable slv_timefactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point timestep +variable slv_gainfactor : std_logic_vector(15 downto 0); -- For 16-bit fixed point gain +variable slv_wavestartaddr : std_logic_vector( 9 downto 0); -- For 10-bit address i.e. 1024 point waveform RAM +variable slv_wavesteps : std_logic_vector( 9 downto 0); -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points +variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit number of clock cycles in top of waveform + +variable slv_entry_data : std_logic_vector(95 downto 0); -- Vector for entire memory entry + +-- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg +-- Define the number of fractional bits +constant BIT_FRAC : integer := 4; -- TODO: this should be defined in qlaser_pkg +begin + + -- Convert each field into its std_logic_vector equivalent + slv_pulsetime := std_logic_vector(to_unsigned(pulsetime, 24)); + slv_timefactor := std_logic_vector(to_unsigned(integer(timefactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_gainfactor := std_logic_vector(to_unsigned(integer(gainfactor * real(2**BIT_FRAC)), 16)); -- Convert real to std_logic_vector keeping the fractional part + slv_wavestartaddr := std_logic_vector(to_unsigned(wavestartaddr, 10)); + slv_wavesteps := std_logic_vector(to_unsigned(wavesteps, 10)); + slv_wavetopwidth := std_logic_vector(to_unsigned(wavetopwidth, 17)); + + + --etc, etc. + + -- Build full entry out of component fields. Final length should be 96 bits. + slv_entry_data := "000" & slv_pulsetime & slv_timefactor & slv_gainfactor & slv_wavestartaddr & slv_wavesteps & slv_wavetopwidth; -- This might not correct + + -- Write 96-bit entry in 3 writes. (Address is an integer) + cpu_read(clk, ADR_RAM_PULSE+(4*num_entry), slv_entry_data(31 downto 0), cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + cpu_read(clk, ADR_RAM_PULSE+(4*num_entry) + 1, slv_entry_data(63 downto 32), cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + cpu_read(clk, ADR_RAM_PULSE+(4*num_entry) + 2, slv_entry_data(95 downto 64), cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + +end; + + +------------------------------------------------------------- +-- Delay +------------------------------------------------------------- +procedure clk_delay( + constant nclks : in integer +) is +begin + for I in 0 to nclks loop + wait until clk'event and clk ='0'; + end loop; +end; + + +---------------------------------------------------------------- +-- Print a string with no time or instance path. +---------------------------------------------------------------- +procedure cpu_print_msg( + constant msg : in string +) is +variable line_out : line; +begin + write(line_out, msg); + writeline(output, line_out); +end procedure cpu_print_msg; + + +begin + + ------------------------------------------------------------- + -- Unit Under Test + ------------------------------------------------------------- + u_dac_pulse : entity work.qlaser_dacs_pulse_channel + port map ( + clk => clk , -- in std_logic; + reset => reset , -- in std_logic; + + enable => enable , -- out std_logic; + start => start , -- out std_logic; + cnt_time => cnt_time , -- out std_logic_vector(23 downto 0); -- Set to '1' while SPI interface is busy + + busy => busy , -- out std_logic; -- Set to '1' while SPI interface is busy + + -- CPU interface + cpu_wr => cpu_wr , -- in std_logic; + cpu_sel => cpu_sel , -- in std_logic; + cpu_addr => cpu_addr(11 downto 0) , -- in std_logic_vector(11 downto 0); + cpu_wdata => cpu_wdata , -- in std_logic_vector(31 downto 0); + + cpu_rdata => cpu_rdata , -- out std_logic_vector(31 downto 0); + cpu_rdata_dv => cpu_rdata_dv , -- out std_logic; + + + -- AXI-Stream interface + axis_tready => axis_tready , -- in std_logic; -- Clock (50 MHz max) + axis_tdata => axis_tdata , -- out std_logic_vector(15 downto 0); + axis_tvalid => axis_tvalid , -- out std_logic; -- Master out, Slave in. (Data to DAC) + axis_tlast => axis_tlast -- out std_logic; -- Active low chip select (sync_n) + ); + + + ------------------------------------------------------------- + -- Generate system clock. Halt when sim_done is true. + ------------------------------------------------------------- + pr_clk : process + begin + clk <= '0'; + wait for (CLK_PER/2); + clk <= '1'; + wait for (CLK_PER-CLK_PER/2); + if (sim_done=true) then + wait; + end if; + end process; + + + ------------------------------------------------------------- + -- Reset and drive CPU bus + ------------------------------------------------------------- + pr_main : process + variable v_ndata32 : integer := 0; + variable v_ndata16 : integer := 0; + begin + -- Reset + reset <= '1'; + enable <= '0'; + start <= '0'; + cnt_time <= (others=>'0'); + + cpu_sel <= '0'; + cpu_wr <= '0'; + cpu_wdata <= (others=>'0'); + cpu_addr <= (others=>'0'); + + cpu_print_msg("Simulation start"); + clk_delay(5); + reset <= '0'; + + clk_delay(5); + enable <= '1'; + + + clk_delay(20); + + + ---------------------------------------------------------------- + -- Load pulse RAM with a series of pulse start times + ---------------------------------------------------------------- + v_ndata32 := 128; -- Time for first pulse + cpu_print_msg("Load pulse RAM"); + for NADDR in 0 to 15 loop + -- cpu_write(clk, ADR_RAM_PULSE + NADDR , v_ndata32 + (NADDR*(1024+32)), cpu_sel, cpu_wr, cpu_addr, cpu_wdata); -- TODO: rn don't know how to make it write three difference places, for now I', just gonna manually write it + cpu_write_pulsedef(clk, NADDR, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 512, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + end loop; + cpu_print_msg("Pulse RAM loaded"); + clk_delay(20); + + ---------------------------------------------------------------- + -- Read back Pulse RAM. + ---------------------------------------------------------------- + v_ndata32 := 128; -- Time for first pulse + for NADDR in 0 to 15 loop + cpu_read_pulsedef(clk, NADDR, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 512, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + end loop; + clk_delay(20); + + wait for 10 us; + + cpu_print_msg("Simulation done"); + clk_delay(5); + + sim_done <= true; + wait; + + end process; + +end behave; + diff --git a/tools/build_src/build.tcl b/tools/build_src/build.tcl new file mode 100644 index 0000000..909a90b --- /dev/null +++ b/tools/build_src/build.tcl @@ -0,0 +1,45 @@ +# "cd" to the directory where this script is located +cd [file dirname [info script]] + +create_project zcu_pulse_channel ../../prj -force + +set_property board_part xilinx.com:zcu102:part0:3.4 [current_project] + +add_files {..\..\src\hdl\modules\qlaser_dacs_pulse_channel.vhdl} +add_files -fileset sim_1 {..\..\src\hdl\tb\tb_cpubus_dacs_pulse_channel.vhdl} +add_files {..\..\src\hdl\pkg\qlaser_dacs_pulse_channel_pkg.vhd} +add_files {..\..\src\hdl\pkg\qlaser_dac_dc_pkg.vhd} +add_files {..\..\src\hdl\pkg\qlaser_pkg.vhd} +add_files {..\..\src\hdl\pkg\iopakp.vhd} +add_files {..\..\src\hdl\pkg\iopakb.vhd} +read_ip {..\xilinx-zcu\bram_pulseposition\bram_pulseposition.xci} +read_ip {..\xilinx-zcu\bram_waveform\bram_waveform.xci} +read_ip {..\xilinx-zcu\fifo_data_to_stream\fifo_data_to_stream.xci} +read_ip {..\xilinx-zcu\bram_pulse_definition\bram_pulse_definition.xci} + +# upgrade_ip [get_ips -filter {SCOPE !~ "*.bd"}] +generate_target all [get_ips -filter {SCOPE !~ "*.bd"}] + +# Run the synthesis and generate the IP output products +launch_runs synth_1 + +# Wait for the synthesis to complete +wait_on_run synth_1 + +# Generate the simulation models +proc recursive_glob {dir} { + set files [glob -nocomplain -type f -directory $dir *_sim_netlist.vhdl] + foreach subdir [glob -nocomplain -type d -directory $dir *] { + lappend files {*}[recursive_glob $subdir] + } + return $files +} + +set src_dir ../../prj/zcu_pulse_channel.gen/sources_1/ip/ +set files [recursive_glob $src_dir] + +foreach file $files { + file copy -force $file ../../src/hdl/ip_gen +} + +exit diff --git a/tools/sim/README.md b/tools/sim/README.md index 8b13789..07c6b38 100644 --- a/tools/sim/README.md +++ b/tools/sim/README.md @@ -1 +1,2 @@ +Please put your modelsim.ini file in this directory and compile modelsim in this directory. diff --git a/tools/sim/compile.bat b/tools/sim/compile.bat new file mode 100644 index 0000000..90718fc --- /dev/null +++ b/tools/sim/compile.bat @@ -0,0 +1,2 @@ +echo off +vsim -c -quiet -do compile.do \ No newline at end of file diff --git a/tools/sim/compile.do b/tools/sim/compile.do new file mode 100644 index 0000000..90e2eb3 --- /dev/null +++ b/tools/sim/compile.do @@ -0,0 +1,8 @@ +vlib work + +vcom ../../src/hdl/ip_gen/*.vhd* +vcom ../../src/hdl/pkg/*pkg.vhd +vcom ../../src/hdl/pkg/iopakp.vhd +vcom ../../src/hdl/pkg/iopakb.vhd +vcom ../../src/hdl/modules/*.vhd* +vcom ../../src/hdl/tb/*.vhd* \ No newline at end of file diff --git a/tools/sim/graphit.py b/tools/sim/graphit.py new file mode 100644 index 0000000..52b3c46 --- /dev/null +++ b/tools/sim/graphit.py @@ -0,0 +1,22 @@ +# take wave_values.txt and plot it +import matplotlib +import matplotlib.pyplot as plt +import numpy as np +import sys + +matplotlib.use('wxAgg') + +f = open('wave_values.txt', 'r') +lines = f.readlines() +f.close() + +# convert to float +vals = np.array([float(x) for x in lines]) +times = np.arange(0, len(vals), 1)/4096.0 + +# plot. range is 0 to 1 +plt.plot(times, vals) +plt.show() + + + diff --git a/tools/sim/modelsim.ini b/tools/sim/modelsim.ini new file mode 100644 index 0000000..bd51c12 --- /dev/null +++ b/tools/sim/modelsim.ini @@ -0,0 +1,764 @@ +; Copyright 1991-2009 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini + +; Altera Primitive libraries +; +; VHDL Section +; +; +; Verilog Section +; + +secureip = E:/xilinx_libs/secureip +unisim = E:/xilinx_libs/unisim +unimacro = E:/xilinx_libs/unimacro +unifast = E:/xilinx_libs/unifast +unisims_ver = E:/xilinx_libs/unisims_ver +unimacro_ver = E:/xilinx_libs/unimacro_ver +unifast_ver = E:/xilinx_libs/unifast_ver +simprims_ver = E:/xilinx_libs/simprims_ver +xpm = E:/xilinx_libs/xpm +xilinx_vip = E:/xilinx_libs/xilinx_vip +adc_dac_if_phy_v1_0_0 = E:/xilinx_libs/adc_dac_if_phy_v1_0_0 +advanced_io_wizard_phy_v1_0_0 = E:/xilinx_libs/advanced_io_wizard_phy_v1_0_0 +advanced_io_wizard_v1_0_7 = E:/xilinx_libs/advanced_io_wizard_v1_0_7 +ahblite_axi_bridge_v3_0_21 = E:/xilinx_libs/ahblite_axi_bridge_v3_0_21 +ai_noc = E:/xilinx_libs/ai_noc +ai_pl_trig = E:/xilinx_libs/ai_pl_trig +ai_pl = E:/xilinx_libs/ai_pl +an_lt_v1_0_6 = E:/xilinx_libs/an_lt_v1_0_6 +audio_clock_recovery_unit_v1_0_2 = E:/xilinx_libs/audio_clock_recovery_unit_v1_0_2 +audio_tpg_v1_0_0 = E:/xilinx_libs/audio_tpg_v1_0_0 +av_pat_gen_v1_0_1 = E:/xilinx_libs/av_pat_gen_v1_0_1 +av_pat_gen_v2_0_0 = E:/xilinx_libs/av_pat_gen_v2_0_0 +axis_cap_ctrl_v1_0_0 = E:/xilinx_libs/axis_cap_ctrl_v1_0_0 +axis_dbg_stub_v1_0_0 = E:/xilinx_libs/axis_dbg_stub_v1_0_0 +axis_dbg_sync_v1_0_0 = E:/xilinx_libs/axis_dbg_sync_v1_0_0 +axis_ila_adv_trig_v1_0_0 = E:/xilinx_libs/axis_ila_adv_trig_v1_0_0 +axis_ila_ct_v1_0_0 = E:/xilinx_libs/axis_ila_ct_v1_0_0 +axis_ila_pp_v1_0_0 = E:/xilinx_libs/axis_ila_pp_v1_0_0 +axis_ila_txns_cntr_v1_0_0 = E:/xilinx_libs/axis_ila_txns_cntr_v1_0_0 +axis_infrastructure_v1_1_0 = E:/xilinx_libs/axis_infrastructure_v1_1_0 +axis_itct_v1_0_0 = E:/xilinx_libs/axis_itct_v1_0_0 +axis_mem_v1_0_0 = E:/xilinx_libs/axis_mem_v1_0_0 +axis_mu_v1_0_0 = E:/xilinx_libs/axis_mu_v1_0_0 +axis_protocol_checker_v2_0_10 = E:/xilinx_libs/axis_protocol_checker_v2_0_10 +axi_ahblite_bridge_v3_0_23 = E:/xilinx_libs/axi_ahblite_bridge_v3_0_23 +axi_amm_bridge_v1_0_16 = E:/xilinx_libs/axi_amm_bridge_v1_0_16 +axi_bram_ctrl_v4_1_6 = E:/xilinx_libs/axi_bram_ctrl_v4_1_6 +axi_chip2chip_v5_0_15 = E:/xilinx_libs/axi_chip2chip_v5_0_15 +axi_dbg_hub = E:/xilinx_libs/axi_dbg_hub +axi_infrastructure_v1_1_0 = E:/xilinx_libs/axi_infrastructure_v1_1_0 +axi_jtag_v1_0_0 = E:/xilinx_libs/axi_jtag_v1_0_0 +axi_lite_ipif_v3_0_4 = E:/xilinx_libs/axi_lite_ipif_v3_0_4 +axi_lmb_bridge_v1_0_0 = E:/xilinx_libs/axi_lmb_bridge_v1_0_0 +axi_pcie3_v3_0_22 = E:/xilinx_libs/axi_pcie3_v3_0_22 +axi_perf_mon_v5_0_28 = E:/xilinx_libs/axi_perf_mon_v5_0_28 +axi_pmon_v1_0_0 = E:/xilinx_libs/axi_pmon_v1_0_0 +axi_remapper_rx_v1_0_0 = E:/xilinx_libs/axi_remapper_rx_v1_0_0 +axi_remapper_tx_v1_0_0 = E:/xilinx_libs/axi_remapper_tx_v1_0_0 +blk_mem_gen_v8_3_6 = E:/xilinx_libs/blk_mem_gen_v8_3_6 +blk_mem_gen_v8_4_5 = E:/xilinx_libs/blk_mem_gen_v8_4_5 +bsip_v1_1_0 = E:/xilinx_libs/bsip_v1_1_0 +bs_mux_v1_0_0 = E:/xilinx_libs/bs_mux_v1_0_0 +cam_v2_3_0 = E:/xilinx_libs/cam_v2_3_0 +clk_gen_sim_v1_0_2 = E:/xilinx_libs/clk_gen_sim_v1_0_2 +clk_vip_v1_0_2 = E:/xilinx_libs/clk_vip_v1_0_2 +cmac_usplus_v3_1_9 = E:/xilinx_libs/cmac_usplus_v3_1_9 +cmac_v2_6_7 = E:/xilinx_libs/cmac_v2_6_7 +compact_gt_v1_0_12 = E:/xilinx_libs/compact_gt_v1_0_12 +cpm4_v1_0_8 = E:/xilinx_libs/cpm4_v1_0_8 +cpm5_v1_0_8 = E:/xilinx_libs/cpm5_v1_0_8 +dcmac_v2_0_0 = E:/xilinx_libs/dcmac_v2_0_0 +ddr4_pl_phy_v1_0_0 = E:/xilinx_libs/ddr4_pl_phy_v1_0_0 +ddr4_pl_v1_0_8 = E:/xilinx_libs/ddr4_pl_v1_0_8 +displayport_v8_1_5 = E:/xilinx_libs/displayport_v8_1_5 +dist_mem_gen_v8_0_13 = E:/xilinx_libs/dist_mem_gen_v8_0_13 +dprx_fec_8b10b_v1_0_1 = E:/xilinx_libs/dprx_fec_8b10b_v1_0_1 +dp_videoaxi4s_bridge_v1_0_1 = E:/xilinx_libs/dp_videoaxi4s_bridge_v1_0_1 +ecc_v2_0_13 = E:/xilinx_libs/ecc_v2_0_13 +emb_fifo_gen_v1_0_2 = E:/xilinx_libs/emb_fifo_gen_v1_0_2 +emb_mem_gen_v1_0_6 = E:/xilinx_libs/emb_mem_gen_v1_0_6 +emc_common_v3_0_5 = E:/xilinx_libs/emc_common_v3_0_5 +ethernet_1_10_25g_v2_7_5 = E:/xilinx_libs/ethernet_1_10_25g_v2_7_5 +fast_adapter_v1_0_3 = E:/xilinx_libs/fast_adapter_v1_0_3 +fifo_generator_v13_0_6 = E:/xilinx_libs/fifo_generator_v13_0_6 +fifo_generator_v13_1_4 = E:/xilinx_libs/fifo_generator_v13_1_4 +fifo_generator_v13_2_7 = E:/xilinx_libs/fifo_generator_v13_2_7 +fit_timer_v2_0_10 = E:/xilinx_libs/fit_timer_v2_0_10 +generic_baseblocks_v2_1_0 = E:/xilinx_libs/generic_baseblocks_v2_1_0 +gigantic_mux = E:/xilinx_libs/gigantic_mux +gig_ethernet_pcs_pma_v16_2_8 = E:/xilinx_libs/gig_ethernet_pcs_pma_v16_2_8 +gmii_to_rgmii_v4_1_4 = E:/xilinx_libs/gmii_to_rgmii_v4_1_4 +gtwizard_ultrascale_v1_5_4 = E:/xilinx_libs/gtwizard_ultrascale_v1_5_4 +gtwizard_ultrascale_v1_6_13 = E:/xilinx_libs/gtwizard_ultrascale_v1_6_13 +gtwizard_ultrascale_v1_7_13 = E:/xilinx_libs/gtwizard_ultrascale_v1_7_13 +hbm2e_pl_v1_0_0 = E:/xilinx_libs/hbm2e_pl_v1_0_0 +hbm_v1_0_12 = E:/xilinx_libs/hbm_v1_0_12 +hdcp22_cipher_dp_v1_0_0 = E:/xilinx_libs/hdcp22_cipher_dp_v1_0_0 +hdcp22_cipher_v1_0_3 = E:/xilinx_libs/hdcp22_cipher_v1_0_3 +hdcp22_rng_v1_0_1 = E:/xilinx_libs/hdcp22_rng_v1_0_1 +hdcp_keymngmt_blk_v1_0_0 = E:/xilinx_libs/hdcp_keymngmt_blk_v1_0_0 +hdcp_v1_0_3 = E:/xilinx_libs/hdcp_v1_0_3 +hdmi_acr_ctrl_v1_0_0 = E:/xilinx_libs/hdmi_acr_ctrl_v1_0_0 +hdmi_gt_controller_v1_0_7 = E:/xilinx_libs/hdmi_gt_controller_v1_0_7 +high_speed_selectio_wiz_v3_6_3 = E:/xilinx_libs/high_speed_selectio_wiz_v3_6_3 +i2s_receiver_v1_0_5 = E:/xilinx_libs/i2s_receiver_v1_0_5 +i2s_transmitter_v1_0_5 = E:/xilinx_libs/i2s_transmitter_v1_0_5 +ibert_lib_v1_0_7 = E:/xilinx_libs/ibert_lib_v1_0_7 +ieee802d3_clause74_fec_v1_0_13 = E:/xilinx_libs/ieee802d3_clause74_fec_v1_0_13 +ilknf_v1_1_0 = E:/xilinx_libs/ilknf_v1_1_0 +interlaken_v2_4_11 = E:/xilinx_libs/interlaken_v2_4_11 +in_system_ibert_v1_0_16 = E:/xilinx_libs/in_system_ibert_v1_0_16 +iomodule_v3_1_8 = E:/xilinx_libs/iomodule_v3_1_8 +jesd204c_v4_2_8 = E:/xilinx_libs/jesd204c_v4_2_8 +jesd204_v7_2_15 = E:/xilinx_libs/jesd204_v7_2_15 +jtag_axi = E:/xilinx_libs/jtag_axi +lib_cdc_v1_0_2 = E:/xilinx_libs/lib_cdc_v1_0_2 +lib_pkg_v1_0_2 = E:/xilinx_libs/lib_pkg_v1_0_2 +ll_compress_v1_0_0 = E:/xilinx_libs/ll_compress_v1_0_0 +ll_compress_v1_1_0 = E:/xilinx_libs/ll_compress_v1_1_0 +ll_compress_v2_0_1 = E:/xilinx_libs/ll_compress_v2_0_1 +ll_compress_v2_1_0 = E:/xilinx_libs/ll_compress_v2_1_0 +lmb_bram_if_cntlr_v4_0_21 = E:/xilinx_libs/lmb_bram_if_cntlr_v4_0_21 +lmb_v10_v3_0_12 = E:/xilinx_libs/lmb_v10_v3_0_12 +ltlib_v1_0_0 = E:/xilinx_libs/ltlib_v1_0_0 +lut_buffer_v2_0_0 = E:/xilinx_libs/lut_buffer_v2_0_0 +l_ethernet_v3_3_0 = E:/xilinx_libs/l_ethernet_v3_3_0 +mammoth_transcode_v1_0_0 = E:/xilinx_libs/mammoth_transcode_v1_0_0 +mem_pl_v1_0_0 = E:/xilinx_libs/mem_pl_v1_0_0 +microblaze_v11_0_9 = E:/xilinx_libs/microblaze_v11_0_9 +microblaze_v9_5_4 = E:/xilinx_libs/microblaze_v9_5_4 +mipi_csi2_rx_ctrl_v1_0_8 = E:/xilinx_libs/mipi_csi2_rx_ctrl_v1_0_8 +mipi_csi2_tx_ctrl_v1_0_4 = E:/xilinx_libs/mipi_csi2_tx_ctrl_v1_0_4 +mipi_dphy_v4_3_4 = E:/xilinx_libs/mipi_dphy_v4_3_4 +mipi_dsi_tx_ctrl_v1_0_7 = E:/xilinx_libs/mipi_dsi_tx_ctrl_v1_0_7 +mpegtsmux_v1_1_4 = E:/xilinx_libs/mpegtsmux_v1_1_4 +mrmac_v1_6_0 = E:/xilinx_libs/mrmac_v1_6_0 +multi_channel_25g_rs_fec_v1_0_18 = E:/xilinx_libs/multi_channel_25g_rs_fec_v1_0_18 +mutex_v2_1_11 = E:/xilinx_libs/mutex_v2_1_11 +axi_tg_lib = E:/xilinx_libs/axi_tg_lib +noc_hbm_v1_0_0 = E:/xilinx_libs/noc_hbm_v1_0_0 +noc_ncrb_v1_0_0 = E:/xilinx_libs/noc_ncrb_v1_0_0 +noc_nidb_v1_0_0 = E:/xilinx_libs/noc_nidb_v1_0_0 +noc_nmu_phydir_v1_0_0 = E:/xilinx_libs/noc_nmu_phydir_v1_0_0 +noc_npp_rptr_v1_0_0 = E:/xilinx_libs/noc_npp_rptr_v1_0_0 +noc_nps4_v1_0_0 = E:/xilinx_libs/noc_nps4_v1_0_0 +noc_nps6_v1_0_0 = E:/xilinx_libs/noc_nps6_v1_0_0 +noc_nps_v1_0_0 = E:/xilinx_libs/noc_nps_v1_0_0 +noc_nsu_v1_0_0 = E:/xilinx_libs/noc_nsu_v1_0_0 +nvmeha_v1_0_7 = E:/xilinx_libs/nvmeha_v1_0_7 +nvme_tc_v3_0_1 = E:/xilinx_libs/nvme_tc_v3_0_1 +oddr_v1_0_2 = E:/xilinx_libs/oddr_v1_0_2 +oran_radio_if_v2_2_0 = E:/xilinx_libs/oran_radio_if_v2_2_0 +pci32_v5_0_12 = E:/xilinx_libs/pci32_v5_0_12 +pci64_v5_0_11 = E:/xilinx_libs/pci64_v5_0_11 +pcie_axi4lite_tap_v1_0_1 = E:/xilinx_libs/pcie_axi4lite_tap_v1_0_1 +pcie_dma_versal_v2_0_11 = E:/xilinx_libs/pcie_dma_versal_v2_0_11 +pcie_jtag_v1_0_0 = E:/xilinx_libs/pcie_jtag_v1_0_0 +pcie_qdma_mailbox_v1_0_0 = E:/xilinx_libs/pcie_qdma_mailbox_v1_0_0 +pc_cfr_v6_4_2 = E:/xilinx_libs/pc_cfr_v6_4_2 +pc_cfr_v7_0_1 = E:/xilinx_libs/pc_cfr_v7_0_1 +pc_cfr_v7_1_0 = E:/xilinx_libs/pc_cfr_v7_1_0 +picxo = E:/xilinx_libs/picxo +ptp_1588_timer_syncer_v1_0_2 = E:/xilinx_libs/ptp_1588_timer_syncer_v1_0_2 +ptp_1588_timer_syncer_v2_0_3 = E:/xilinx_libs/ptp_1588_timer_syncer_v2_0_3 +qdma_v4_0_13 = E:/xilinx_libs/qdma_v4_0_13 +qdriv_pl_v1_0_7 = E:/xilinx_libs/qdriv_pl_v1_0_7 +rama_v1_1_12_lib = E:/xilinx_libs/rama_v1_1_12_lib +rld3_pl_phy_v1_0_0 = E:/xilinx_libs/rld3_pl_phy_v1_0_0 +rld3_pl_v1_0_9 = E:/xilinx_libs/rld3_pl_v1_0_9 +roe_framer_v3_0_3 = E:/xilinx_libs/roe_framer_v3_0_3 +rst_vip_v1_0_4 = E:/xilinx_libs/rst_vip_v1_0_4 +smartconnect_v1_0 = E:/xilinx_libs/smartconnect_v1_0 +sem_ultra_v3_1_23 = E:/xilinx_libs/sem_ultra_v3_1_23 +sem_v4_1_13 = E:/xilinx_libs/sem_v4_1_13 +shell_utils_msp432_bsl_crc_gen_v1_0_0 = E:/xilinx_libs/shell_utils_msp432_bsl_crc_gen_v1_0_0 +sim_clk_gen_v1_0_3 = E:/xilinx_libs/sim_clk_gen_v1_0_3 +sim_rst_gen_v1_0_2 = E:/xilinx_libs/sim_rst_gen_v1_0_2 +sim_trig_v1_0_7 = E:/xilinx_libs/sim_trig_v1_0_7 +stm_v1_0 = E:/xilinx_libs/stm_v1_0 +stm_v1_0_0 = E:/xilinx_libs/stm_v1_0_0 +system_cache_v5_0_8 = E:/xilinx_libs/system_cache_v5_0_8 +ta_dma_v1_0_10 = E:/xilinx_libs/ta_dma_v1_0_10 +tcc_decoder_3gpplte_v3_0_6 = E:/xilinx_libs/tcc_decoder_3gpplte_v3_0_6 +ten_gig_eth_mac_v15_1_10 = E:/xilinx_libs/ten_gig_eth_mac_v15_1_10 +ten_gig_eth_pcs_pma_v6_0_22 = E:/xilinx_libs/ten_gig_eth_pcs_pma_v6_0_22 +timer_sync_1588_v1_2_4 = E:/xilinx_libs/timer_sync_1588_v1_2_4 +tmr_inject_v1_0_4 = E:/xilinx_libs/tmr_inject_v1_0_4 +tmr_manager_v1_0_10 = E:/xilinx_libs/tmr_manager_v1_0_10 +tmr_voter_v1_0_4 = E:/xilinx_libs/tmr_voter_v1_0_4 +trace_s2mm_v1_2_0 = E:/xilinx_libs/trace_s2mm_v1_2_0 +tsn_endpoint_ethernet_mac_block_v1_0_11 = E:/xilinx_libs/tsn_endpoint_ethernet_mac_block_v1_0_11 +uhdsdi_gt_v2_0_8 = E:/xilinx_libs/uhdsdi_gt_v2_0_8 +uram_rd_back_v1_0_2 = E:/xilinx_libs/uram_rd_back_v1_0_2 +usxgmii_v1_2_7 = E:/xilinx_libs/usxgmii_v1_2_7 +util_ff_v1_0_0 = E:/xilinx_libs/util_ff_v1_0_0 +util_idelay_ctrl_v1_0_2 = E:/xilinx_libs/util_idelay_ctrl_v1_0_2 +util_reduced_logic_v2_0_4 = E:/xilinx_libs/util_reduced_logic_v2_0_4 +util_vector_logic_v2_0_2 = E:/xilinx_libs/util_vector_logic_v2_0_2 +versal_cips_v3_2_1 = E:/xilinx_libs/versal_cips_v3_2_1 +vfb_v1_0_20 = E:/xilinx_libs/vfb_v1_0_20 +video_frame_crc_v1_0_4 = E:/xilinx_libs/video_frame_crc_v1_0_4 +vid_edid_v1_0_0 = E:/xilinx_libs/vid_edid_v1_0_0 +vid_phy_controller_v2_1_13 = E:/xilinx_libs/vid_phy_controller_v2_1_13 +vid_phy_controller_v2_2_13 = E:/xilinx_libs/vid_phy_controller_v2_2_13 +vitis_deadlock_detector_v1_0_1 = E:/xilinx_libs/vitis_deadlock_detector_v1_0_1 +v_axi4s_remap_v1_0_19 = E:/xilinx_libs/v_axi4s_remap_v1_0_19 +v_axi4s_remap_v1_1_5 = E:/xilinx_libs/v_axi4s_remap_v1_1_5 +v_csc_v1_1_5 = E:/xilinx_libs/v_csc_v1_1_5 +v_deinterlacer_v5_1_0 = E:/xilinx_libs/v_deinterlacer_v5_1_0 +v_demosaic_v1_1_5 = E:/xilinx_libs/v_demosaic_v1_1_5 +v_frmbuf_rd_v2_2_5 = E:/xilinx_libs/v_frmbuf_rd_v2_2_5 +v_frmbuf_wr_v2_2_5 = E:/xilinx_libs/v_frmbuf_wr_v2_2_5 +v_gamma_lut_v1_1_5 = E:/xilinx_libs/v_gamma_lut_v1_1_5 +v_hcresampler_v1_1_5 = E:/xilinx_libs/v_hcresampler_v1_1_5 +v_hdmi_phy1_v1_0_6 = E:/xilinx_libs/v_hdmi_phy1_v1_0_6 +v_hdmi_rx_v3_0_0 = E:/xilinx_libs/v_hdmi_rx_v3_0_0 +v_hdmi_tx_v3_0_0 = E:/xilinx_libs/v_hdmi_tx_v3_0_0 +v_hscaler_v1_1_5 = E:/xilinx_libs/v_hscaler_v1_1_5 +v_letterbox_v1_1_5 = E:/xilinx_libs/v_letterbox_v1_1_5 +v_mix_v5_1_5 = E:/xilinx_libs/v_mix_v5_1_5 +v_scenechange_v1_1_4 = E:/xilinx_libs/v_scenechange_v1_1_4 +v_sdi_rx_vid_bridge_v2_0_0 = E:/xilinx_libs/v_sdi_rx_vid_bridge_v2_0_0 +v_smpte_sdi_v3_0_9 = E:/xilinx_libs/v_smpte_sdi_v3_0_9 +v_smpte_uhdsdi_rx_v1_0_1 = E:/xilinx_libs/v_smpte_uhdsdi_rx_v1_0_1 +v_smpte_uhdsdi_tx_v1_0_1 = E:/xilinx_libs/v_smpte_uhdsdi_tx_v1_0_1 +v_smpte_uhdsdi_v1_0_9 = E:/xilinx_libs/v_smpte_uhdsdi_v1_0_9 +v_tpg_v8_0_9 = E:/xilinx_libs/v_tpg_v8_0_9 +v_tpg_v8_1_5 = E:/xilinx_libs/v_tpg_v8_1_5 +v_tpg_v8_2_1 = E:/xilinx_libs/v_tpg_v8_2_1 +v_uhdsdi_audio_v2_0_6 = E:/xilinx_libs/v_uhdsdi_audio_v2_0_6 +v_uhdsdi_vidgen_v1_0_1 = E:/xilinx_libs/v_uhdsdi_vidgen_v1_0_1 +v_vcresampler_v1_1_5 = E:/xilinx_libs/v_vcresampler_v1_1_5 +v_vid_in_axi4s_v4_0_9 = E:/xilinx_libs/v_vid_in_axi4s_v4_0_9 +v_vid_in_axi4s_v5_0_1 = E:/xilinx_libs/v_vid_in_axi4s_v5_0_1 +v_vscaler_v1_1_5 = E:/xilinx_libs/v_vscaler_v1_1_5 +v_warp_filter_v1_0_2 = E:/xilinx_libs/v_warp_filter_v1_0_2 +v_warp_init_v1_0_2 = E:/xilinx_libs/v_warp_init_v1_0_2 +xbip_dsp48_wrapper_v3_0_4 = E:/xilinx_libs/xbip_dsp48_wrapper_v3_0_4 +xbip_utils_v3_0_10 = E:/xilinx_libs/xbip_utils_v3_0_10 +xdfe_nlf_v1_0_1 = E:/xilinx_libs/xdfe_nlf_v1_0_1 +xdfe_resampler_v1_0_4 = E:/xilinx_libs/xdfe_resampler_v1_0_4 +xdma_v4_1_19 = E:/xilinx_libs/xdma_v4_1_19 +xlconcat_v2_1_4 = E:/xilinx_libs/xlconcat_v2_1_4 +xlconstant_v1_1_7 = E:/xilinx_libs/xlconstant_v1_1_7 +xlslice_v1_0_2 = E:/xilinx_libs/xlslice_v1_0_2 +xpm_cdc_gen_v1_0_1 = E:/xilinx_libs/xpm_cdc_gen_v1_0_1 +xsdbm_v3_0_0 = E:/xilinx_libs/xsdbm_v3_0_0 +xxv_ethernet_v4_1_0 = E:/xilinx_libs/xxv_ethernet_v4_1_0 +aurora_8b10b_versal_v1_0_1 = E:/xilinx_libs/aurora_8b10b_versal_v1_0_1 +axi_c2c_v1_0_3 = E:/xilinx_libs/axi_c2c_v1_0_3 +lib_srl_fifo_v1_0_2 = E:/xilinx_libs/lib_srl_fifo_v1_0_2 +lib_fifo_v1_0_16 = E:/xilinx_libs/lib_fifo_v1_0_16 +axi_datamover_v5_1_28 = E:/xilinx_libs/axi_datamover_v5_1_28 +amm_axi_bridge_v1_0_12 = E:/xilinx_libs/amm_axi_bridge_v1_0_12 +axis_register_slice_v1_1_26 = E:/xilinx_libs/axis_register_slice_v1_1_26 +axis_switch_v1_1_26 = E:/xilinx_libs/axis_switch_v1_1_26 +axis_clock_converter_v1_1_27 = E:/xilinx_libs/axis_clock_converter_v1_1_27 +axis_data_fifo_v2_0_8 = E:/xilinx_libs/axis_data_fifo_v2_0_8 +ats_switch_v1_0_5 = E:/xilinx_libs/ats_switch_v1_0_5 +audio_formatter_v1_0_8 = E:/xilinx_libs/audio_formatter_v1_0_8 +axi4stream_vip_v1_1_12 = E:/xilinx_libs/axi4stream_vip_v1_1_12 +v_tc_v6_2_4 = E:/xilinx_libs/v_tc_v6_2_4 +v_dp_axi4s_vid_out_v1_0_4 = E:/xilinx_libs/v_dp_axi4s_vid_out_v1_0_4 +v_tc_v6_1_13 = E:/xilinx_libs/v_tc_v6_1_13 +v_axi4s_vid_out_v4_0_14 = E:/xilinx_libs/v_axi4s_vid_out_v4_0_14 +axi4svideo_bridge_v1_0_14 = E:/xilinx_libs/axi4svideo_bridge_v1_0_14 +axis_accelerator_adapter_v2_1_16 = E:/xilinx_libs/axis_accelerator_adapter_v2_1_16 +axis_broadcaster_v1_1_25 = E:/xilinx_libs/axis_broadcaster_v1_1_25 +axis_combiner_v1_1_24 = E:/xilinx_libs/axis_combiner_v1_1_24 +axis_data_fifo_v1_1_27 = E:/xilinx_libs/axis_data_fifo_v1_1_27 +axis_dwidth_converter_v1_1_25 = E:/xilinx_libs/axis_dwidth_converter_v1_1_25 +axis_ila_intf_v1_0_0 = E:/xilinx_libs/axis_ila_intf_v1_0_0 +axis_interconnect_v1_1_20 = E:/xilinx_libs/axis_interconnect_v1_1_20 +axis_subset_converter_v1_1_26 = E:/xilinx_libs/axis_subset_converter_v1_1_26 +axis_vio_v1_0_6 = E:/xilinx_libs/axis_vio_v1_0_6 +axi_apb_bridge_v3_0_17 = E:/xilinx_libs/axi_apb_bridge_v3_0_17 +axi_bram_ctrl_v4_0_14 = E:/xilinx_libs/axi_bram_ctrl_v4_0_14 +axi_sg_v4_1_15 = E:/xilinx_libs/axi_sg_v4_1_15 +axi_cdma_v4_1_26 = E:/xilinx_libs/axi_cdma_v4_1_26 +axi_clock_converter_v2_1_25 = E:/xilinx_libs/axi_clock_converter_v2_1_25 +axi_data_fifo_v2_1_25 = E:/xilinx_libs/axi_data_fifo_v2_1_25 +axi_register_slice_v2_1_26 = E:/xilinx_libs/axi_register_slice_v2_1_26 +axi_crossbar_v2_1_27 = E:/xilinx_libs/axi_crossbar_v2_1_27 +axi_dma_v7_1_27 = E:/xilinx_libs/axi_dma_v7_1_27 +axi_protocol_converter_v2_1_26 = E:/xilinx_libs/axi_protocol_converter_v2_1_26 +axi_dwidth_converter_v2_1_26 = E:/xilinx_libs/axi_dwidth_converter_v2_1_26 +axi_emc_v3_0_26 = E:/xilinx_libs/axi_emc_v3_0_26 +axi_epc_v2_0_29 = E:/xilinx_libs/axi_epc_v2_0_29 +lib_bmg_v1_0_14 = E:/xilinx_libs/lib_bmg_v1_0_14 +axi_ethernetlite_v3_0_25 = E:/xilinx_libs/axi_ethernetlite_v3_0_25 +axi_ethernet_buffer_v2_0_24 = E:/xilinx_libs/axi_ethernet_buffer_v2_0_24 +axi_fifo_mm_s_v4_2_8 = E:/xilinx_libs/axi_fifo_mm_s_v4_2_8 +axi_firewall_v1_1_5 = E:/xilinx_libs/axi_firewall_v1_1_5 +axi_firewall_v1_2_1 = E:/xilinx_libs/axi_firewall_v1_2_1 +interrupt_control_v3_1_4 = E:/xilinx_libs/interrupt_control_v3_1_4 +axi_gpio_v2_0_28 = E:/xilinx_libs/axi_gpio_v2_0_28 +axi_hbicap_v1_0_4 = E:/xilinx_libs/axi_hbicap_v1_0_4 +axi_hwicap_v3_0_30 = E:/xilinx_libs/axi_hwicap_v3_0_30 +axi_iic_v2_1_2 = E:/xilinx_libs/axi_iic_v2_1_2 +axi_intc_v4_1_17 = E:/xilinx_libs/axi_intc_v4_1_17 +axi_interconnect_v1_7_20 = E:/xilinx_libs/axi_interconnect_v1_7_20 +axi_master_burst_v2_0_7 = E:/xilinx_libs/axi_master_burst_v2_0_7 +axi_msg_v1_0_8 = E:/xilinx_libs/axi_msg_v1_0_8 +axi_mcdma_v1_1_7 = E:/xilinx_libs/axi_mcdma_v1_1_7 +axi_memory_init_v1_0_7 = E:/xilinx_libs/axi_memory_init_v1_0_7 +axi_mm2s_mapper_v1_1_25 = E:/xilinx_libs/axi_mm2s_mapper_v1_1_25 +axi_mmu_v2_1_24 = E:/xilinx_libs/axi_mmu_v2_1_24 +axi_pcie_v2_9_7 = E:/xilinx_libs/axi_pcie_v2_9_7 +axi_protocol_checker_v2_0_12 = E:/xilinx_libs/axi_protocol_checker_v2_0_12 +axi_quad_spi_v3_2_25 = E:/xilinx_libs/axi_quad_spi_v3_2_25 +axi_sideband_util_v1_0_10 = E:/xilinx_libs/axi_sideband_util_v1_0_10 +axi_tft_v2_0_25 = E:/xilinx_libs/axi_tft_v2_0_25 +axi_timebase_wdt_v3_0_18 = E:/xilinx_libs/axi_timebase_wdt_v3_0_18 +axi_timer_v2_0_28 = E:/xilinx_libs/axi_timer_v2_0_28 +axi_traffic_gen_v3_0_12 = E:/xilinx_libs/axi_traffic_gen_v3_0_12 +axi_uart16550_v2_0_28 = E:/xilinx_libs/axi_uart16550_v2_0_28 +axi_uartlite_v2_0_30 = E:/xilinx_libs/axi_uartlite_v2_0_30 +axi_usb2_device_v5_0_27 = E:/xilinx_libs/axi_usb2_device_v5_0_27 +axi_utils_v2_0_6 = E:/xilinx_libs/axi_utils_v2_0_6 +axi_vdma_v6_3_14 = E:/xilinx_libs/axi_vdma_v6_3_14 +xbip_pipe_v3_0_6 = E:/xilinx_libs/xbip_pipe_v3_0_6 +xbip_dsp48_addsub_v3_0_6 = E:/xilinx_libs/xbip_dsp48_addsub_v3_0_6 +xbip_addsub_v3_0_6 = E:/xilinx_libs/xbip_addsub_v3_0_6 +c_reg_fd_v12_0_6 = E:/xilinx_libs/c_reg_fd_v12_0_6 +c_addsub_v12_0_14 = E:/xilinx_libs/c_addsub_v12_0_14 +axi_vfifo_ctrl_v2_0_28 = E:/xilinx_libs/axi_vfifo_ctrl_v2_0_28 +axi_vip_v1_1_12 = E:/xilinx_libs/axi_vip_v1_1_12 +bs_switch_v1_0_0 = E:/xilinx_libs/bs_switch_v1_0_0 +canfd_v3_0_5 = E:/xilinx_libs/canfd_v3_0_5 +can_v5_0_29 = E:/xilinx_libs/can_v5_0_29 +cic_compiler_v4_0_16 = E:/xilinx_libs/cic_compiler_v4_0_16 +xbip_bram18k_v3_0_6 = E:/xilinx_libs/xbip_bram18k_v3_0_6 +mult_gen_v12_0_18 = E:/xilinx_libs/mult_gen_v12_0_18 +cmpy_v6_0_21 = E:/xilinx_libs/cmpy_v6_0_21 +c_mux_bit_v12_0_6 = E:/xilinx_libs/c_mux_bit_v12_0_6 +c_shift_ram_v12_0_14 = E:/xilinx_libs/c_shift_ram_v12_0_14 +c_mux_bus_v12_0_6 = E:/xilinx_libs/c_mux_bus_v12_0_6 +c_gate_bit_v12_0_6 = E:/xilinx_libs/c_gate_bit_v12_0_6 +xbip_counter_v3_0_6 = E:/xilinx_libs/xbip_counter_v3_0_6 +c_counter_binary_v12_0_15 = E:/xilinx_libs/c_counter_binary_v12_0_15 +c_compare_v12_0_6 = E:/xilinx_libs/c_compare_v12_0_6 +convolution_v9_0_16 = E:/xilinx_libs/convolution_v9_0_16 +cordic_v6_0_18 = E:/xilinx_libs/cordic_v6_0_18 +cpri_v8_11_12 = E:/xilinx_libs/cpri_v8_11_12 +xbip_dsp48_acc_v3_0_6 = E:/xilinx_libs/xbip_dsp48_acc_v3_0_6 +xbip_accum_v3_0_6 = E:/xilinx_libs/xbip_accum_v3_0_6 +c_accum_v12_0_14 = E:/xilinx_libs/c_accum_v12_0_14 +dbg_intf = E:/xilinx_libs/dbg_intf +xbip_dsp48_multadd_v3_0_6 = E:/xilinx_libs/xbip_dsp48_multadd_v3_0_6 +dds_compiler_v6_0_22 = E:/xilinx_libs/dds_compiler_v6_0_22 +dft_v4_0_16 = E:/xilinx_libs/dft_v4_0_16 +dft_v4_2_3 = E:/xilinx_libs/dft_v4_2_3 +dfx_axi_shutdown_manager_v1_0_0 = E:/xilinx_libs/dfx_axi_shutdown_manager_v1_0_0 +dfx_bitstream_monitor_v1_0_1 = E:/xilinx_libs/dfx_bitstream_monitor_v1_0_1 +dfx_controller_v1_0_3 = E:/xilinx_libs/dfx_controller_v1_0_3 +dfx_decoupler_v1_0_4 = E:/xilinx_libs/dfx_decoupler_v1_0_4 +displayport_v7_0_0 = E:/xilinx_libs/displayport_v7_0_0 +displayport_v9_0_5 = E:/xilinx_libs/displayport_v9_0_5 +xbip_dsp48_mult_v3_0_6 = E:/xilinx_libs/xbip_dsp48_mult_v3_0_6 +floating_point_v7_0_20 = E:/xilinx_libs/floating_point_v7_0_20 +div_gen_v5_1_19 = E:/xilinx_libs/div_gen_v5_1_19 +dsp_macro_v1_0_2 = E:/xilinx_libs/dsp_macro_v1_0_2 +ernic_v3_1_2 = E:/xilinx_libs/ernic_v3_1_2 +etrnic_v1_1_5 = E:/xilinx_libs/etrnic_v1_1_5 +fc32_rs_fec_v1_0_21 = E:/xilinx_libs/fc32_rs_fec_v1_0_21 +fec_5g_common_v1_1_1 = E:/xilinx_libs/fec_5g_common_v1_1_1 +fir_compiler_v5_2_6 = E:/xilinx_libs/fir_compiler_v5_2_6 +fir_compiler_v7_2_18 = E:/xilinx_libs/fir_compiler_v7_2_18 +flexo_100g_rs_fec_v1_0_22 = E:/xilinx_libs/flexo_100g_rs_fec_v1_0_22 +floating_point_v7_1_14 = E:/xilinx_libs/floating_point_v7_1_14 +g709_rs_encoder_v2_2_8 = E:/xilinx_libs/g709_rs_encoder_v2_2_8 +rs_toolbox_v9_0_9 = E:/xilinx_libs/rs_toolbox_v9_0_9 +g709_rs_decoder_v2_2_10 = E:/xilinx_libs/g709_rs_decoder_v2_2_10 +g709_fec_v2_4_5 = E:/xilinx_libs/g709_fec_v2_4_5 +g975_efec_i4_v1_0_18 = E:/xilinx_libs/g975_efec_i4_v1_0_18 +g975_efec_i7_v2_0_18 = E:/xilinx_libs/g975_efec_i7_v2_0_18 +hw_trace = E:/xilinx_libs/hw_trace +icap_arb_v1_0_1 = E:/xilinx_libs/icap_arb_v1_0_1 +ieee802d3_200g_rs_fec_v2_0_5 = E:/xilinx_libs/ieee802d3_200g_rs_fec_v2_0_5 +ieee802d3_25g_rs_fec_v1_0_23 = E:/xilinx_libs/ieee802d3_25g_rs_fec_v1_0_23 +ieee802d3_400g_rs_fec_v2_0_8 = E:/xilinx_libs/ieee802d3_400g_rs_fec_v2_0_8 +ieee802d3_50g_rs_fec_v1_0_19 = E:/xilinx_libs/ieee802d3_50g_rs_fec_v1_0_19 +ieee802d3_50g_rs_fec_v2_0_11 = E:/xilinx_libs/ieee802d3_50g_rs_fec_v2_0_11 +ieee802d3_rs_fec_v2_0_15 = E:/xilinx_libs/ieee802d3_rs_fec_v2_0_15 +ldpc_v2_0_10 = E:/xilinx_libs/ldpc_v2_0_10 +xfft_v7_2_13 = E:/xilinx_libs/xfft_v7_2_13 +lte_fft_v2_0_22 = E:/xilinx_libs/lte_fft_v2_0_22 +xfft_v9_1_8 = E:/xilinx_libs/xfft_v9_1_8 +lte_fft_v2_1_6 = E:/xilinx_libs/lte_fft_v2_1_6 +mailbox_v2_1_15 = E:/xilinx_libs/mailbox_v2_1_15 +mdm_v3_2_23 = E:/xilinx_libs/mdm_v3_2_23 +mem_tg_v1_0_8 = E:/xilinx_libs/mem_tg_v1_0_8 +iomodule_v3_0 = E:/xilinx_libs/iomodule_v3_0 +lmb_bram_if_cntlr_v4_0 = E:/xilinx_libs/lmb_bram_if_cntlr_v4_0 +lmb_v10_v3_0 = E:/xilinx_libs/lmb_v10_v3_0 +axi_lite_ipif_v3_0 = E:/xilinx_libs/axi_lite_ipif_v3_0 +mdm_v3_2 = E:/xilinx_libs/mdm_v3_2 +microblaze_mcs_v2_3_6 = E:/xilinx_libs/microblaze_mcs_v2_3_6 +perf_axi_tg_v1_0_8 = E:/xilinx_libs/perf_axi_tg_v1_0_8 +polar_v1_0_10 = E:/xilinx_libs/polar_v1_0_10 +polar_v1_1_0 = E:/xilinx_libs/polar_v1_1_0 +processing_system7_vip_v1_0_14 = E:/xilinx_libs/processing_system7_vip_v1_0_14 +proc_sys_reset_v5_0_13 = E:/xilinx_libs/proc_sys_reset_v5_0_13 +pr_decoupler_v1_0_10 = E:/xilinx_libs/pr_decoupler_v1_0_10 +qdriv_pl_phy_v1_0_0 = E:/xilinx_libs/qdriv_pl_phy_v1_0_0 +quadsgmii_v3_5_8 = E:/xilinx_libs/quadsgmii_v3_5_8 +rs_decoder_v9_0_18 = E:/xilinx_libs/rs_decoder_v9_0_18 +rs_encoder_v9_0_17 = E:/xilinx_libs/rs_encoder_v9_0_17 +sd_fec_v1_1_9 = E:/xilinx_libs/sd_fec_v1_1_9 +shell_utils_addr_remap_v1_0_5 = E:/xilinx_libs/shell_utils_addr_remap_v1_0_5 +sid_v8_0_17 = E:/xilinx_libs/sid_v8_0_17 +soft_ecc_proxy_v1_0_1 = E:/xilinx_libs/soft_ecc_proxy_v1_0_1 +spdif_v2_0_26 = E:/xilinx_libs/spdif_v2_0_26 +srio_gen2_v4_1_14 = E:/xilinx_libs/srio_gen2_v4_1_14 +switch_core_top_v1_0_11 = E:/xilinx_libs/switch_core_top_v1_0_11 +tcc_decoder_3gppmm_v2_0_23 = E:/xilinx_libs/tcc_decoder_3gppmm_v2_0_23 +tcc_encoder_3gpplte_v4_0_16 = E:/xilinx_libs/tcc_encoder_3gpplte_v4_0_16 +tcc_encoder_3gpp_v5_0_18 = E:/xilinx_libs/tcc_encoder_3gpp_v5_0_18 +tmr_comparator_v1_0_5 = E:/xilinx_libs/tmr_comparator_v1_0_5 +tmr_sem_v1_0_22 = E:/xilinx_libs/tmr_sem_v1_0_22 +tri_mode_ethernet_mac_v9_0_22 = E:/xilinx_libs/tri_mode_ethernet_mac_v9_0_22 +tsn_temac_v1_0_7 = E:/xilinx_libs/tsn_temac_v1_0_7 +vby1hs_v1_0_2 = E:/xilinx_libs/vby1hs_v1_0_2 +versal_cips_ps_vip_v1_0_4 = E:/xilinx_libs/versal_cips_ps_vip_v1_0_4 +videoaxi4s_bridge_v1_0_5 = E:/xilinx_libs/videoaxi4s_bridge_v1_0_5 +viterbi_v9_1_13 = E:/xilinx_libs/viterbi_v9_1_13 +vitis_net_p4_v1_1_0 = E:/xilinx_libs/vitis_net_p4_v1_1_0 +v_dual_splitter_v1_0_9 = E:/xilinx_libs/v_dual_splitter_v1_0_9 +v_frmbuf_rd_v2_3_1 = E:/xilinx_libs/v_frmbuf_rd_v2_3_1 +v_frmbuf_rd_v2_4_0 = E:/xilinx_libs/v_frmbuf_rd_v2_4_0 +v_frmbuf_wr_v2_3_1 = E:/xilinx_libs/v_frmbuf_wr_v2_3_1 +v_frmbuf_wr_v2_4_0 = E:/xilinx_libs/v_frmbuf_wr_v2_4_0 +v_hdmi_rx1_v1_0_3 = E:/xilinx_libs/v_hdmi_rx1_v1_0_3 +v_hdmi_tx1_v1_0_3 = E:/xilinx_libs/v_hdmi_tx1_v1_0_3 +v_mix_v5_2_3 = E:/xilinx_libs/v_mix_v5_2_3 +v_multi_scaler_v1_2_3 = E:/xilinx_libs/v_multi_scaler_v1_2_3 +v_vid_gt_bridge_v1_0_5 = E:/xilinx_libs/v_vid_gt_bridge_v1_0_5 +v_vid_sdi_tx_bridge_v2_0_0 = E:/xilinx_libs/v_vid_sdi_tx_bridge_v2_0_0 +v_warp_filter_v1_1_0 = E:/xilinx_libs/v_warp_filter_v1_1_0 +v_warp_init_v1_1_0 = E:/xilinx_libs/v_warp_init_v1_1_0 +xbip_dsp48_multacc_v3_0_6 = E:/xilinx_libs/xbip_dsp48_multacc_v3_0_6 +xbip_multadd_v3_0_17 = E:/xilinx_libs/xbip_multadd_v3_0_17 +xdfe_common_v1_0_0 = E:/xilinx_libs/xdfe_common_v1_0_0 +xdfe_cc_filter_v1_0_4 = E:/xilinx_libs/xdfe_cc_filter_v1_0_4 +xdfe_cc_mixer_v1_0_4 = E:/xilinx_libs/xdfe_cc_mixer_v1_0_4 +xdfe_equalizer_v1_0_4 = E:/xilinx_libs/xdfe_equalizer_v1_0_4 +xdfe_fft_v1_0_4 = E:/xilinx_libs/xdfe_fft_v1_0_4 +xdfe_nr_prach_v1_0_4 = E:/xilinx_libs/xdfe_nr_prach_v1_0_4 +xsdbs_v1_0_2 = E:/xilinx_libs/xsdbs_v1_0_2 +zynq_ultra_ps_e_vip_v1_0_12 = E:/xilinx_libs/zynq_ultra_ps_e_vip_v1_0_12 +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +; Default or value of 3 or 2008 for VHDL-2008. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Turn on incremental compilation of modules. Default is off. +; Incremental = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +[vsim] +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = fs + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = default + +; Default run length +RunLength = 100 + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Directive to license manager: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license isn't available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license +; License = plus + +; Stop the simulator after a VHDL/Verilog assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 3 + +; Assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %% - print '%' character +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" + +; Assertion File - alternate file for storing VHDL/Verilog assertion messages +; AssertFile = assert.log + +; Default radix for all windows and commands... +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example, sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Automatic SDF compilation +; Disables automatic compilation of SDF files in flows that support it. +; Default is on, uncomment to turn off. +; NoAutoSDFCompile = 1 + +[lmc] + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both + diff --git a/tools/sim/run.bat b/tools/sim/run.bat new file mode 100644 index 0000000..814dbc5 --- /dev/null +++ b/tools/sim/run.bat @@ -0,0 +1,2 @@ +echo off +modelsim -do run.do \ No newline at end of file diff --git a/tools/sim/run.do b/tools/sim/run.do new file mode 100644 index 0000000..aae548e --- /dev/null +++ b/tools/sim/run.do @@ -0,0 +1,13 @@ +do compile.do + +vsim -voptargs="+acc" -lib work tb_pulse_channel_random_polynomials + +do waves_do/pp_polyrandom.do + +view wave +view structure +view signals + +run -all + +# End diff --git a/tools/sim/run_qlaser.do b/tools/sim/run_qlaser.do new file mode 100644 index 0000000..c67beeb --- /dev/null +++ b/tools/sim/run_qlaser.do @@ -0,0 +1,13 @@ +do compile.do + +vsim -voptargs="+acc" -lib work qlaser_dacs_pulse_tb + +do waves_do/pp_qlaser_wavetables.do + +view wave +view structure +view signals + +run -all + +# End diff --git a/tools/sim/transcript b/tools/sim/transcript new file mode 100644 index 0000000..0835fcc --- /dev/null +++ b/tools/sim/transcript @@ -0,0 +1,1788 @@ +# Reading D:/intelFPGA_lite/17.0/modelsim_ase/tcl/vsim/pref.tcl +# do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:19:40 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# -- Compiling entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulse_definition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulseposition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling entity bram_waveform +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_waveform +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# -- Compiling entity fifo_data_to_stream +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of fifo_data_to_stream +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity fifo_data_to_stream +# -- Loading package STANDARD +# End time: 02:19:43 on Mar 05,2024, Elapsed time: 0:00:03 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:19:43 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/qlaser_dac_dc_pkg.vhd ../../src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd ../../src/hdl/pkg/qlaser_pkg.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package qlaser_dac_dc_pkg +# -- Compiling package qlaser_dacs_pulse_channel_pkg +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Compiling package qlaser_pkg +# -- Compiling package body qlaser_pkg +# -- Loading package qlaser_pkg +# End time: 02:19:43 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:19:43 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakp.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(984): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(986): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1010): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1012): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1042): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1085): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1182): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1207): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1231): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1254): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1276): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1296): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1315): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1333): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1350): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1366): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1381): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1395): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1408): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1420): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1431): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1441): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1450): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1458): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1465): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1471): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1525): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1551): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1575): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1598): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1620): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1641): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1661): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1680): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1698): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1715): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1731): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1746): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1760): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1773): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1785): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1796): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1806): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1815): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1823): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1830): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2194): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2221): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2257): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2290): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2322): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2351): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2387): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2424): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2456): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:19:43 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 56 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:19:43 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakb.vhd +# -- Loading package STANDARD +# -- Compiling package body std_iopak +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(1203): (vcom-1135) Subprogram parameter asc_file is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4397): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4399): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4431): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4433): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4473): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4636): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4971): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5005): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5135): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5392): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5423): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5454): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5485): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5516): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5578): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5610): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5642): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5674): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5707): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5739): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5771): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5803): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5835): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5867): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5899): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5931): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5963): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6018): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6066): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6130): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6382): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6415): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6448): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6481): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6514): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6580): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6613): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6646): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6679): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6712): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6745): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6778): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6811): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6844): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6877): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6910): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6946): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6979): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8059): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8103): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8159): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8224): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8285): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8344): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8404): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8444): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8529): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:19:44 on Mar 05,2024, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 61 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:19:44 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/modules/qlaser_dacs_pulse_channel.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity qlaser_dacs_pulse_channel +# -- Compiling architecture channel of qlaser_dacs_pulse_channel +# -- Loading entity bram_pulse_definition +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# End time: 02:19:45 on Mar 05,2024, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:19:45 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/tb/poly_gen_nonsynth.vhdl ../../src/hdl/tb/qlaser_dacs_pulse_tb.vhdl ../../src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl ../../src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package MATH_REAL +# -- Loading package std_iopak +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity poly_gen +# -- Compiling architecture nonsynth of poly_gen +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading entity qlaser_dacs_pulse_channel +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package std_logic_textio +# -- Compiling entity tb_pulse_channel_random_polynomials +# -- Compiling architecture verify of tb_pulse_channel_random_polynomials +# End time: 02:19:45 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# vsim -voptargs=""+acc"" -lib work tb_pulse_channel_random_polynomials +# Start time: 02:19:45 on Mar 05,2024 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading ieee.std_logic_textio(body) +# Loading ieee.math_real(body) +# Loading work.std_iopak(body) +# Loading work.qlaser_dacs_pulse_channel_pkg +# Loading work.qlaser_dac_dc_pkg +# Loading work.qlaser_pkg(body) +# Loading work.tb_pulse_channel_random_polynomials(verify) +# Loading work.qlaser_dacs_pulse_channel(channel) +# Loading work.bram_pulse_definition(structure) +# Loading unisim.gnd(gnd_v) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading unisim.vpkg(body) +# Loading unisim.ramb36e2(ramb36e2_v) +# Loading work.bram_waveform(structure) +# ** Warning: Design size of 19434 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. +# Expect performance to be adversely affected. +# .main_pane.wave.interior.cs.body.pw.wf +# .main_pane.structure.interior.cs.body.struct +# .main_pane.objects.interior.cs.body.tree +# Simulation start +# Simulation done +do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:01 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# -- Compiling entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulse_definition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulseposition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulseposition +# -- Loading package STANDARD +# ** Error: ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl(139): near "STD": Identifier may not contain non-graphic character. +# ** Error: ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl(139): (vcom-1136) Unknown identifier "". +# ** Error: ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl(389): (vcom-1136) Unknown identifier "". +# ** Error: ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl(389): (vcom-1454) Formal "" of mode cannot be associated with an expression. +# ** Error: ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl(412): VHDL Compiler exiting +# End time: 02:21:03 on Mar 05,2024, Elapsed time: 0:00:02 +# Errors: 5, Warnings: 0 +# ** Error: D:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/vcom failed. +# Error in macro ./compile.do line 3 +# D:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/vcom failed. +# while executing +# "vcom ../../src/hdl/ip_gen/*.vhd*" +do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:18 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# -- Compiling entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulse_definition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulse_definition +# -- Loading package STANDARD +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(3081): near ".": syntax error +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(3090): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(417): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(419): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(421): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(423): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(425): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(427): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(429): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(431): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(433): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(435): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(437): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(439): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(441): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(443): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(445): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(447): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(449): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(451): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(453): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(455): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(457): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(459): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(461): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(463): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(465): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(467): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(469): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(471): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(473): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(475): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(477): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(479): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(481): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(483): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(485): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(487): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(489): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(491): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(493): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(495): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(497): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(499): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(501): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(503): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(505): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(507): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(509): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(512): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(531): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(541): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(551): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(561): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(571): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(581): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(591): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(601): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(611): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(621): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(631): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(641): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(651): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(661): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(671): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(681): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(691): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(701): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(711): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(721): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(731): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(741): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(751): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(761): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(771): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(781): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(791): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(801): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(811): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(821): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(831): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(841): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(851): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(861): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(871): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(881): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(891): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(901): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(911): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(921): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(931): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(941): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(951): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(961): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(971): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(981): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(991): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1001): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1011): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1021): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1031): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1041): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1051): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1061): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1071): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1081): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1091): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1101): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1111): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1121): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1131): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1141): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1151): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1161): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1171): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1181): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1191): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1201): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1211): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1221): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1231): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1241): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1251): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1261): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1271): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1281): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1291): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1301): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1311): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1321): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1331): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1341): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1351): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1361): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1371): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1381): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1391): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1401): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1411): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1421): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1431): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1441): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1451): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1461): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1471): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(5612): VHDL Compiler exiting +# End time: 02:21:19 on Mar 05,2024, Elapsed time: 0:00:01 +# Errors: 147, Warnings: 0 +# ** Error: D:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/vcom failed. +# Error in macro ./compile.do line 3 +# D:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/vcom failed. +# while executing +# "vcom ../../src/hdl/ip_gen/*.vhd*" +do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:21 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# -- Compiling entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulse_definition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulse_definition +# -- Loading package STANDARD +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(822): in protected region +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(944): near "attribute": syntax error +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(974): near "¤": (vcom-1576) . +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(974): near "": illegal character found in source +# ** Error (suppressible): ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl(1): (vcom-1491) Empty source files. +# ** Error: ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl(1): near "": illegal character found in source +# ** Error: ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl(1): VHDL Compiler exiting +# End time: 02:21:23 on Mar 05,2024, Elapsed time: 0:00:02 +# Errors: 8, Warnings: 0 +# ** Error: D:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/vcom failed. +# Error in macro ./compile.do line 3 +# D:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/vcom failed. +# while executing +# "vcom ../../src/hdl/ip_gen/*.vhd*" +do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:24 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# ** Error: ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl(122): near "îport": (vcom-1576) . +# ** Error: ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl(1): VHDL Compiler exiting +# End time: 02:21:24 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 2, Warnings: 0 +# ** Error: D:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/vcom failed. +# Error in macro ./compile.do line 3 +# D:/intelFPGA_lite/17.0/modelsim_ase/win32aloem/vcom failed. +# while executing +# "vcom ../../src/hdl/ip_gen/*.vhd*" +do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:25 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# -- Compiling entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulse_definition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulseposition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling entity bram_waveform +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_waveform +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# -- Compiling entity fifo_data_to_stream +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of fifo_data_to_stream +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity fifo_data_to_stream +# -- Loading package STANDARD +# End time: 02:21:28 on Mar 05,2024, Elapsed time: 0:00:03 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:28 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/qlaser_dac_dc_pkg.vhd ../../src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd ../../src/hdl/pkg/qlaser_pkg.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package qlaser_dac_dc_pkg +# -- Compiling package qlaser_dacs_pulse_channel_pkg +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Compiling package qlaser_pkg +# -- Compiling package body qlaser_pkg +# -- Loading package qlaser_pkg +# End time: 02:21:28 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:29 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakp.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(984): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(986): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1010): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1012): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1042): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1085): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1182): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1207): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1231): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1254): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1276): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1296): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1315): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1333): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1350): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1366): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1381): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1395): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1408): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1420): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1431): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1441): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1450): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1458): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1465): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1471): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1525): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1551): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1575): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1598): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1620): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1641): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1661): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1680): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1698): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1715): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1731): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1746): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1760): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1773): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1785): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1796): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1806): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1815): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1823): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1830): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2194): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2221): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2257): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2290): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2322): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2351): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2387): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2424): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2456): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:21:29 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 56 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:29 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakb.vhd +# -- Loading package STANDARD +# -- Compiling package body std_iopak +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(1203): (vcom-1135) Subprogram parameter asc_file is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4397): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4399): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4431): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4433): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4473): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4636): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4971): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5005): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5135): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5392): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5423): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5454): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5485): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5516): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5578): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5610): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5642): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5674): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5707): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5739): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5771): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5803): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5835): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5867): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5899): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5931): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5963): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6018): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6066): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6130): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6382): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6415): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6448): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6481): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6514): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6580): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6613): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6646): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6679): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6712): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6745): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6778): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6811): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6844): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6877): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6910): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6946): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6979): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8059): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8103): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8159): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8224): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8285): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8344): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8404): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8444): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8529): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:21:29 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 61 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:30 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/modules/qlaser_dacs_pulse_channel.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity qlaser_dacs_pulse_channel +# -- Compiling architecture channel of qlaser_dacs_pulse_channel +# -- Loading entity bram_pulse_definition +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# End time: 02:21:30 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:21:30 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/tb/poly_gen_nonsynth.vhdl ../../src/hdl/tb/qlaser_dacs_pulse_tb.vhdl ../../src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl ../../src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package MATH_REAL +# -- Loading package std_iopak +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity poly_gen +# -- Compiling architecture nonsynth of poly_gen +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading entity qlaser_dacs_pulse_channel +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package std_logic_textio +# -- Compiling entity tb_pulse_channel_random_polynomials +# -- Compiling architecture verify of tb_pulse_channel_random_polynomials +# End time: 02:21:30 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# End time: 02:21:32 on Mar 05,2024, Elapsed time: 0:01:47 +# Errors: 171, Warnings: 118 +# vsim -voptargs=""+acc"" -lib work tb_pulse_channel_random_polynomials +# Start time: 02:21:32 on Mar 05,2024 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading ieee.std_logic_textio(body) +# Loading ieee.math_real(body) +# Loading work.std_iopak(body) +# Loading work.qlaser_dacs_pulse_channel_pkg +# Loading work.qlaser_dac_dc_pkg +# Loading work.qlaser_pkg(body) +# Loading work.tb_pulse_channel_random_polynomials(verify) +# Loading work.qlaser_dacs_pulse_channel(channel) +# Loading work.bram_pulse_definition(structure) +# Loading unisim.gnd(gnd_v) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading unisim.vpkg(body) +# Loading unisim.ramb36e2(ramb36e2_v) +# Loading work.bram_waveform(structure) +# ** Warning: Design size of 19434 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. +# Expect performance to be adversely affected. +# .main_pane.wave.interior.cs.body.pw.wf +# .main_pane.structure.interior.cs.body.struct +# .main_pane.objects.interior.cs.body.tree +# Simulation start +# Simulation done +do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:22:32 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# -- Compiling entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulse_definition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulseposition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling entity bram_waveform +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_waveform +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# -- Compiling entity fifo_data_to_stream +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of fifo_data_to_stream +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity fifo_data_to_stream +# -- Loading package STANDARD +# End time: 02:22:35 on Mar 05,2024, Elapsed time: 0:00:03 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:22:35 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/qlaser_dac_dc_pkg.vhd ../../src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd ../../src/hdl/pkg/qlaser_pkg.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package qlaser_dac_dc_pkg +# -- Compiling package qlaser_dacs_pulse_channel_pkg +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Compiling package qlaser_pkg +# -- Compiling package body qlaser_pkg +# -- Loading package qlaser_pkg +# End time: 02:22:35 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:22:35 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakp.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(984): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(986): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1010): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1012): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1042): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1085): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1182): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1207): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1231): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1254): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1276): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1296): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1315): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1333): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1350): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1366): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1381): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1395): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1408): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1420): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1431): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1441): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1450): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1458): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1465): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1471): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1525): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1551): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1575): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1598): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1620): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1641): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1661): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1680): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1698): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1715): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1731): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1746): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1760): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1773): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1785): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1796): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1806): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1815): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1823): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1830): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2194): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2221): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2257): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2290): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2322): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2351): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2387): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2424): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2456): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:22:36 on Mar 05,2024, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 56 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:22:36 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakb.vhd +# -- Loading package STANDARD +# -- Compiling package body std_iopak +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(1203): (vcom-1135) Subprogram parameter asc_file is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4397): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4399): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4431): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4433): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4473): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4636): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4971): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5005): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5135): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5392): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5423): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5454): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5485): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5516): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5578): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5610): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5642): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5674): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5707): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5739): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5771): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5803): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5835): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5867): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5899): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5931): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5963): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6018): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6066): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6130): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6382): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6415): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6448): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6481): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6514): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6580): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6613): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6646): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6679): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6712): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6745): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6778): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6811): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6844): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6877): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6910): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6946): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6979): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8059): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8103): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8159): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8224): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8285): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8344): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8404): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8444): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8529): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:22:36 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 61 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:22:36 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/modules/qlaser_dacs_pulse_channel.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity qlaser_dacs_pulse_channel +# -- Compiling architecture channel of qlaser_dacs_pulse_channel +# -- Loading entity bram_pulse_definition +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# End time: 02:22:37 on Mar 05,2024, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:22:37 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/tb/poly_gen_nonsynth.vhdl ../../src/hdl/tb/qlaser_dacs_pulse_tb.vhdl ../../src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl ../../src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package MATH_REAL +# -- Loading package std_iopak +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity poly_gen +# -- Compiling architecture nonsynth of poly_gen +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading entity qlaser_dacs_pulse_channel +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package std_logic_textio +# -- Compiling entity tb_pulse_channel_random_polynomials +# -- Compiling architecture verify of tb_pulse_channel_random_polynomials +# End time: 02:22:37 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# End time: 02:22:39 on Mar 05,2024, Elapsed time: 0:01:07 +# Errors: 0, Warnings: 118 +# vsim -voptargs=""+acc"" -lib work tb_pulse_channel_random_polynomials +# Start time: 02:22:39 on Mar 05,2024 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading ieee.std_logic_textio(body) +# Loading ieee.math_real(body) +# Loading work.std_iopak(body) +# Loading work.qlaser_dacs_pulse_channel_pkg +# Loading work.qlaser_dac_dc_pkg +# Loading work.qlaser_pkg(body) +# Loading work.tb_pulse_channel_random_polynomials(verify) +# Loading work.qlaser_dacs_pulse_channel(channel) +# Loading work.bram_pulse_definition(structure) +# Loading unisim.gnd(gnd_v) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading unisim.vpkg(body) +# Loading unisim.ramb36e2(ramb36e2_v) +# Loading work.bram_waveform(structure) +# ** Warning: Design size of 19437 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. +# Expect performance to be adversely affected. +# .main_pane.wave.interior.cs.body.pw.wf +# .main_pane.structure.interior.cs.body.struct +# .main_pane.objects.interior.cs.body.tree +# Simulation start +# Simulation done +do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:23:15 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# -- Compiling entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulse_definition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulseposition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling entity bram_waveform +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_waveform +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# -- Compiling entity fifo_data_to_stream +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of fifo_data_to_stream +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity fifo_data_to_stream +# -- Loading package STANDARD +# End time: 02:23:19 on Mar 05,2024, Elapsed time: 0:00:04 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:23:19 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/qlaser_dac_dc_pkg.vhd ../../src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd ../../src/hdl/pkg/qlaser_pkg.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package qlaser_dac_dc_pkg +# -- Compiling package qlaser_dacs_pulse_channel_pkg +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Compiling package qlaser_pkg +# -- Compiling package body qlaser_pkg +# -- Loading package qlaser_pkg +# End time: 02:23:19 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:23:19 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakp.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(984): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(986): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1010): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1012): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1042): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1085): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1182): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1207): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1231): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1254): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1276): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1296): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1315): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1333): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1350): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1366): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1381): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1395): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1408): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1420): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1431): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1441): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1450): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1458): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1465): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1471): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1525): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1551): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1575): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1598): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1620): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1641): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1661): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1680): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1698): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1715): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1731): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1746): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1760): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1773): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1785): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1796): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1806): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1815): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1823): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1830): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2194): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2221): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2257): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2290): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2322): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2351): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2387): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2424): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2456): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:23:19 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 56 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:23:19 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakb.vhd +# -- Loading package STANDARD +# -- Compiling package body std_iopak +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(1203): (vcom-1135) Subprogram parameter asc_file is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4397): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4399): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4431): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4433): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4473): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4636): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4971): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5005): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5135): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5392): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5423): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5454): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5485): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5516): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5578): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5610): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5642): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5674): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5707): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5739): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5771): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5803): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5835): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5867): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5899): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5931): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5963): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6018): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6066): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6130): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6382): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6415): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6448): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6481): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6514): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6580): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6613): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6646): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6679): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6712): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6745): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6778): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6811): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6844): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6877): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6910): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6946): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6979): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8059): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8103): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8159): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8224): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8285): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8344): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8404): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8444): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8529): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:23:20 on Mar 05,2024, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 61 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:23:20 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/modules/qlaser_dacs_pulse_channel.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity qlaser_dacs_pulse_channel +# -- Compiling architecture channel of qlaser_dacs_pulse_channel +# -- Loading entity bram_pulse_definition +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# End time: 02:23:21 on Mar 05,2024, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:23:21 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/tb/poly_gen_nonsynth.vhdl ../../src/hdl/tb/qlaser_dacs_pulse_tb.vhdl ../../src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl ../../src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package MATH_REAL +# -- Loading package std_iopak +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity poly_gen +# -- Compiling architecture nonsynth of poly_gen +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading entity qlaser_dacs_pulse_channel +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package std_logic_textio +# -- Compiling entity tb_pulse_channel_random_polynomials +# -- Compiling architecture verify of tb_pulse_channel_random_polynomials +# End time: 02:23:21 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# End time: 02:23:22 on Mar 05,2024, Elapsed time: 0:00:43 +# Errors: 0, Warnings: 118 +# vsim -voptargs=""+acc"" -lib work tb_pulse_channel_random_polynomials +# Start time: 02:23:22 on Mar 05,2024 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading ieee.std_logic_textio(body) +# Loading ieee.math_real(body) +# Loading work.std_iopak(body) +# Loading work.qlaser_dacs_pulse_channel_pkg +# Loading work.qlaser_dac_dc_pkg +# Loading work.qlaser_pkg(body) +# Loading work.tb_pulse_channel_random_polynomials(verify) +# Loading work.qlaser_dacs_pulse_channel(channel) +# Loading work.bram_pulse_definition(structure) +# Loading unisim.gnd(gnd_v) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading unisim.vpkg(body) +# Loading unisim.ramb36e2(ramb36e2_v) +# Loading work.bram_waveform(structure) +# ** Warning: Design size of 19437 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. +# Expect performance to be adversely affected. +# .main_pane.wave.interior.cs.body.pw.wf +# .main_pane.structure.interior.cs.body.struct +# .main_pane.objects.interior.cs.body.tree +# Simulation start +# Simulation done +do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:24:09 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# -- Compiling entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulse_definition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulseposition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling entity bram_waveform +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_waveform +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# -- Compiling entity fifo_data_to_stream +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of fifo_data_to_stream +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity fifo_data_to_stream +# -- Loading package STANDARD +# End time: 02:24:12 on Mar 05,2024, Elapsed time: 0:00:03 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:24:12 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/qlaser_dac_dc_pkg.vhd ../../src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd ../../src/hdl/pkg/qlaser_pkg.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package qlaser_dac_dc_pkg +# -- Compiling package qlaser_dacs_pulse_channel_pkg +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Compiling package qlaser_pkg +# -- Compiling package body qlaser_pkg +# -- Loading package qlaser_pkg +# End time: 02:24:12 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:24:12 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakp.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(984): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(986): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1010): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1012): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1042): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1085): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1182): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1207): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1231): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1254): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1276): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1296): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1315): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1333): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1350): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1366): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1381): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1395): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1408): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1420): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1431): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1441): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1450): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1458): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1465): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1471): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1525): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1551): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1575): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1598): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1620): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1641): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1661): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1680): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1698): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1715): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1731): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1746): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1760): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1773): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1785): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1796): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1806): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1815): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1823): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1830): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2194): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2221): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2257): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2290): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2322): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2351): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2387): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2424): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2456): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:24:12 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 56 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:24:13 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakb.vhd +# -- Loading package STANDARD +# -- Compiling package body std_iopak +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(1203): (vcom-1135) Subprogram parameter asc_file is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4397): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4399): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4431): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4433): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4473): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4636): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4971): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5005): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5135): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5392): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5423): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5454): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5485): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5516): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5578): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5610): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5642): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5674): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5707): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5739): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5771): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5803): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5835): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5867): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5899): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5931): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5963): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6018): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6066): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6130): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6382): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6415): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6448): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6481): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6514): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6580): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6613): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6646): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6679): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6712): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6745): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6778): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6811): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6844): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6877): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6910): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6946): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6979): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8059): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8103): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8159): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8224): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8285): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8344): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8404): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8444): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8529): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:24:13 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 61 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:24:13 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/modules/qlaser_dacs_pulse_channel.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity qlaser_dacs_pulse_channel +# -- Compiling architecture channel of qlaser_dacs_pulse_channel +# -- Loading entity bram_pulse_definition +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# End time: 02:24:14 on Mar 05,2024, Elapsed time: 0:00:01 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:24:14 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/tb/poly_gen_nonsynth.vhdl ../../src/hdl/tb/qlaser_dacs_pulse_tb.vhdl ../../src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl ../../src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package MATH_REAL +# -- Loading package std_iopak +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity poly_gen +# -- Compiling architecture nonsynth of poly_gen +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading entity qlaser_dacs_pulse_channel +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package std_logic_textio +# -- Compiling entity tb_pulse_channel_random_polynomials +# -- Compiling architecture verify of tb_pulse_channel_random_polynomials +# End time: 02:24:14 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# End time: 02:24:15 on Mar 05,2024, Elapsed time: 0:00:53 +# Errors: 0, Warnings: 118 +# vsim -voptargs=""+acc"" -lib work tb_pulse_channel_random_polynomials +# Start time: 02:24:15 on Mar 05,2024 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading ieee.std_logic_textio(body) +# Loading ieee.math_real(body) +# Loading work.std_iopak(body) +# Loading work.qlaser_dacs_pulse_channel_pkg +# Loading work.qlaser_dac_dc_pkg +# Loading work.qlaser_pkg(body) +# Loading work.tb_pulse_channel_random_polynomials(verify) +# Loading work.qlaser_dacs_pulse_channel(channel) +# Loading work.bram_pulse_definition(structure) +# Loading unisim.gnd(gnd_v) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading unisim.vpkg(body) +# Loading unisim.ramb36e2(ramb36e2_v) +# Loading work.bram_waveform(structure) +# ** Warning: Design size of 19437 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. +# Expect performance to be adversely affected. +# .main_pane.wave.interior.cs.body.pw.wf +# .main_pane.structure.interior.cs.body.struct +# .main_pane.objects.interior.cs.body.tree +# Simulation start +# Simulation done +do run.do +# ** Warning: (vlib-34) Library already exists at "work". +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:25:48 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl ../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl +# -- Loading package STANDARD +# -- Compiling entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulse_definition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulse_definition +# -- Loading package STANDARD +# -- Compiling entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_pulseposition +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_pulseposition +# -- Loading package STANDARD +# -- Compiling entity bram_waveform +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of bram_waveform +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# -- Compiling entity fifo_data_to_stream +# -- Loading package STANDARD +# -- Compiling architecture STRUCTURE of fifo_data_to_stream +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading entity fifo_data_to_stream +# -- Loading package STANDARD +# End time: 02:25:51 on Mar 05,2024, Elapsed time: 0:00:03 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:25:52 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/qlaser_dac_dc_pkg.vhd ../../src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd ../../src/hdl/pkg/qlaser_pkg.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package qlaser_dac_dc_pkg +# -- Compiling package qlaser_dacs_pulse_channel_pkg +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Compiling package qlaser_pkg +# -- Compiling package body qlaser_pkg +# -- Loading package qlaser_pkg +# End time: 02:25:52 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:25:52 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakp.vhd +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Compiling package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(984): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(986): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1010): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1012): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1042): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1085): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1182): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1207): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1231): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1254): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1276): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1296): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1315): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1333): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1350): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1366): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1381): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1395): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1408): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1420): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1431): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1441): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1450): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1458): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1465): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1471): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1525): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1551): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1575): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1598): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1620): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1641): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1661): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1680): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1698): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1715): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1731): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1746): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1760): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1773): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1785): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1796): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1806): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1815): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1823): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(1830): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2194): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2221): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2257): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2290): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2322): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2351): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2387): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2424): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2456): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakp.vhd(2486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:25:52 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 56 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:25:52 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/pkg/iopakb.vhd +# -- Loading package STANDARD +# -- Compiling package body std_iopak +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package std_iopak +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(1203): (vcom-1135) Subprogram parameter asc_file is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4397): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4399): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4431): (vcom-1135) Subprogram parameter in_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4433): (vcom-1135) Subprogram parameter out_fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4473): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4636): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(4971): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5005): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5135): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5392): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5423): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5454): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5485): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5516): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5578): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5610): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5642): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5674): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5707): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5739): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5771): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5803): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5835): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5867): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5899): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5931): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(5963): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6018): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6066): (vcom-1135) Subprogram parameter fptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6130): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6382): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6415): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6448): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6481): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6514): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6547): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6580): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6613): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6646): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6679): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6712): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6745): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6778): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6811): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6844): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6877): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6910): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6946): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(6979): (vcom-1135) Subprogram parameter file_ptr is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8059): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8103): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8159): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8224): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8285): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8344): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8404): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8444): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8486): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# ** Warning: ../../src/hdl/pkg/iopakb.vhd(8529): (vcom-1135) Subprogram parameter stream is declared using VHDL 1987 syntax. +# End time: 02:25:52 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 61 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:25:53 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/modules/qlaser_dacs_pulse_channel.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity qlaser_dacs_pulse_channel +# -- Compiling architecture channel of qlaser_dacs_pulse_channel +# -- Loading entity bram_pulse_definition +# -- Loading entity bram_waveform +# -- Loading package STANDARD +# End time: 02:25:53 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 +# Start time: 02:25:53 on Mar 05,2024 +# vcom -reportprogress 300 ../../src/hdl/tb/poly_gen_nonsynth.vhdl ../../src/hdl/tb/qlaser_dacs_pulse_tb.vhdl ../../src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl ../../src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl +# -- Loading package STANDARD +# -- Loading package TEXTIO +# -- Loading package std_logic_1164 +# -- Loading package NUMERIC_STD +# -- Loading package MATH_REAL +# -- Loading package std_iopak +# -- Loading package qlaser_dacs_pulse_channel_pkg +# -- Compiling entity poly_gen +# -- Compiling architecture nonsynth of poly_gen +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package qlaser_dac_dc_pkg +# -- Loading package qlaser_pkg +# -- Loading entity qlaser_dacs_pulse_channel +# -- Compiling entity tb_cpubus_dacs_pulse_channel +# -- Compiling architecture behave of tb_cpubus_dacs_pulse_channel +# -- Loading package std_logic_textio +# -- Compiling entity tb_pulse_channel_random_polynomials +# -- Compiling architecture verify of tb_pulse_channel_random_polynomials +# End time: 02:25:53 on Mar 05,2024, Elapsed time: 0:00:00 +# Errors: 0, Warnings: 0 +# End time: 02:25:55 on Mar 05,2024, Elapsed time: 0:01:40 +# Errors: 0, Warnings: 118 +# vsim -voptargs=""+acc"" -lib work tb_pulse_channel_random_polynomials +# Start time: 02:25:55 on Mar 05,2024 +# Loading std.standard +# Loading std.textio(body) +# Loading ieee.std_logic_1164(body) +# Loading ieee.numeric_std(body) +# Loading ieee.std_logic_textio(body) +# Loading ieee.math_real(body) +# Loading work.std_iopak(body) +# Loading work.qlaser_dacs_pulse_channel_pkg +# Loading work.qlaser_dac_dc_pkg +# Loading work.qlaser_pkg(body) +# Loading work.tb_pulse_channel_random_polynomials(verify) +# Loading work.qlaser_dacs_pulse_channel(channel) +# Loading work.bram_pulse_definition(structure) +# Loading unisim.gnd(gnd_v) +# Loading ieee.vital_timing(body) +# Loading ieee.vital_primitives(body) +# Loading unisim.vpkg(body) +# Loading unisim.ramb36e2(ramb36e2_v) +# Loading work.bram_waveform(structure) +# ** Warning: Design size of 19437 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity. +# Expect performance to be adversely affected. +# .main_pane.wave.interior.cs.body.pw.wf +# .main_pane.structure.interior.cs.body.struct +# .main_pane.objects.interior.cs.body.tree +# Simulation start +# Simulation done +write format wave -window .main_pane.wave.interior.cs.body.pw.wf E:/github/PulseChannel/tools/sim/waves_do/pp_polyrandom.do diff --git a/tools/sim/vsim.wlf b/tools/sim/vsim.wlf new file mode 100644 index 0000000..0967860 Binary files /dev/null and b/tools/sim/vsim.wlf differ diff --git a/tools/sim/wave_values.txt b/tools/sim/wave_values.txt new file mode 100644 index 0000000..f0f459c --- /dev/null +++ b/tools/sim/wave_values.txt @@ -0,0 +1,4096 @@ +0.000000e+00 +-0.000000e+00 +0.000000e+00 +2.997817e-01 +6.006957e-01 +9.027420e-01 +1.205921e+00 +1.510232e+00 +1.815675e+00 +2.122251e+00 +2.429959e+00 +2.738799e+00 +3.048772e+00 +3.359877e+00 +3.672115e+00 +3.985484e+00 +4.299986e+00 +4.615621e+00 +4.932388e+00 +5.250287e+00 +5.569318e+00 +5.889482e+00 +6.210778e+00 +6.533207e+00 +6.856768e+00 +7.181461e+00 +7.507286e+00 +7.834244e+00 +8.162334e+00 +8.491557e+00 +8.821912e+00 +9.153399e+00 +9.486019e+00 +9.819771e+00 +1.015465e+01 +1.049067e+01 +1.082782e+01 +1.116610e+01 +1.150552e+01 +1.184606e+01 +1.218774e+01 +1.253055e+01 +1.287449e+01 +1.321957e+01 +1.356578e+01 +1.391312e+01 +1.426159e+01 +1.461119e+01 +1.496193e+01 +1.531380e+01 +1.566680e+01 +1.602094e+01 +1.637620e+01 +1.673260e+01 +1.709013e+01 +1.744880e+01 +1.780859e+01 +1.816952e+01 +1.853158e+01 +1.889477e+01 +1.925910e+01 +1.962456e+01 +1.999115e+01 +2.035887e+01 +2.072772e+01 +2.109771e+01 +2.146883e+01 +2.184108e+01 +2.221446e+01 +2.258898e+01 +2.296463e+01 +2.334141e+01 +2.371932e+01 +2.409837e+01 +2.447855e+01 +2.485986e+01 +2.524230e+01 +2.562587e+01 +2.601058e+01 +2.639642e+01 +2.678339e+01 +2.717150e+01 +2.756073e+01 +2.795110e+01 +2.834261e+01 +2.873524e+01 +2.912900e+01 +2.952390e+01 +2.991993e+01 +3.031710e+01 +3.071539e+01 +3.111482e+01 +3.151538e+01 +3.191707e+01 +3.231990e+01 +3.272385e+01 +3.312894e+01 +3.353517e+01 +3.394252e+01 +3.435101e+01 +3.476063e+01 +3.517138e+01 +3.558326e+01 +3.599628e+01 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+1.017860e+04 +1.018463e+04 +1.019067e+04 +1.019671e+04 +1.020275e+04 +1.020880e+04 +1.021485e+04 +1.022090e+04 +1.022695e+04 +1.023300e+04 +1.023906e+04 +1.024512e+04 +1.025118e+04 +1.025724e+04 +1.026331e+04 +1.026937e+04 diff --git a/tools/sim/waves_do/pp_polyrandom.do b/tools/sim/waves_do/pp_polyrandom.do new file mode 100644 index 0000000..428d3e3 --- /dev/null +++ b/tools/sim/waves_do/pp_polyrandom.do @@ -0,0 +1,25 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_pulse_channel_random_polynomials/degrees +add wave -noupdate /tb_pulse_channel_random_polynomials/times +add wave -noupdate /tb_pulse_channel_random_polynomials/direction +add wave -noupdate -clampanalog 1 -format Analog-Backstep -max 10300.0 -radix decimal /tb_pulse_channel_random_polynomials/wave_values +add wave -noupdate /tb_pulse_channel_random_polynomials/wave_values_next +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {42167186887 fs} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {0 fs} {42845964444 fs} diff --git a/tools/sim/waves_do/pp_qlaser_wavetables.do b/tools/sim/waves_do/pp_qlaser_wavetables.do new file mode 100644 index 0000000..94622f5 --- /dev/null +++ b/tools/sim/waves_do/pp_qlaser_wavetables.do @@ -0,0 +1,59 @@ +onerror {resume} +quietly virtual signal -install /qlaser_dacs_pulse_tb/u_dac_pulse { /qlaser_dacs_pulse_tb/u_dac_pulse/reg_pulse_time(31 downto 16)} reg_pulse_time_31_16 +quietly virtual signal -install /qlaser_dacs_pulse_tb/u_dac_pulse { /qlaser_dacs_pulse_tb/u_dac_pulse/reg_pulse_time(15 downto 0)} reg_pulse_time_15_0 +quietly WaveActivateNextPane {} 0 +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/clk +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/start +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/reset +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/busy +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/cnt_time +add wave -noupdate -radix binary /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_addr +add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_wdata +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_wr +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_sel +add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_rdata +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/cpu_rdata_dv +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_addra +add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_dina +add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_douta +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_we +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/sm_state +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/pc +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_addrb +add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/ram_pulse_doutb +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/reg_pulse_time +add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/reg_scale_gain +add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/reg_scale_time +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/reg_wave_start_addr +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/reg_wave_length +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/reg_pulse_flattop +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_wea +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_addra +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_dina +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_douta +add wave -noupdate -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_addrb +add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/ram_waveform_doutb +add wave -noupdate -radix hexadecimal /qlaser_dacs_pulse_tb/u_dac_pulse/sm_wavedata +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/sm_wavedata_dv +add wave -noupdate -format Analog-Step -height 74 -max 204.0 -radix unsigned /qlaser_dacs_pulse_tb/u_dac_pulse/axis_tdata +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/axis_tvalid +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/axis_tlast +add wave -noupdate /qlaser_dacs_pulse_tb/u_dac_pulse/axis_tready +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 2} {62275000000 fs} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 163 +configure wave -valuecolwidth 99 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits fs +update +WaveRestoreZoom {61852729312 fs} {62817270688 fs} diff --git a/tools/sim/waves_do/pp_rw_cpu.do b/tools/sim/waves_do/pp_rw_cpu.do new file mode 100644 index 0000000..918713f --- /dev/null +++ b/tools/sim/waves_do/pp_rw_cpu.do @@ -0,0 +1,34 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy +add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wdata +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wr +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_sel +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {480433536 fs} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 172 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits fs +update +WaveRestoreZoom {0 fs} {1953088753 fs} diff --git a/tools/sim/waves_do/pp_sm.do b/tools/sim/waves_do/pp_sm.do new file mode 100644 index 0000000..ecbde72 --- /dev/null +++ b/tools/sim/waves_do/pp_sm.do @@ -0,0 +1,42 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time +add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wdata +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wr +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_sel +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {277726970613 fs} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 99 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits fs +update +WaveRestoreZoom {277686713216 fs} {277803286784 fs} diff --git a/tools/sim/waves_do/pp_sm_wavetables.do b/tools/sim/waves_do/pp_sm_wavetables.do new file mode 100644 index 0000000..0549379 --- /dev/null +++ b/tools/sim/waves_do/pp_sm_wavetables.do @@ -0,0 +1,66 @@ +onerror {resume} +quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time(31 downto 16)} reg_pulse_time_31_16 +quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time(15 downto 0)} reg_pulse_time_15_0 +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/start +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time +add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wdata +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wr +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_sel +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state_d1 +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_scale_gain +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_scale_time +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_wave_start_addr +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_wave_length +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_wave_end_addr +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_wea +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_addra +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_dina +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_douta +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_addr +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_wave_top +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_wave_len +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_last_addr +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_addrb +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_doutb +add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_wavedata +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_wavedata_dv +add wave -noupdate -format Analog-Step -height 74 -max 70.0 -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tdata +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tvalid +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tlast +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tready +add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/done_seq +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 2} {62521930491 fs} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 163 +configure wave -valuecolwidth 99 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits fs +update +WaveRestoreZoom {62366292805 fs} {63694887423 fs} diff --git a/tools/sim/work/_info b/tools/sim/work/_info new file mode 100644 index 0000000..50e61ff --- /dev/null +++ b/tools/sim/work/_info @@ -0,0 +1,1590 @@ +m255 +K4 +z2 +13 +!s112 1.1 +!i10d 8192 +!i10e 25 +!i10f 100 +cModel Technology +Z0 dE:/github/PulseChannel/tools/sim +EsMlsj2YTrVrQ30VUXC9A9zggxemV1ljAH5S0yYSaPtBglVtxRJuD2i4SIQwdr2VKgL2efdu8Wg/T09hZsgpnhg== +Z1 w1708918545 +Z2 DPx4 ieee 11 numeric_std 0 22 :ASDNFgHXf_ih3J@9F3Ze1 +Z3 DPx6 unisim 11 vcomponents 0 22 LBCWZ3`cMODZ;DmGj4eXY2 +Z4 DPx3 std 6 textio 0 22 zE1`LPoLg^DX3Oz^4Fj1K3 +Z5 DPx4 ieee 14 std_logic_1164 0 22 eNV`TJ_GofJTzYa?f<@Oe1 +R0 +Z6 8../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl +Z7 F../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl +l0 +L755 +Vg?Uga`^ZD2_e]GUW0eTDU1 +!s100 hWaO9A@e2YolCE9W[fhko0 +Z8 OV;C;10.5b;63 +!i8a 1357845664 +32 +Z9 !s110 1709634350 +!i10b 1 +Z10 !s108 1709634348.000000 +Z11 !s90 -reportprogress|300|../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl|../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl|../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl|../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl| +Z12 !s107 ../../src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl|../../src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl|../../src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl|../../src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl| +!i113 1 +Z13 tExplicit 1 CvgOpt 0 +ne0b634c +AZy+cMXGLmPuP0aGD89zIGg== +Z14 DEx4 work 56 \bram_waveform_blk_mem_gen_prim_wrapper__parameterized0\ 0 22 b:nm>ASAZ`KRP2;7TO1?S3 +R2 +R3 +R4 +R5 +Z15 DEx4 work 54 \bram_waveform_blk_mem_gen_prim_width__parameterized0\ 0 22 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F../../src/hdl/tb/tb_pulse_channel_random_polynomials.vhdl +l0 +L25 +VjBo^TKL=6XFhYLQP3[B<@2 +!s100 =OU[8z02 +R8 +32 +R58 +!i10b 1 +R59 +R60 +R61 +!i113 1 +R13 +Averify +R71 +R72 +R77 +R53 +R54 +R55 +R87 +R5 +R4 +R2 +Z90 DEx4 work 35 tb_pulse_channel_random_polynomials 0 22 jBo^TKL=6XFhYLQP3[B<@2 +l277 +L28 +Vg][83WXmn78CQKEc>G;`U0 +!s100 j_S2[48^;5OXZWDO7nHEQ0 +R8 +32 +R58 +!i10b 1 +R59 +R60 +R61 +!i113 1 +R13 diff --git a/tools/sim/work/_lib.qdb b/tools/sim/work/_lib.qdb new file mode 100644 index 0000000..e39bf7a Binary files /dev/null and b/tools/sim/work/_lib.qdb differ diff --git a/tools/sim/work/_lib1_7.qdb b/tools/sim/work/_lib1_7.qdb new file mode 100644 index 0000000..ac0d6d6 Binary files /dev/null and b/tools/sim/work/_lib1_7.qdb differ diff --git a/tools/sim/work/_lib1_7.qpg b/tools/sim/work/_lib1_7.qpg new file mode 100644 index 0000000..364b730 Binary files /dev/null and b/tools/sim/work/_lib1_7.qpg differ diff --git a/tools/sim/work/_lib1_7.qtl b/tools/sim/work/_lib1_7.qtl new file mode 100644 index 0000000..034cd6a Binary files /dev/null and b/tools/sim/work/_lib1_7.qtl differ diff --git a/tools/sim/work/_vmake b/tools/sim/work/_vmake new file mode 100644 index 0000000..37aa36a --- /dev/null +++ b/tools/sim/work/_vmake @@ -0,0 +1,4 @@ +m255 +K4 +z0 +cModel Technology diff --git a/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci b/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci new file mode 100644 index 0000000..8ed0677 --- /dev/null +++ b/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci @@ -0,0 +1,422 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bram_pulse_definition + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 10 + 10 + 1 + 4 + 0 + 1 + 9 + 1 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 4.465107 mW + zynquplus + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + bram_pulse_definition.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 1024 + 1024 + 1 + 1 + 32 + 32 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1024 + 1024 + READ_FIRST + READ_FIRST + 32 + 32 + zynquplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + bram_pulse_definition + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + True_Dual_Port_RAM + READ_FIRST + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 32 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 1024 + 32 + 32 + No_ECC + false + false + false + Stand_Alone + zynquplus + xilinx.com:zcu102:part0:3.4 + + xczu9eg + ffvb1156 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + ../../../prj/zcu_pulse_channel.gen/sources_1/ip/bram_pulse_definition + + . + 2022.1.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/xilinx-zcu/bram_pulseposition/bram_pulseposition.xci b/tools/xilinx-zcu/bram_pulseposition/bram_pulseposition.xci new file mode 100644 index 0000000..e0fd654 --- /dev/null +++ b/tools/xilinx-zcu/bram_pulseposition/bram_pulseposition.xci @@ -0,0 +1,119 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bram_pulseposition + + + 4 + 0 + 16 + ./ + zynquplus + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + no_coe_file_loaded + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 96 + bram_pulseposition + 0 + ce_overrides_sync_controls + no_coe_file_loaded + false + false + 96 + 0 + 16 + 16 + non_registered + false + false + non_registered + dual_port_ram + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynquplus + xilinx.com:zcu102:part0:3.4 + + xczu9eg + ffvb1156 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 13 + TRUE + ../../../prj/zcu_pulse_channel.gen/sources_1/ip/bram_pulseposition + + . + 2022.1.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + diff --git a/tools/xilinx-zcu/bram_waveform/bram_waveform.xci b/tools/xilinx-zcu/bram_waveform/bram_waveform.xci new file mode 100644 index 0000000..e93f3a5 --- /dev/null +++ b/tools/xilinx-zcu/bram_waveform/bram_waveform.xci @@ -0,0 +1,422 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bram_waveform + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 11 + 12 + 1 + 4 + 0 + 1 + 9 + 1 + 0 + 2 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 7.369992 mW + zynquplus + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + bram_waveform.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 2048 + 4096 + 1 + 1 + 32 + 16 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 2048 + 4096 + READ_FIRST + READ_FIRST + 32 + 16 + zynquplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + true + 9 + NONE + no_coe_file_loaded + ALL + bram_waveform + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + True_Dual_Port_RAM + READ_FIRST + READ_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 16 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 2048 + 32 + 16 + No_ECC + false + false + false + Stand_Alone + zynquplus + xilinx.com:zcu102:part0:3.4 + + xczu9eg + ffvb1156 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + ../../../prj/zcu_pulse_channel.gen/sources_1/ip/bram_waveform + + . + 2022.1.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/xilinx-zcu/fifo_data_to_stream/fifo_data_to_stream.xci b/tools/xilinx-zcu/fifo_data_to_stream/fifo_data_to_stream.xci new file mode 100644 index 0000000..19bf8f7 --- /dev/null +++ b/tools/xilinx-zcu/fifo_data_to_stream/fifo_data_to_stream.xci @@ -0,0 +1,635 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_data_to_stream + + + + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 9 + BlankString + 32 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 16 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynquplus + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 6 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 4 + BlankString + 1 + 0 + 0 + 0 + 2 + 1 + 512x36 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 510 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 509 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 9 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 9 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_data_to_stream + 64 + false + 9 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Builtin_FIFO + 0 + 510 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 509 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 32 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 16 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Synchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + true + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 9 + true + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynquplus + xilinx.com:zcu102:part0:3.4 + + xczu9eg + ffvb1156 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 7 + TRUE + ../../../prj/zcu_pulse_channel.gen/sources_1/ip/fifo_data_to_stream + + . + 2022.1.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/xilinx-zcu/pinout_zcu.xdc b/tools/xilinx-zcu/pinout_zcu.xdc new file mode 100644 index 0000000..4584d12 --- /dev/null +++ b/tools/xilinx-zcu/pinout_zcu.xdc @@ -0,0 +1,73 @@ +## 300MHz Clock from USER_SI570 +set_property PACKAGE_PIN AL7 [get_ports "p_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 +set_property IOSTANDARD DIFF_SSTL12 [get_ports "p_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 +set_property PACKAGE_PIN AL8 [get_ports "p_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 +set_property IOSTANDARD DIFF_SSTL12 [get_ports "p_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 + +## Buttons SW_C +# set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports p_reset] + +set_property PACKAGE_PIN AG13 [get_ports "p_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 +## LEDs +set_property PACKAGE_PIN AG14 [get_ports "p_leds_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 +set_property PACKAGE_PIN AF13 [get_ports "p_leds_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 +set_property PACKAGE_PIN AE13 [get_ports "p_leds_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 +set_property PACKAGE_PIN AJ14 [get_ports "p_leds_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 +set_property PACKAGE_PIN AJ15 [get_ports "p_leds_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 +set_property PACKAGE_PIN AH13 [get_ports "p_leds_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 + +# set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[0]}] +# set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[1]}] +# set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[2]}] + +# set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[0]}] +# set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[1]}] +# set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[2]}] + + +## Pmod Header J55 +set_property PACKAGE_PIN A20 [get_ports "p_dc0_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property PACKAGE_PIN B20 [get_ports "p_dc0_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 +# set_property PACKAGE_PIN A22 [get_ports "p_dc0_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 +# set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 +set_property PACKAGE_PIN A21 [get_ports "p_dc0_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 +set_property PACKAGE_PIN B21 [get_ports "p_dc1_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 +set_property PACKAGE_PIN C21 [get_ports "p_dc1_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 +# set_property PACKAGE_PIN C22 [get_ports "p_dc1_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 +# set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 +set_property PACKAGE_PIN D21 [get_ports "p_dc1_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 + +## Pmod Header J87 +set_property PACKAGE_PIN D20 [get_ports "p_dc2_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc2_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 +set_property PACKAGE_PIN E20 [get_ports "p_dc2_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc2_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 +set_property PACKAGE_PIN E22 [get_ports "p_dc2_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc2_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 + +# UART +set_property PACKAGE_PIN E13 [get_ports "p_serial_rxd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +set_property IOSTANDARD LVCMOS33 [get_ports "p_serial_rxd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +set_property PACKAGE_PIN F13 [get_ports "p_serial_txd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 +set_property IOSTANDARD LVCMOS33 [get_ports "p_serial_txd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 + +# UART Debug (unsure, maybe just indicator LEDs?) +set_property PACKAGE_PIN D12 [get_ports "p_debug_out[0]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 +set_property IOSTANDARD LVCMOS33 [get_ports "p_debug_out[0]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 +set_property PACKAGE_PIN E12 [get_ports "p_debug_out[1]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 +set_property IOSTANDARD LVCMOS33 [get_ports "p_debug_out[1]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 + + diff --git a/tools/xilinx-zcu/qlaser_timing_zcu.xdc b/tools/xilinx-zcu/qlaser_timing_zcu.xdc new file mode 100644 index 0000000..348918d --- /dev/null +++ b/tools/xilinx-zcu/qlaser_timing_zcu.xdc @@ -0,0 +1,3 @@ +## 125MHz Clock from Ethernet PHY +create_clock -period 3.333 -name sys_clk_pin -waveform {0.000 1.667} -add [get_ports p_clk_p] +create_clock -period 3.333 -name sys_clk_pin -waveform {0.000 1.667} -add [get_ports p_clk_n] diff --git a/tools/xilinx-zcu/set_usercode_zcu.xdc b/tools/xilinx-zcu/set_usercode_zcu.xdc new file mode 100644 index 0000000..3288be0 --- /dev/null +++ b/tools/xilinx-zcu/set_usercode_zcu.xdc @@ -0,0 +1,29 @@ +##--------------------------------------------------------------------------------------- +## Filename : set_usercode.xdc +## +## Vivado onstraint file to set user version number into the bitfile +##--------------------------------------------------------------------------------------- + +#---------------------------------------------------------------------------------------- +#-- Usercode major revisions +#---------------------------------------------------------------------------------------- +#-- 0x0000_NNNN : Early debug and test. No PMODs,ZMODs, DACs etc +#-- 0x1AC0_NNNN : DC PMODs, 4? single bit pulses. NNN incremented each bitfile +#-- 0x1DC0_NNNN : DC PMODs DAC versions. NNN incremented each bitfile +#-- 0x2AC0_NNNN : DC PMODs, AC ZMODs. 4 channel NNN incremented each bitfile +#-- 0x3AC0_NNNN : DC PMODs, JESD AC (16ch Abaco board) NNN incremented each bitfile +# +#---------------------------------------------------------------------------------------- +#-- Usercode history +#---------------------------------------------------------------------------------------- +#-- 0x1DC0_0001 : Original release +#-- 0x1DC0_0002 : Modified double blink and added QSPI and SD into the PS1 block +#-- 0x1DC0_0003 : SD pins on 1.8V bank. Add SD_CD on MIO47 +#-- 0x1DC0_0004 : SD clock dropped from 100MHz to 20Mhz +#-- 0x1DC0_0005 : Restore internal reference enable for pmod DACs +#-- 0x3AC0_0006 : Existing working codes ported to ZCU102 +#-- +#---------------------------------------------------------------------------------------- +# In VHDL package : constant C_QLASER_VERSION : std_logic_vector(31 downto 0) +#---------------------------------------------------------------------------------------- +set_property BITSTREAM.CONFIG.USERID 32'h3AC00006 [current_design] diff --git a/tools/xilinx/build_project.tcl b/tools/xilinx/build_project.tcl new file mode 100644 index 0000000..1400ac9 --- /dev/null +++ b/tools/xilinx/build_project.tcl @@ -0,0 +1,597 @@ +#***************************************************************************************** +# Vivado (TM) v2018.2 (64-bit) +# +# build_project.tcl: Tcl script for re-creating project 'qlaser_eclypse7' +# +# Generated by Vivado on Thu Feb 16 16:07:58 -0800 2023 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (build_project.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "D:/Work/UW-Quantum/tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/ps1.bd" +# "D:/Work/UW-Quantum/tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/hdl/ps1_wrapper.vhd" +# "D:/Work/UW-Quantum/tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/ip/clkpll/clkpll.xci" +# +# 3. The following remote source files that were added to the original project:- +# +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_pkg.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/blink.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/clkreset.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_cpu2uart.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_serial_pkg_100MHz.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_uart.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_uart2cpu.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/qlaser_cpuint_serial.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_dac_dc_package.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_spi.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_dacs_dc.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_dacs_pulse.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_version_pkg.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_misc.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_top.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/tools/xilinx/pinout.xdc" +# "D:/Work/UW-Quantum/github/NANO_QLASER/tools/xilinx/set_usercode.xdc" +# "D:/Work/UW-Quantum/github/NANO_QLASER/tools/xilinx/qlaser_timing.xdc" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "qlaser_eclypse7" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "build_project.tcl" + +# Help information for this script +proc help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/../../../../tools/Vivado2018_2/qlaser_eclypse7"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg484-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Reconstruct message rules +# None + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "digilentinc.com:eclypse-z7:part0:1.1" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.board_id" -value "eclypse-z7" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.uses_pr" -value "1" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "target_language" -value "VHDL" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "6" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "6" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "6" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "6" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "6" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "6" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "6" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../../../Common/IP_GJED"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_pkg.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/blink.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/clkreset.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_cpu2uart.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_serial_pkg_100MHz.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_uart.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_uart2cpu.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/qlaser_cpuint_serial.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_dac_dc_package.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_spi.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_dacs_dc.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_dacs_pulse.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_version_pkg.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_misc.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_top.vhd"] \ +] +add_files -norecurse -fileset $obj $files + +# Add local files from the original project (-no_copy_sources specified) +set files [list \ + [file normalize "${origin_dir}/../../../../tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/ps1.bd" ]\ + [file normalize "${origin_dir}/../../../../tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/hdl/ps1_wrapper.vhd" ]\ +] +set added_files [add_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../../src/hdl/fpga/qlaser_pkg.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/blink.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/clkreset.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/nc3_cpu2uart.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/nc3_serial_pkg_100MHz.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/nc3_uart.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/nc3_uart2cpu.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/qlaser_cpuint_serial.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_dac_dc_package.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_spi.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_dacs_dc.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_dacs_pulse.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_version_pkg.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_misc.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_top.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + + +# Set 'sources_1' fileset file properties for local files +set file "ps1/ps1.bd" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "registered_with_manager" -value "1" -objects $file_obj + +set file "hdl/ps1_wrapper.vhd" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "qlaser_top" -objects $obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Add local files from the original project (-no_copy_sources specified) +set files [list \ + [file normalize "${origin_dir}/../../../../tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/ip/clkpll/clkpll.xci" ]\ +] +set added_files [add_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "clkpll/clkpll.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/pinout.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/pinout.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/set_usercode.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/set_usercode.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/qlaser_timing.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/qlaser_timing.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "sim_mode" -value "post-implementation" -objects $obj +set_property -name "top" -value "qlaser_top" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2018" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2018" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { + +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" diff --git a/tools/xilinx/build_ps1.tcl b/tools/xilinx/build_ps1.tcl new file mode 100644 index 0000000..3a526ba --- /dev/null +++ b/tools/xilinx/build_ps1.tcl @@ -0,0 +1,890 @@ + +################################################################ +# This is a generated script based on design: ps1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2018.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source ps1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z020clg484-1 + set_property BOARD_PART digilentinc.com:eclypse-z7:part0:1.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name ps1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_bram_ctrl:4.*\ +xilinx.com:ip:blk_mem_gen:8.*\ +xilinx.com:ip:smartconnect:1.*\ +xilinx.com:ip:processing_system7:5.*\ +xilinx.com:ip:proc_sys_reset:5.*\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + # Create ports + set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] + set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] + set ext_reset_n [ create_bd_port -dir I -type rst ext_reset_n ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $ext_reset_n + + # Create instance: axi_bram_ctrl, and set properties + set axi_bram_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.* axi_bram_ctrl ] + + # Create instance: axi_bram_ctrl_bram, and set properties + set axi_bram_ctrl_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.* axi_bram_ctrl_bram ] + set_property -dict [ list \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + ] $axi_bram_ctrl_bram + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.* axi_smc ] + set_property -dict [ list \ + CONFIG.NUM_SI {1} \ + ] $axi_smc + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.* processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {20.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ + CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \ + CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ + CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ + CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \ + CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ + CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ + CONFIG.PCW_CLK0_FREQ {100000000} \ + CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK2_FREQ {10000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CORE0_FIQ_INTR {0} \ + CONFIG.PCW_CORE0_IRQ_INTR {0} \ + CONFIG.PCW_CORE1_FIQ_INTR {0} \ + CONFIG.PCW_CORE1_IRQ_INTR {0} \ + CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \ + CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ + CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ + CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ + CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DM_WIDTH {4} \ + CONFIG.PCW_DQS_WIDTH {4} \ + CONFIG.PCW_DQ_WIDTH {32} \ + CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \ + CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {0} \ + CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ + CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ + CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ + CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ + CONFIG.PCW_EN_4K_TIMER {0} \ + CONFIG.PCW_EN_CAN0 {0} \ + CONFIG.PCW_EN_CAN1 {0} \ + CONFIG.PCW_EN_CLK0_PORT {1} \ + CONFIG.PCW_EN_CLK1_PORT {0} \ + CONFIG.PCW_EN_CLK2_PORT {0} \ + CONFIG.PCW_EN_CLK3_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ + CONFIG.PCW_EN_DDR {1} \ + CONFIG.PCW_EN_EMIO_CAN0 {0} \ + CONFIG.PCW_EN_EMIO_CAN1 {0} \ + CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_ENET0 {0} \ + CONFIG.PCW_EN_EMIO_ENET1 {0} \ + CONFIG.PCW_EN_EMIO_GPIO {0} \ + CONFIG.PCW_EN_EMIO_I2C0 {0} \ + CONFIG.PCW_EN_EMIO_I2C1 {0} \ + CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ + CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ + CONFIG.PCW_EN_EMIO_PJTAG {0} \ + CONFIG.PCW_EN_EMIO_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_SPI0 {0} \ + CONFIG.PCW_EN_EMIO_SPI1 {0} \ + CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ + CONFIG.PCW_EN_EMIO_TRACE {0} \ + CONFIG.PCW_EN_EMIO_TTC0 {0} \ + CONFIG.PCW_EN_EMIO_TTC1 {0} \ + CONFIG.PCW_EN_EMIO_UART0 {0} \ + CONFIG.PCW_EN_EMIO_UART1 {0} \ + CONFIG.PCW_EN_EMIO_WDT {0} \ + CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ + CONFIG.PCW_EN_ENET0 {0} \ + CONFIG.PCW_EN_ENET1 {0} \ + CONFIG.PCW_EN_GPIO {0} \ + CONFIG.PCW_EN_I2C0 {0} \ + CONFIG.PCW_EN_I2C1 {0} \ + CONFIG.PCW_EN_MODEM_UART0 {0} \ + CONFIG.PCW_EN_MODEM_UART1 {0} \ + CONFIG.PCW_EN_PJTAG {0} \ + CONFIG.PCW_EN_PTP_ENET0 {0} \ + CONFIG.PCW_EN_PTP_ENET1 {0} \ + CONFIG.PCW_EN_QSPI {1} \ + CONFIG.PCW_EN_RST0_PORT {1} \ + CONFIG.PCW_EN_RST1_PORT {0} \ + CONFIG.PCW_EN_RST2_PORT {0} \ + CONFIG.PCW_EN_RST3_PORT {0} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SDIO1 {0} \ + CONFIG.PCW_EN_SMC {0} \ + CONFIG.PCW_EN_SPI0 {0} \ + CONFIG.PCW_EN_SPI1 {0} \ + CONFIG.PCW_EN_TRACE {0} \ + CONFIG.PCW_EN_TTC0 {0} \ + CONFIG.PCW_EN_TTC1 {0} \ + CONFIG.PCW_EN_UART0 {1} \ + CONFIG.PCW_EN_UART1 {0} \ + CONFIG.PCW_EN_USB0 {0} \ + CONFIG.PCW_EN_USB1 {0} \ + CONFIG.PCW_EN_WDT {0} \ + CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {4} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {3} \ + CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \ + CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \ + CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ + CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {1} \ + CONFIG.PCW_GP0_NUM_READ_THREADS {4} \ + CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \ + CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {1} \ + CONFIG.PCW_GP1_NUM_READ_THREADS {4} \ + CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \ + CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {