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modified the wave ram

This commit is contained in:
Eric Yu 2023-12-21 15:49:54 -08:00
parent bad218fbf3
commit b282a13882
8 changed files with 6474 additions and 6493 deletions
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1458
src/hdl/ip_gen/bram_pulse_definition_sim_netlist.vhdl
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6654
src/hdl/ip_gen/bram_pulseposition_sim_netlist.vhdl
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2246
src/hdl/ip_gen/bram_waveform_sim_netlist.vhdl
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2580
src/hdl/ip_gen/fifo_data_to_stream_sim_netlist.vhdl
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2
src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
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@ -135,7 +135,6 @@ begin
port map (
-- Port A CPU Bus
clka => clk , -- input std_logic
ena => ram_waveform_ena , -- input std_logic
wea => ram_waveform_wea , -- input slv(0 downto 0)
addra => ram_waveform_addra , -- input slv(10 downto 0)
dina => ram_waveform_dina , -- input slv(31 downto 0)
@ -143,7 +142,6 @@ begin
-- Port B waveform output
clkb => clk , -- input std_logic
enb => ram_waveform_enb , -- input std_logic
web => (others=>'0') , -- input slv(0 downto 0)
addrb => ram_waveform_addrb , -- input slv(11 downto 0)
dinb => (others=>'0') , -- input slv(15 downto 0)

12
src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl
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@ -100,7 +100,7 @@ end;
-------------------------------------------------------------
-- CPU write pulse definition RAM
-- Use 96 bit data to make three 32-bit writes
-- Make fore 32-bit data write
-------------------------------------------------------------
procedure cpu_write_pulsedef(
signal clk : in std_logic;
@ -193,7 +193,7 @@ end;
-------------------------------------------------------------
-- CPU read pulse definition RAM
-- Use 96 bit data to make three 32-bit writes
-- make four 32-bit reads
-------------------------------------------------------------
procedure cpu_read_pulsedef(
signal clk : in std_logic;
@ -238,10 +238,10 @@ begin
--etc, etc.
-- 4 writes. (Address is an integer)
cpu_write(clk, ADR_RAM_PULSE+num_entry , x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
cpu_write(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
cpu_write(clk, ADR_RAM_PULSE+(num_entry+2) , slv_timefactor & slv_gainfactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
cpu_write(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
-- cpu_read(clk, ADR_RAM_PULSE+num_entry, x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
-- cpu_read(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
-- cpu_read(clk, ADR_RAM_PULSE+(num_entry+2) , slv_timefactor & slv_gainfactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
-- cpu_read(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
end;

2
tools/build_src/build.tcl
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@ -3,7 +3,7 @@ create_project zcu_pulse_channel ../../prj -force
set_property board_part xilinx.com:zcu102:part0:3.4 [current_project]
add_files {..\..\src\hdl\modules\qlaser_dacs_pulse_channel.vhdl}
add_files -fileset sim_1 {..\..\src\hdl\tb\tb_cpubus_dacs_pulse_channel_pd.vhdl}
add_files -fileset sim_1 {..\..\src\hdl\tb\tb_cpubus_dacs_pulse_channel.vhdl}
add_files {..\..\src\hdl\pkg\qlaser_dac_dc_pkg.vhd}
add_files {..\..\src\hdl\pkg\qlaser_pkg.vhd}
add_files {..\..\src\hdl\pkg\iopakp.vhd}

13
tools/xilinx-zcu/bram_waveform/bram_waveform.xci
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@ -117,8 +117,8 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 6.91608 mW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">zynquplus</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
@ -186,8 +186,8 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
@ -297,6 +297,7 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
@ -316,13 +317,11 @@
&quot;boundary&quot;: {
&quot;ports&quot;: {
&quot;clka&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
&quot;ena&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
&quot;wea&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;0&quot;, &quot;size_right&quot;: &quot;0&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
&quot;addra&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;10&quot;, &quot;size_right&quot;: &quot;0&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
&quot;dina&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;31&quot;, &quot;size_right&quot;: &quot;0&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
&quot;douta&quot;: [ { &quot;direction&quot;: &quot;out&quot;, &quot;size_left&quot;: &quot;31&quot;, &quot;size_right&quot;: &quot;0&quot; } ],
&quot;clkb&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
&quot;enb&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
&quot;web&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;0&quot;, &quot;size_right&quot;: &quot;0&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
&quot;addrb&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;11&quot;, &quot;size_right&quot;: &quot;0&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
&quot;dinb&quot;: [ { &quot;direction&quot;: &quot;in&quot;, &quot;size_left&quot;: &quot;15&quot;, &quot;size_right&quot;: &quot;0&quot;, &quot;driver_value&quot;: &quot;0&quot; } ],
@ -370,7 +369,6 @@
&quot;CLK&quot;: [ { &quot;physical_name&quot;: &quot;clka&quot; } ],
&quot;DIN&quot;: [ { &quot;physical_name&quot;: &quot;dina&quot; } ],
&quot;DOUT&quot;: [ { &quot;physical_name&quot;: &quot;douta&quot; } ],
&quot;EN&quot;: [ { &quot;physical_name&quot;: &quot;ena&quot; } ],
&quot;WE&quot;: [ { &quot;physical_name&quot;: &quot;wea&quot; } ]
}
},
@ -391,7 +389,6 @@
&quot;CLK&quot;: [ { &quot;physical_name&quot;: &quot;clkb&quot; } ],
&quot;DIN&quot;: [ { &quot;physical_name&quot;: &quot;dinb&quot; } ],
&quot;DOUT&quot;: [ { &quot;physical_name&quot;: &quot;doutb&quot; } ],
&quot;EN&quot;: [ { &quot;physical_name&quot;: &quot;enb&quot; } ],
&quot;WE&quot;: [ { &quot;physical_name&quot;: &quot;web&quot; } ]
}
}