From a7bd4bd27604623852490911f2bb1b14a931a285 Mon Sep 17 00:00:00 2001 From: Eric Yu Date: Mon, 4 Dec 2023 18:00:55 -0800 Subject: [PATCH] added other files --- .gitignore | 7 +- tools/build_src/build.tcl | 17 + tools/xilinx-zcu/bram_pulseposition.xci | 119 +++ tools/xilinx-zcu/bram_waveform.xci | 422 ++++++++ tools/xilinx-zcu/clkpll_zcu.xci | 769 ++++++++++++++ tools/xilinx-zcu/fifo_data_to_stream.xci | 635 ++++++++++++ tools/xilinx-zcu/pinout_zcu.xdc | 73 ++ tools/xilinx-zcu/qlaser_timing_zcu.xdc | 3 + tools/xilinx-zcu/set_usercode_zcu.xdc | 29 + tools/xilinx-zcu/vscode_proj.yaml | 73 ++ tools/xilinx/build_project.tcl | 597 +++++++++++ tools/xilinx/build_ps1.tcl | 890 ++++++++++++++++ tools/xilinx/clkpll.xci | 793 +++++++++++++++ tools/xilinx/pinout.xdc | 119 +++ tools/xilinx/ps1.bd | 838 ++++++++++++++++ tools/xilinx/qlaser_timing.xdc | 3 + tools/xilinx/set_usercode.xdc | 28 + tools/xilinx/zcu102_Rev1.0_U1_09152016.xdc | 1059 ++++++++++++++++++++ 18 files changed, 6472 insertions(+), 2 deletions(-) create mode 100644 tools/build_src/build.tcl create mode 100644 tools/xilinx-zcu/bram_pulseposition.xci create mode 100644 tools/xilinx-zcu/bram_waveform.xci create mode 100644 tools/xilinx-zcu/clkpll_zcu.xci create mode 100644 tools/xilinx-zcu/fifo_data_to_stream.xci create mode 100644 tools/xilinx-zcu/pinout_zcu.xdc create mode 100644 tools/xilinx-zcu/qlaser_timing_zcu.xdc create mode 100644 tools/xilinx-zcu/set_usercode_zcu.xdc create mode 100644 tools/xilinx-zcu/vscode_proj.yaml create mode 100644 tools/xilinx/build_project.tcl create mode 100644 tools/xilinx/build_ps1.tcl create mode 100644 tools/xilinx/clkpll.xci create mode 100644 tools/xilinx/pinout.xdc create mode 100644 tools/xilinx/ps1.bd create mode 100644 tools/xilinx/qlaser_timing.xdc create mode 100644 tools/xilinx/set_usercode.xdc create mode 100644 tools/xilinx/zcu102_Rev1.0_U1_09152016.xdc diff --git a/.gitignore b/.gitignore index 9ae1e83..d3aeb69 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,8 @@ - +*.log +*.jou *.ini *.wlf work -transcript \ No newline at end of file +transcript +prj +.Xil \ No newline at end of file diff --git a/tools/build_src/build.tcl b/tools/build_src/build.tcl new file mode 100644 index 0000000..c42a161 --- /dev/null +++ b/tools/build_src/build.tcl @@ -0,0 +1,17 @@ +create_project zcu_pulse_channel ../../prj -force + +set_property board_part xilinx.com:zcu102:part0:3.4 [current_project] + +add_files {..\..\src\hdl\modules\qlaser_dacs_pulse_channel.vhdl} +add_files -fileset sim_1 {..\..\src\hdl\tb\tb_cpubus_dacs_pulse_channel_pd.vhdl} +add_files {..\..\src\hdl\pkg\qlaser_dac_dc_pkg.vhd} +add_files {..\..\src\hdl\pkg\qlaser_pkg.vhd} +add_files {..\..\src\hdl\pkg\iopakp.vhd} +add_files {..\..\src\hdl\pkg\iopakb.vhd} +import_ip {..\xilinx-zcu\bram_pulseposition.xci} +import_ip {..\xilinx-zcu\bram_waveform.xci} +import_ip {..\xilinx-zcu\fifo_data_to_stream.xci} + +upgrade_ip [get_ips -filter {SCOPE !~ "*.bd"}] +generate_target all [get_ips -filter {SCOPE !~ "*.bd"}] +exit diff --git a/tools/xilinx-zcu/bram_pulseposition.xci b/tools/xilinx-zcu/bram_pulseposition.xci new file mode 100644 index 0000000..f545456 --- /dev/null +++ b/tools/xilinx-zcu/bram_pulseposition.xci @@ -0,0 +1,119 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bram_pulseposition + + + 4 + 0 + 16 + ./ + zynquplus + 1 + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + no_coe_file_loaded + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 24 + bram_pulseposition + 0 + ce_overrides_sync_controls + no_coe_file_loaded + false + false + 24 + 0 + 16 + 16 + non_registered + false + false + non_registered + dual_port_ram + non_registered + false + false + false + false + non_registered + false + false + false + false + false + zynquplus + xilinx.com:zcu102:part0:3.4 + + xczu9eg + ffvb1156 + VHDL + + VHDL + -2 + + E + TRUE + TRUE + IP_Flow + 13 + TRUE + ../../../../blink_clk.gen/sources_1/ip/bram_pulseposition + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + diff --git a/tools/xilinx-zcu/bram_waveform.xci b/tools/xilinx-zcu/bram_waveform.xci new file mode 100644 index 0000000..1f3b7a4 --- /dev/null +++ b/tools/xilinx-zcu/bram_waveform.xci @@ -0,0 +1,422 @@ + + + xilinx.com + xci + unknown + 1.0 + + + bram_waveform + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + + 100000000 + 0 + 0 + 0.0 + 0 + 9 + 10 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 1 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 3.643151 mW + zynquplus + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + bram_waveform.mem + no_coe_file_loaded + 0 + 0 + 2 + 0 + 1 + 512 + 1024 + 1 + 1 + 32 + 16 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 512 + 1024 + WRITE_FIRST + WRITE_FIRST + 32 + 16 + zynquplus + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + bram_waveform + false + false + false + false + false + false + false + false + false + Use_ENA_Pin + Use_ENB_Pin + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + True_Dual_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 100 + 100 + 50 + 8kx2 + false + false + 1 + 1 + 32 + 16 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 512 + 32 + 16 + No_ECC + false + false + false + Stand_Alone + zynquplus + xilinx.com:zcu102:part0:3.4 + + xczu9eg + ffvb1156 + VHDL + + VHDL + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + ../../../../blink_clk.gen/sources_1/ip/bram_waveform + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/xilinx-zcu/clkpll_zcu.xci b/tools/xilinx-zcu/clkpll_zcu.xci new file mode 100644 index 0000000..66e821d --- /dev/null +++ b/tools/xilinx-zcu/clkpll_zcu.xci @@ -0,0 +1,769 @@ + + + xilinx.com + xci + unknown + 1.0 + + + clkpll_zcu + + + false + 100000000 + false + 100000000 + false + 100000000 + false + 100000000 + + + + + 100000000 + 0 + 0 + 0.0 + 1 + LEVEL_HIGH + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 0 + MMCM + cddcdone + cddcreq + 0000 + 0000 + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 33.330000000000005 + 100.0 + 0000 + 0000 + 100.00000 + 0000 + 0000 + 100.000 + BUFG + 50.0 + false + 100.00000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + 0000 + 0000 + 100.000 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + BUFG + 50.000 + false + 100.000 + 0.000 + 50.000 + 100.000 + 0.000 + 1 + 0 + VCO + clk_in_sel + clk_out1 + clk_out2 + clk_out3 + clk_out4 + clk_out5 + clk_out6 + clk_out7 + CLK_VALID + NA + daddr + dclk + den + din + 0000 + 1 + 0.08333333333333333 + 0.08333333333333333 + 0.08333333333333333 + 0.08333333333333333 + 0.08333333333333333 + 0.08333333333333333 + dout + drdy + dwe + 93.000 + 1.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + FDBK_AUTO + 0000 + 0000 + 0 + Input Clock Freq (MHz) Input Jitter (UI) + __primary_________300.000____________0.010 + no_secondary_input_clock + input_clk_stopped + 0 + Units_MHz + No_Jitter + locked + 0000 + 0000 + 0000 + false + false + false + false + false + false + false + false + OPTIMIZED + 4.000 + 0.000 + FALSE + 3.333 + 10.0 + 12.000 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + 1 + 0.500 + 0.000 + FALSE + FALSE + AUTO + 1 + None + 0.010 + 0.010 + FALSE + 128.000 + 2.000 + 1 + 0 + Output Output Phase Duty Cycle Pk-to-Pk Phase + Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) + clk_out1__100.00000______0.000______50.0______101.475_____77.836 + no_CLK_OUT2_output + no_CLK_OUT3_output + no_CLK_OUT4_output + no_CLK_OUT5_output + no_CLK_OUT6_output + no_CLK_OUT7_output + 0 + 0 + 128.000 + 1.000 + LATENCY + UNKNOWN + false + false + false + false + false + OPTIMIZED + 1 + 0.000 + 1.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + No notes + 0.010 + power_down + 0000 + 1 + clk_in1 + MMCM + AUTO + 300.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + 0 + reset + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 4000 + 0.004 + STATUS + 11 + 32 + 100.0 + 100.0 + 100.0 + 100.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1600.000 + 800.000 + clkpll_zcu + MMCM + false + empty + cddcdone + cddcreq + clkfb_in_n + clkfb_in + clkfb_in_p + SINGLE + clkfb_out_n + clkfb_out + clkfb_out_p + clkfb_stopped + 33.330000000000005 + 0.010 + 100.0 + 0.010 + Buffer + 101.475 + false + 77.836 + 50.000 + 100.000 + 0.000 + 1 + true + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + Buffer + 0.0 + false + 0.0 + 50.000 + 100.000 + 0.000 + 1 + false + 600.000 + user_si570_sysclk + Custom + clk_in_sel + clk_out1 + false + clk_out2 + false + clk_out3 + false + clk_out4 + false + clk_out5 + false + clk_out6 + false + clk_out7 + false + CLK_VALID + auto + clkpll_zcu + daddr + dclk + den + Custom + Custom + din + dout + drdy + dwe + false + false + false + false + false + false + false + false + false + FDBK_AUTO + input_clk_stopped + frequency + Enable_AXI + Units_MHz + Units_UI + UI + No_Jitter + locked + OPTIMIZED + 4.000 + 0.000 + false + 3.333 + 10.0 + 12.000 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + 1 + 0.500 + 0.000 + false + false + AUTO + 1 + None + 0.010 + 0.010 + false + 1 + false + false + false + LATENCY + false + UNKNOWN + OPTIMIZED + 4 + 0.000 + 10.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + 1 + 0.500 + 0.000 + CLKFBOUT + SYSTEM_SYNCHRONOUS + 1 + None + 0.010 + power_down + 1 + clk_in1 + MMCM + mmcm_adv + 300.000 + 0.010 + 10.000 + Differential_clock_capable_pin + psclk + psdone + psen + psincdec + 100.0 + REL_PRIMARY + reset + reset + ACTIVE_HIGH + 100.000 + 0.010 + 10.000 + clk_in2 + Single_ended_clock_capable_pin + CENTER_HIGH + 250 + 0.004 + STATUS + empty + 100.0 + 100.0 + 100.0 + 100.0 + false + false + false + false + false + false + false + true + false + false + true + false + false + false + false + false + true + false + false + false + zynquplus + xilinx.com:zcu102:part0:3.4 + + xczu9eg + ffvb1156 + VHDL + + VHDL + -2 + + E + TRUE + TRUE + IP_Flow + 10 + TRUE + ../../../../nanoq_zcu.gen/sources_1/ip/clkpll_zcu + + . + 2022.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/xilinx-zcu/fifo_data_to_stream.xci b/tools/xilinx-zcu/fifo_data_to_stream.xci new file mode 100644 index 0000000..d25885a --- /dev/null +++ b/tools/xilinx-zcu/fifo_data_to_stream.xci @@ -0,0 +1,635 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_data_to_stream + + + + + + + 100000000 + 0 + 0 + 0.0 + + + + 100000000 + 0 + 0 + 0.0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + + 100000000 + 0 + 0 + 0.0 + + + 100000000 + 0 + 0 + 0.0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.0 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.0 + 0 + 0 + 0 + 0 + + + + + 100000000 + 0 + 0 + 0.0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 1 + 0 + 9 + BlankString + 32 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 16 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + zynquplus + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 6 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 4 + BlankString + 1 + 0 + 0 + 0 + 2 + 1 + 512x36 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 510 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 509 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 9 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 9 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_data_to_stream + 64 + false + 9 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + false + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Builtin_FIFO + 0 + 510 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 509 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 32 + 512 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 16 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Synchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + true + false + false + false + Active_High + 0 + false + Active_High + 1 + false + 9 + true + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + zynquplus + xilinx.com:zcu102:part0:3.4 + + xczu9eg + ffvb1156 + VERILOG + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 7 + TRUE + ../../../../pulse_channel_zcu.gen/sources_1/ip/fifo_data_to_stream + + . + 2022.1.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/xilinx-zcu/pinout_zcu.xdc b/tools/xilinx-zcu/pinout_zcu.xdc new file mode 100644 index 0000000..4584d12 --- /dev/null +++ b/tools/xilinx-zcu/pinout_zcu.xdc @@ -0,0 +1,73 @@ +## 300MHz Clock from USER_SI570 +set_property PACKAGE_PIN AL7 [get_ports "p_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 +set_property IOSTANDARD DIFF_SSTL12 [get_ports "p_clk_n"] ;# Bank 64 VCCO - VCC1V2 - IO_L12N_T1U_N11_GC_64 +set_property PACKAGE_PIN AL8 [get_ports "p_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 +set_property IOSTANDARD DIFF_SSTL12 [get_ports "p_clk_p"] ;# Bank 64 VCCO - VCC1V2 - IO_L12P_T1U_N10_GC_64 + +## Buttons SW_C +# set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS33} [get_ports p_reset] + +set_property PACKAGE_PIN AG13 [get_ports "p_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_reset"] ;# Bank 44 VCCO - VCC3V3 - IO_L10N_AD2N_44 +## LEDs +set_property PACKAGE_PIN AG14 [get_ports "p_leds_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_0"] ;# Bank 44 VCCO - VCC3V3 - IO_L10P_AD2P_44 +set_property PACKAGE_PIN AF13 [get_ports "p_leds_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_1"] ;# Bank 44 VCCO - VCC3V3 - IO_L9N_AD3N_44 +set_property PACKAGE_PIN AE13 [get_ports "p_leds_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_2"] ;# Bank 44 VCCO - VCC3V3 - IO_L9P_AD3P_44 +set_property PACKAGE_PIN AJ14 [get_ports "p_leds_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_3"] ;# Bank 44 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_44 +set_property PACKAGE_PIN AJ15 [get_ports "p_leds_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_4"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 +set_property PACKAGE_PIN AH13 [get_ports "p_leds_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_44 +set_property IOSTANDARD LVCMOS33 [get_ports "p_leds_5"] ;# Bank 44 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_44 + +# set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[0]}] +# set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[1]}] +# set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports {p_leds0_rgb[2]}] + +# set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[0]}] +# set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[1]}] +# set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports {p_leds1_rgb[2]}] + + +## Pmod Header J55 +set_property PACKAGE_PIN A20 [get_ports "p_dc0_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property PACKAGE_PIN B20 [get_ports "p_dc0_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 +# set_property PACKAGE_PIN A22 [get_ports "p_dc0_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 +# set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 +set_property PACKAGE_PIN A21 [get_ports "p_dc0_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc0_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 +set_property PACKAGE_PIN B21 [get_ports "p_dc1_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 +set_property PACKAGE_PIN C21 [get_ports "p_dc1_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 +# set_property PACKAGE_PIN C22 [get_ports "p_dc1_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 +# set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_nc"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 +set_property PACKAGE_PIN D21 [get_ports "p_dc1_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc1_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 + +## Pmod Header J87 +set_property PACKAGE_PIN D20 [get_ports "p_dc2_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc2_cs_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 +set_property PACKAGE_PIN E20 [get_ports "p_dc2_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc2_mosi"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 +set_property PACKAGE_PIN E22 [get_ports "p_dc2_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "p_dc2_sclk"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 + +# UART +set_property PACKAGE_PIN E13 [get_ports "p_serial_rxd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +set_property IOSTANDARD LVCMOS33 [get_ports "p_serial_rxd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +set_property PACKAGE_PIN F13 [get_ports "p_serial_txd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 +set_property IOSTANDARD LVCMOS33 [get_ports "p_serial_txd"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 + +# UART Debug (unsure, maybe just indicator LEDs?) +set_property PACKAGE_PIN D12 [get_ports "p_debug_out[0]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 +set_property IOSTANDARD LVCMOS33 [get_ports "p_debug_out[0]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 +set_property PACKAGE_PIN E12 [get_ports "p_debug_out[1]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 +set_property IOSTANDARD LVCMOS33 [get_ports "p_debug_out[1]"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 + + diff --git a/tools/xilinx-zcu/qlaser_timing_zcu.xdc b/tools/xilinx-zcu/qlaser_timing_zcu.xdc new file mode 100644 index 0000000..348918d --- /dev/null +++ b/tools/xilinx-zcu/qlaser_timing_zcu.xdc @@ -0,0 +1,3 @@ +## 125MHz Clock from Ethernet PHY +create_clock -period 3.333 -name sys_clk_pin -waveform {0.000 1.667} -add [get_ports p_clk_p] +create_clock -period 3.333 -name sys_clk_pin -waveform {0.000 1.667} -add [get_ports p_clk_n] diff --git a/tools/xilinx-zcu/set_usercode_zcu.xdc b/tools/xilinx-zcu/set_usercode_zcu.xdc new file mode 100644 index 0000000..3288be0 --- /dev/null +++ b/tools/xilinx-zcu/set_usercode_zcu.xdc @@ -0,0 +1,29 @@ +##--------------------------------------------------------------------------------------- +## Filename : set_usercode.xdc +## +## Vivado onstraint file to set user version number into the bitfile +##--------------------------------------------------------------------------------------- + +#---------------------------------------------------------------------------------------- +#-- Usercode major revisions +#---------------------------------------------------------------------------------------- +#-- 0x0000_NNNN : Early debug and test. No PMODs,ZMODs, DACs etc +#-- 0x1AC0_NNNN : DC PMODs, 4? single bit pulses. NNN incremented each bitfile +#-- 0x1DC0_NNNN : DC PMODs DAC versions. NNN incremented each bitfile +#-- 0x2AC0_NNNN : DC PMODs, AC ZMODs. 4 channel NNN incremented each bitfile +#-- 0x3AC0_NNNN : DC PMODs, JESD AC (16ch Abaco board) NNN incremented each bitfile +# +#---------------------------------------------------------------------------------------- +#-- Usercode history +#---------------------------------------------------------------------------------------- +#-- 0x1DC0_0001 : Original release +#-- 0x1DC0_0002 : Modified double blink and added QSPI and SD into the PS1 block +#-- 0x1DC0_0003 : SD pins on 1.8V bank. Add SD_CD on MIO47 +#-- 0x1DC0_0004 : SD clock dropped from 100MHz to 20Mhz +#-- 0x1DC0_0005 : Restore internal reference enable for pmod DACs +#-- 0x3AC0_0006 : Existing working codes ported to ZCU102 +#-- +#---------------------------------------------------------------------------------------- +# In VHDL package : constant C_QLASER_VERSION : std_logic_vector(31 downto 0) +#---------------------------------------------------------------------------------------- +set_property BITSTREAM.CONFIG.USERID 32'h3AC00006 [current_design] diff --git a/tools/xilinx-zcu/vscode_proj.yaml b/tools/xilinx-zcu/vscode_proj.yaml new file mode 100644 index 0000000..f5949cb --- /dev/null +++ b/tools/xilinx-zcu/vscode_proj.yaml @@ -0,0 +1,73 @@ +files: + - name: "..\..\src\eyhc\bram_pulseposition_sim_netlist.vhdl" + file_type: "vhdlSource-2008" + is_include_file: false + include_path: "" + logical_name: "" + is_manual: true + - name: "..\..\src\eyhc\bram_waveform_sim_netlist.vhdl" + file_type: "vhdlSource-2008" + is_include_file: false + include_path: "" + logical_name: "" + is_manual: true + - name: "..\..\src\eyhc\qlaser_dacs_pulse_channel.vhd" + file_type: "vhdlSource-2008" + is_include_file: false + include_path: "" + logical_name: "" + is_manual: true + - name: "..\..\src\eyhc\qlaser_pkg.vhd" + file_type: "vhdlSource-2008" + is_include_file: false + include_path: "" + logical_name: "" + is_manual: true + - name: "bram_pulseposition.xci" + file_type: xci + is_include_file: false + include_path: "" + logical_name: "" + is_manual: true + - name: "bram_waveform.xci" + file_type: xci + is_include_file: false + include_path: "" + logical_name: "" + is_manual: true + - name: "fifo_data_to_stream.xci" + file_type: xci + is_include_file: false + include_path: "" + logical_name: "" + is_manual: true + - name: "..\..\src\eyhc\fifo_data_to_stream_sim_netlist.vhdl" + file_type: "vhdlSource-2008" + is_include_file: false + include_path: "" + logical_name: "" + is_manual: true +hooks: + pre_build: + [] + post_build: + [] + pre_run: + [] + post_run: + [] +watchers: + [] +name: nanoq_pulse_channel_single +tool_options: + ghdl: + name: ghdl + installation_path: "" + config: + installation_path: "" + waveform: vcd + analyze_options: + [] + run_options: + [] +toplevel: "..\..\src\eyhc\qlaser_dacs_pulse_channel.vhd" \ No newline at end of file diff --git a/tools/xilinx/build_project.tcl b/tools/xilinx/build_project.tcl new file mode 100644 index 0000000..1400ac9 --- /dev/null +++ b/tools/xilinx/build_project.tcl @@ -0,0 +1,597 @@ +#***************************************************************************************** +# Vivado (TM) v2018.2 (64-bit) +# +# build_project.tcl: Tcl script for re-creating project 'qlaser_eclypse7' +# +# Generated by Vivado on Thu Feb 16 16:07:58 -0800 2023 +# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 +# +# This file contains the Vivado Tcl commands for re-creating the project to the state* +# when this script was generated. In order to re-create the project, please source this +# file in the Vivado Tcl Shell. +# +# * Note that the runs in the created project will be configured the same way as the +# original project, however they will not be launched automatically. To regenerate the +# run results please launch the synthesis/implementation runs as needed. +# +#***************************************************************************************** +# NOTE: In order to use this script for source control purposes, please make sure that the +# following files are added to the source control system:- +# +# 1. This project restoration tcl script (build_project.tcl) that was generated. +# +# 2. The following source(s) files that were local or imported into the original project. +# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script) +# +# "D:/Work/UW-Quantum/tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/ps1.bd" +# "D:/Work/UW-Quantum/tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/hdl/ps1_wrapper.vhd" +# "D:/Work/UW-Quantum/tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/ip/clkpll/clkpll.xci" +# +# 3. The following remote source files that were added to the original project:- +# +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_pkg.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/blink.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/clkreset.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_cpu2uart.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_serial_pkg_100MHz.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_uart.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/nc3_uart2cpu.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/serial_io/qlaser_cpuint_serial.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_dac_dc_package.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_spi.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_dacs_dc.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_dacs_pulse.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_version_pkg.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_misc.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/src/hdl/fpga/qlaser_top.vhd" +# "D:/Work/UW-Quantum/github/NANO_QLASER/tools/xilinx/pinout.xdc" +# "D:/Work/UW-Quantum/github/NANO_QLASER/tools/xilinx/set_usercode.xdc" +# "D:/Work/UW-Quantum/github/NANO_QLASER/tools/xilinx/qlaser_timing.xdc" +# +#***************************************************************************************** + +# Set the reference directory for source file relative paths (by default the value is script directory path) +set origin_dir "." + +# Use origin directory path location variable, if specified in the tcl shell +if { [info exists ::origin_dir_loc] } { + set origin_dir $::origin_dir_loc +} + +# Set the project name +set _xil_proj_name_ "qlaser_eclypse7" + +# Use project name variable, if specified in the tcl shell +if { [info exists ::user_project_name] } { + set _xil_proj_name_ $::user_project_name +} + +variable script_file +set script_file "build_project.tcl" + +# Help information for this script +proc help {} { + variable script_file + puts "\nDescription:" + puts "Recreate a Vivado project from this script. The created project will be" + puts "functionally equivalent to the original project for which this script was" + puts "generated. The script contains commands for creating a project, filesets," + puts "runs, adding/importing sources and setting properties on various objects.\n" + puts "Syntax:" + puts "$script_file" + puts "$script_file -tclargs \[--origin_dir \]" + puts "$script_file -tclargs \[--project_name \]" + puts "$script_file -tclargs \[--help\]\n" + puts "Usage:" + puts "Name Description" + puts "-------------------------------------------------------------------------" + puts "\[--origin_dir \] Determine source file paths wrt this path. Default" + puts " origin_dir path value is \".\", otherwise, the value" + puts " that was set with the \"-paths_relative_to\" switch" + puts " when this script was generated.\n" + puts "\[--project_name \] Create project with the specified name. Default" + puts " name is the name of the project from where this" + puts " script was generated.\n" + puts "\[--help\] Print help information for this script" + puts "-------------------------------------------------------------------------\n" + exit 0 +} + +if { $::argc > 0 } { + for {set i 0} {$i < $::argc} {incr i} { + set option [string trim [lindex $::argv $i]] + switch -regexp -- $option { + "--origin_dir" { incr i; set origin_dir [lindex $::argv $i] } + "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] } + "--help" { help } + default { + if { [regexp {^-} $option] } { + puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n" + return 1 + } + } + } + } +} + +# Set the directory path for the original project from where this script was exported +set orig_proj_dir "[file normalize "$origin_dir/../../../../tools/Vivado2018_2/qlaser_eclypse7"]" + +# Create project +create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xc7z020clg484-1 + +# Set the directory path for the new project +set proj_dir [get_property directory [current_project]] + +# Reconstruct message rules +# None + +# Set project properties +set obj [current_project] +set_property -name "board_part" -value "digilentinc.com:eclypse-z7:part0:1.1" -objects $obj +set_property -name "default_lib" -value "xil_defaultlib" -objects $obj +set_property -name "dsa.accelerator_binary_content" -value "bitstream" -objects $obj +set_property -name "dsa.accelerator_binary_format" -value "xclbin2" -objects $obj +set_property -name "dsa.board_id" -value "eclypse-z7" -objects $obj +set_property -name "dsa.description" -value "Vivado generated DSA" -objects $obj +set_property -name "dsa.dr_bd_base_address" -value "0" -objects $obj +set_property -name "dsa.emu_dir" -value "emu" -objects $obj +set_property -name "dsa.flash_interface_type" -value "bpix16" -objects $obj +set_property -name "dsa.flash_offset_address" -value "0" -objects $obj +set_property -name "dsa.flash_size" -value "1024" -objects $obj +set_property -name "dsa.host_architecture" -value "x86_64" -objects $obj +set_property -name "dsa.host_interface" -value "pcie" -objects $obj +set_property -name "dsa.num_compute_units" -value "60" -objects $obj +set_property -name "dsa.platform_state" -value "pre_synth" -objects $obj +set_property -name "dsa.uses_pr" -value "1" -objects $obj +set_property -name "dsa.vendor" -value "xilinx" -objects $obj +set_property -name "dsa.version" -value "0.0" -objects $obj +set_property -name "enable_vhdl_2008" -value "1" -objects $obj +set_property -name "ip_cache_permissions" -value "read write" -objects $obj +set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj +set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj +set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj +set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj +set_property -name "simulator_language" -value "Mixed" -objects $obj +set_property -name "target_language" -value "VHDL" -objects $obj +set_property -name "webtalk.activehdl_export_sim" -value "6" -objects $obj +set_property -name "webtalk.ies_export_sim" -value "6" -objects $obj +set_property -name "webtalk.modelsim_export_sim" -value "6" -objects $obj +set_property -name "webtalk.questa_export_sim" -value "6" -objects $obj +set_property -name "webtalk.riviera_export_sim" -value "6" -objects $obj +set_property -name "webtalk.vcs_export_sim" -value "6" -objects $obj +set_property -name "webtalk.xsim_export_sim" -value "6" -objects $obj +set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj + +# Create 'sources_1' fileset (if not found) +if {[string equal [get_filesets -quiet sources_1] ""]} { + create_fileset -srcset sources_1 +} + +# Set IP repository paths +set obj [get_filesets sources_1] +set_property "ip_repo_paths" "[file normalize "$origin_dir/../../../../../Common/IP_GJED"]" $obj + +# Rebuild user ip_repo's index before adding any source files +update_ip_catalog -rebuild + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +set files [list \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_pkg.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/blink.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/clkreset.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_cpu2uart.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_serial_pkg_100MHz.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_uart.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/nc3_uart2cpu.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/serial_io/qlaser_cpuint_serial.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_dac_dc_package.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_spi.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_dacs_dc.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_dacs_pulse.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_version_pkg.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_misc.vhd"] \ + [file normalize "${origin_dir}/../../src/hdl/fpga/qlaser_top.vhd"] \ +] +add_files -norecurse -fileset $obj $files + +# Add local files from the original project (-no_copy_sources specified) +set files [list \ + [file normalize "${origin_dir}/../../../../tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/ps1.bd" ]\ + [file normalize "${origin_dir}/../../../../tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/bd/ps1/hdl/ps1_wrapper.vhd" ]\ +] +set added_files [add_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +set file "$origin_dir/../../src/hdl/fpga/qlaser_pkg.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/blink.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/clkreset.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/nc3_cpu2uart.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/nc3_serial_pkg_100MHz.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/nc3_uart.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/nc3_uart2cpu.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/serial_io/qlaser_cpuint_serial.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_dac_dc_package.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_spi.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_dacs_dc.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_dacs_pulse.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_version_pkg.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_misc.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + +set file "$origin_dir/../../src/hdl/fpga/qlaser_top.vhd" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + + +# Set 'sources_1' fileset file properties for local files +set file "ps1/ps1.bd" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "registered_with_manager" -value "1" -objects $file_obj + +set file "hdl/ps1_wrapper.vhd" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "file_type" -value "VHDL" -objects $file_obj + + +# Set 'sources_1' fileset properties +set obj [get_filesets sources_1] +set_property -name "top" -value "qlaser_top" -objects $obj + +# Set 'sources_1' fileset object +set obj [get_filesets sources_1] +# Add local files from the original project (-no_copy_sources specified) +set files [list \ + [file normalize "${origin_dir}/../../../../tools/Vivado2018_2/qlaser_eclypse7/qlaser_eclypse7.srcs/sources_1/ip/clkpll/clkpll.xci" ]\ +] +set added_files [add_files -fileset sources_1 $files] + +# Set 'sources_1' fileset file properties for remote files +# None + +# Set 'sources_1' fileset file properties for local files +set file "clkpll/clkpll.xci" +set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]] +set_property -name "generate_files_for_reference" -value "0" -objects $file_obj +set_property -name "registered_with_manager" -value "1" -objects $file_obj +if { ![get_property "is_locked" $file_obj] } { + set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj +} + + +# Create 'constrs_1' fileset (if not found) +if {[string equal [get_filesets -quiet constrs_1] ""]} { + create_fileset -constrset constrs_1 +} + +# Set 'constrs_1' fileset object +set obj [get_filesets constrs_1] + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/pinout.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/pinout.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/set_usercode.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/set_usercode.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Add/Import constrs file and set constrs file properties +set file "[file normalize "$origin_dir/qlaser_timing.xdc"]" +set file_added [add_files -norecurse -fileset $obj [list $file]] +set file "$origin_dir/qlaser_timing.xdc" +set file [file normalize $file] +set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]] +set_property -name "file_type" -value "XDC" -objects $file_obj + +# Set 'constrs_1' fileset properties +set obj [get_filesets constrs_1] + +# Create 'sim_1' fileset (if not found) +if {[string equal [get_filesets -quiet sim_1] ""]} { + create_fileset -simset sim_1 +} + +# Set 'sim_1' fileset object +set obj [get_filesets sim_1] +# Empty (no sources present) + +# Set 'sim_1' fileset properties +set obj [get_filesets sim_1] +set_property -name "sim_mode" -value "post-implementation" -objects $obj +set_property -name "top" -value "qlaser_top" -objects $obj +set_property -name "top_lib" -value "xil_defaultlib" -objects $obj + +# Create 'synth_1' run (if not found) +if {[string equal [get_runs -quiet synth_1] ""]} { + create_run -name synth_1 -part xc7z020clg484-1 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1 +} else { + set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1] + set_property flow "Vivado Synthesis 2018" [get_runs synth_1] +} +set obj [get_runs synth_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Synthesis Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'synth_1_synth_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } { + create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1 +} +set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] +if { $obj != "" } { + +} +set obj [get_runs synth_1] +set_property -name "needs_refresh" -value "1" -objects $obj +set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj + +# set the current synth run +current_run -synthesis [get_runs synth_1] + +# Create 'impl_1' run (if not found) +if {[string equal [get_runs -quiet impl_1] ""]} { + create_run -name impl_1 -part xc7z020clg484-1 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1 +} else { + set_property strategy "Vivado Implementation Defaults" [get_runs impl_1] + set_property flow "Vivado Implementation 2018" [get_runs impl_1] +} +set obj [get_runs impl_1] +set_property set_report_strategy_name 1 $obj +set_property report_strategy {Vivado Implementation Default Reports} $obj +set_property set_report_strategy_name 0 $obj +# Create 'impl_1_init_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_opt_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } { + create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_io_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } { + create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } { + create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_control_sets_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } { + create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] +if { $obj != "" } { + +} +# Create 'impl_1_place_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_incremental_reuse_1' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } { + create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_place_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] +if { $obj != "" } { +set_property -name "is_enabled" -value "0" -objects $obj + +} +# Create 'impl_1_route_report_drc_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } { + create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_methodology_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } { + create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_power_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } { + create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_route_status_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } { + create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_incremental_reuse_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } { + create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_clock_utilization_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } { + create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] +if { $obj != "" } { + +} +# Create 'impl_1_route_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] +if { $obj != "" } { + +} +# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] +if { $obj != "" } { + +} +# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found) +if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } { + create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1 +} +set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] +if { $obj != "" } { + +} +set obj [get_runs impl_1] +set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj +set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj +set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj + +# set the current impl run +current_run -implementation [get_runs impl_1] + +puts "INFO: Project created:${_xil_proj_name_}" diff --git a/tools/xilinx/build_ps1.tcl b/tools/xilinx/build_ps1.tcl new file mode 100644 index 0000000..3a526ba --- /dev/null +++ b/tools/xilinx/build_ps1.tcl @@ -0,0 +1,890 @@ + +################################################################ +# This is a generated script based on design: ps1 +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2018.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source ps1_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7z020clg484-1 + set_property BOARD_PART digilentinc.com:eclypse-z7:part0:1.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name ps1 + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_bram_ctrl:4.*\ +xilinx.com:ip:blk_mem_gen:8.*\ +xilinx.com:ip:smartconnect:1.*\ +xilinx.com:ip:processing_system7:5.*\ +xilinx.com:ip:proc_sys_reset:5.*\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + + # Create ports + set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] + set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] + set ext_reset_n [ create_bd_port -dir I -type rst ext_reset_n ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_LOW} \ + ] $ext_reset_n + + # Create instance: axi_bram_ctrl, and set properties + set axi_bram_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.* axi_bram_ctrl ] + + # Create instance: axi_bram_ctrl_bram, and set properties + set axi_bram_ctrl_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.* axi_bram_ctrl_bram ] + set_property -dict [ list \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + ] $axi_bram_ctrl_bram + + # Create instance: axi_smc, and set properties + set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.* axi_smc ] + set_property -dict [ list \ + CONFIG.NUM_SI {1} \ + ] $axi_smc + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.* processing_system7_0 ] + set_property -dict [ list \ + CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \ + CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ + CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \ + CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {20.000000} \ + CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ + CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ + CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ + CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ + CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \ + CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ + CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \ + CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \ + CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ + CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \ + CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ + CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ + CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \ + CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ + CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ + CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ + CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ + CONFIG.PCW_CLK0_FREQ {100000000} \ + CONFIG.PCW_CLK1_FREQ {10000000} \ + CONFIG.PCW_CLK2_FREQ {10000000} \ + CONFIG.PCW_CLK3_FREQ {10000000} \ + CONFIG.PCW_CORE0_FIQ_INTR {0} \ + CONFIG.PCW_CORE0_IRQ_INTR {0} \ + CONFIG.PCW_CORE1_FIQ_INTR {0} \ + CONFIG.PCW_CORE1_IRQ_INTR {0} \ + CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ + CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \ + CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ + CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \ + CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \ + CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \ + CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ + CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \ + CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \ + CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ + CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ + CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ + CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ + CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ + CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ + CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \ + CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ + CONFIG.PCW_DM_WIDTH {4} \ + CONFIG.PCW_DQS_WIDTH {4} \ + CONFIG.PCW_DQ_WIDTH {32} \ + CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ + CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \ + CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ + CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET0_RESET_ENABLE {0} \ + CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ + CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ + CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ + CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ + CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ + CONFIG.PCW_ENET1_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_ENABLE {0} \ + CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ + CONFIG.PCW_EN_4K_TIMER {0} \ + CONFIG.PCW_EN_CAN0 {0} \ + CONFIG.PCW_EN_CAN1 {0} \ + CONFIG.PCW_EN_CLK0_PORT {1} \ + CONFIG.PCW_EN_CLK1_PORT {0} \ + CONFIG.PCW_EN_CLK2_PORT {0} \ + CONFIG.PCW_EN_CLK3_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ + CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ + CONFIG.PCW_EN_DDR {1} \ + CONFIG.PCW_EN_EMIO_CAN0 {0} \ + CONFIG.PCW_EN_EMIO_CAN1 {0} \ + CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_ENET0 {0} \ + CONFIG.PCW_EN_EMIO_ENET1 {0} \ + CONFIG.PCW_EN_EMIO_GPIO {0} \ + CONFIG.PCW_EN_EMIO_I2C0 {0} \ + CONFIG.PCW_EN_EMIO_I2C1 {0} \ + CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ + CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ + CONFIG.PCW_EN_EMIO_PJTAG {0} \ + CONFIG.PCW_EN_EMIO_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_SDIO1 {0} \ + CONFIG.PCW_EN_EMIO_SPI0 {0} \ + CONFIG.PCW_EN_EMIO_SPI1 {0} \ + CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ + CONFIG.PCW_EN_EMIO_TRACE {0} \ + CONFIG.PCW_EN_EMIO_TTC0 {0} \ + CONFIG.PCW_EN_EMIO_TTC1 {0} \ + CONFIG.PCW_EN_EMIO_UART0 {0} \ + CONFIG.PCW_EN_EMIO_UART1 {0} \ + CONFIG.PCW_EN_EMIO_WDT {0} \ + CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ + CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ + CONFIG.PCW_EN_ENET0 {0} \ + CONFIG.PCW_EN_ENET1 {0} \ + CONFIG.PCW_EN_GPIO {0} \ + CONFIG.PCW_EN_I2C0 {0} \ + CONFIG.PCW_EN_I2C1 {0} \ + CONFIG.PCW_EN_MODEM_UART0 {0} \ + CONFIG.PCW_EN_MODEM_UART1 {0} \ + CONFIG.PCW_EN_PJTAG {0} \ + CONFIG.PCW_EN_PTP_ENET0 {0} \ + CONFIG.PCW_EN_PTP_ENET1 {0} \ + CONFIG.PCW_EN_QSPI {1} \ + CONFIG.PCW_EN_RST0_PORT {1} \ + CONFIG.PCW_EN_RST1_PORT {0} \ + CONFIG.PCW_EN_RST2_PORT {0} \ + CONFIG.PCW_EN_RST3_PORT {0} \ + CONFIG.PCW_EN_SDIO0 {1} \ + CONFIG.PCW_EN_SDIO1 {0} \ + CONFIG.PCW_EN_SMC {0} \ + CONFIG.PCW_EN_SPI0 {0} \ + CONFIG.PCW_EN_SPI1 {0} \ + CONFIG.PCW_EN_TRACE {0} \ + CONFIG.PCW_EN_TTC0 {0} \ + CONFIG.PCW_EN_TTC1 {0} \ + CONFIG.PCW_EN_UART0 {1} \ + CONFIG.PCW_EN_UART1 {0} \ + CONFIG.PCW_EN_USB0 {0} \ + CONFIG.PCW_EN_USB1 {0} \ + CONFIG.PCW_EN_WDT {0} \ + CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {4} \ + CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {3} \ + CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ + CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ + CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ + CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \ + CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \ + CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \ + CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ + CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ + CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ + CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ + CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ + CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {1} \ + CONFIG.PCW_GP0_NUM_READ_THREADS {4} \ + CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \ + CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {1} \ + CONFIG.PCW_GP1_NUM_READ_THREADS {4} \ + CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \ + CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ + CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ + CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ + CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ + CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \ + CONFIG.PCW_GPIO_MIO_GPIO_IO {