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@ -180,6 +180,14 @@ begin
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----------------------------------------------------------------
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pr_sm : process (reset, clk)
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-- TODO: those bitwidth are not correct, we could optimize it later and find out how many bits each variable should be. But for now just make it big
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variable v_flattop : std_logic_vector(C_BITS_ADDR_TOP - 1 downto 0); -- wait times (flat_top), managed by an internal counter process sm_top_counter unter state S_WAVE_TOP
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variable v_addr_length : std_logic_vector(C_BITS_ADDR_LENGTH - 1 downto 0); -- number of points/addresses used by the pulse edge, the bit width should increase with the amount of addresses the wavetable has
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variable v_addr_start : std_logic_vector(C_BITS_ADDR_START - 1 downto 0); -- start address of the pulse edge data in the Waveform RAM, the bit width should increase with the amount of address the wavetable has.
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variable v_addr_end : std_logic_vector(C_BITS_ADDR_START - 1 downto 0); -- end address of the pulse edge data in the Waveform RAM, the bit width should align with the bit width of v_addr_start
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variable v_amplitude_factor : std_logic_vector(C_BITS_GAIN_FACTOR - 1 downto 0); -- pulse edge amplitude scale factor
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variable v_time_factor : std_logic_vector(C_BITS_TIME_FACTOR - 1 downto 0); -- pulse edge time scale factor
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variable v_cnt_time : std_logic_vector(23 downto 0); -- counter for the time, the bit width should increase with the amount of addresses the wavetable has
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variable v_ram_waveform_addrb : unsigned(95 downto 0);
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begin
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if (reset = '1') then
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@ -203,6 +211,15 @@ begin
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sm_wavedata <= (others=>'0');
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sm_wavedata_dv <= '0';
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-- Actively read pulse definition RAM and update the variables
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v_flattop := ram_pulse_doutb(C_BITS_ADDR_TOP - 1 downto 0);
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v_addr_length := ram_pulse_doutb(C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_ADDR_TOP);
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v_addr_start := ram_pulse_doutb(C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP);
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v_addr_end := std_logic_vector(unsigned(v_addr_start) + unsigned(v_addr_length) - 1);
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v_amplitude_factor := ram_pulse_doutb(C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP);
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v_time_factor := ram_pulse_doutb(C_BITS_TIME_FACTOR + C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP);
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v_cnt_time := ram_pulse_doutb(24 + C_BITS_TIME_FACTOR + C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP - 1 downto C_BITS_TIME_FACTOR + C_BITS_GAIN_FACTOR + C_BITS_ADDR_START + C_BITS_ADDR_LENGTH + C_BITS_ADDR_TOP);
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------------------------------------------------------------------------
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-- Main state machine
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------------------------------------------------------------------------
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@ -246,10 +263,10 @@ begin
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when S_WAIT =>
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-- Start to output wave and increment pulse position RAM address
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if (ram_pulse_doutb(93 downto C_BITS_TIME_FACTOR) = cnt_time) then
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if (v_cnt_time = cnt_time) then
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sm_state <= S_WAVE_UP;
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-- set the wavetable's address to the starting address defined from the pulse ram
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ram_waveform_addrb <= ram_pulse_doutb(C_BITS_GAIN_FACTOR - 1 downto C_BITS_ADDR_START);
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ram_waveform_addrb <= v_addr_start;
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elsif (cnt_time = X"FFFFFF") then
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sm_state <= S_IDLE;
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end if;
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@ -261,46 +278,51 @@ begin
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------------------------------------------------------------------------
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when S_WAVE_UP =>
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-- Check if is end of rise of the waveform, and hold the address
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if (ram_waveform_addrb = std_logic_vector(unsigned(ram_pulse_doutb(C_BITS_GAIN_FACTOR - 1 downto C_BITS_ADDR_START)) + unsigned(ram_pulse_doutb(C_BITS_ADDR_START - 1 downto C_BITS_ADDR_LENGTH)))) then
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if (ram_waveform_addrb = v_addr_end) then
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sm_state <= S_WAVE_FLAT;
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-- initialize the counter for the flat top of the waveform
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cnt_wave_top <= std_logic_vector(to_unsigned(0, C_BITS_ADDR_TOP));
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else
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-- Output waveform from RAM with rounded gain factor
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v_ram_waveform_addrb := ((unsigned(ram_waveform_addrb) + 1) * unsigned(ram_pulse_doutb(C_BITS_TIME_FACTOR - 1 downto C_BITS_GAIN_FACTOR)));
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ram_waveform_addrb <= std_logic_vector(v_ram_waveform_addrb(C_BITS_TIME_INT downto C_BITS_TIME_FRAC));
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-- Output waveform from RAM , and increment the address
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-- TODO: apply scaling factor to the address and then to the output
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ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1);
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sm_wavedata <= ram_waveform_doutb;
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sm_wavedata_dv <= '1';
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end if;
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------------------------------------------------------------------------
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-- Hold the last address and output its data
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-- decrement from this address when finished waiting
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------------------------------------------------------------------------
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when S_WAVE_FLAT =>
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if (cnt_wave_top = ram_pulse_doutb(C_BITS_ADDR_TOP - 1 downto 0)) then
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if (cnt_wave_top = v_flattop) then
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sm_state <= S_WAVE_DOWN;
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else
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cnt_wave_top <= std_logic_vector(unsigned(cnt_wave_top) + 1);
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sm_wavedata <= ram_waveform_doutb;
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sm_wavedata_dv <= '1';
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end if;
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------------------------------------------------------------------------
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-- Output the falling edge of a waveform
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-- Hold the start address when complete
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------------------------------------------------------------------------
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when S_WAVE_DOWN =>
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-- End of waveform?
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if (ram_waveform_addrb = std_logic_vector(to_unsigned(C_LENGTH_WAVEFORM-1,10))) then
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if (ram_waveform_addrb = v_addr_start) then
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-- If the end of the pulse table is reached then go to idle
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if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_NUM_PULSE-1,10))) then
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if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_NUM_PULSE-1,4))) then
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ram_pulse_addrb <= (others=>'0');
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sm_state <= S_IDLE;
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else -- Increment pulse address. Wait for next pulse start time
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else -- increment pulse address for the next waveform
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ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
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sm_state <= S_WAIT;
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end if;
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-- Output waveform from RAM with decremented address
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else
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v_ram_waveform_addrb := (unsigned(ram_waveform_addrb) - 1) * unsigned(ram_pulse_doutb(C_BITS_TIME_FACTOR - 1 downto C_BITS_GAIN_FACTOR));
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ram_waveform_addrb <= std_logic_vector(v_ram_waveform_addrb(C_BITS_TIME_INT downto C_BITS_TIME_FRAC));
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ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - 1);
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sm_wavedata <= ram_waveform_doutb;
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sm_wavedata_dv <= '1';
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end if;
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@ -1,19 +1,19 @@
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vlib work
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proc recursive_glob {dir} {
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set files [glob -nocomplain -type f -directory $dir *_sim_netlist.vhdl]
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foreach subdir [glob -nocomplain -type d -directory $dir *] {
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lappend files {*}[recursive_glob $subdir]
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}
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return $files
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}
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# proc recursive_glob {dir} {
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# set files [glob -nocomplain -type f -directory $dir *_sim_netlist.vhdl]
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# foreach subdir [glob -nocomplain -type d -directory $dir *] {
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# lappend files {*}[recursive_glob $subdir]
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# }
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# return $files
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# }
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set src_dir ../../prj/zcu_pulse_channel.gen
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set files [recursive_glob $src_dir]
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# set src_dir ../../prj/zcu_pulse_channel.gen
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# set files [recursive_glob $src_dir]
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foreach file $files {
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file copy -force $file ../../src/hdl/ip_gen
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}
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# foreach file $files {
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# file copy -force $file ../../src/hdl/ip_gen
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# }
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vcom ../../src/hdl/ip_gen/*.vhd*
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vcom ../../src/hdl/pkg/*pkg.vhd
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@ -336,12 +336,12 @@
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"parameters": {
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"ASSOCIATED_BUSIF": [ { "value": "AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI", "value_src": "constant", "usage": "all" } ],
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"ASSOCIATED_RESET": [ { "value": "s_aresetn", "value_src": "constant", "usage": "all" } ],
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"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
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"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
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}
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},
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"RST.ARESETN": {
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@ -350,7 +350,7 @@
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"mode": "slave",
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"parameters": {
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"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
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}
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},
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"BRAM_PORTA": {
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@ -358,12 +358,12 @@
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"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
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"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_static_object": false } ],
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"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
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"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
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},
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"port_maps": {
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"ADDR": [ { "physical_name": "addra" } ],
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@ -379,12 +379,12 @@
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"abstraction_type": "xilinx.com:interface:bram_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
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"MEM_SIZE": [ { "value": "8192", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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"MEM_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
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"MEM_ECC": [ { "value": "NONE", "resolve_type": "generated", "is_static_object": false } ],
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"MASTER_TYPE": [ { "value": "OTHER", "resolve_type": "generated", "is_static_object": false } ],
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"READ_WRITE_MODE": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
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"READ_LATENCY": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_static_object": false } ]
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},
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"port_maps": {
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"ADDR": [ { "physical_name": "addrb" } ],
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