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Update qlaser_dacs_pulse_channel.vhdl

This commit is contained in:
Eric Yu 2023-12-21 16:09:42 -08:00
parent b282a13882
commit 27deb73d58
1 changed files with 0 additions and 7 deletions
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7
src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
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@ -66,12 +66,10 @@ signal ram_pulse_addrb : std_logic_vector( 9 downto 0); -- Address for pul
signal ram_pulse_doutb : std_logic_vector(31 downto 0); -- Data out from pulse RAM signal ram_pulse_doutb : std_logic_vector(31 downto 0); -- Data out from pulse RAM
-- Signal declarations for waveform RAM -- Signal declarations for waveform RAM
signal ram_waveform_ena : std_logic; -- Enable for waveform RAM
signal ram_waveform_wea : std_logic_vector( 0 downto 0); -- Write enable for waveform RAM signal ram_waveform_wea : std_logic_vector( 0 downto 0); -- Write enable for waveform RAM
signal ram_waveform_addra : std_logic_vector(10 downto 0); -- Address for waveform RAM signal ram_waveform_addra : std_logic_vector(10 downto 0); -- Address for waveform RAM
signal ram_waveform_dina : std_logic_vector(31 downto 0); -- Data for waveform RAM signal ram_waveform_dina : std_logic_vector(31 downto 0); -- Data for waveform RAM
signal ram_waveform_douta : std_logic_vector(31 downto 0); -- Data out from waveform RAM signal ram_waveform_douta : std_logic_vector(31 downto 0); -- Data out from waveform RAM
signal ram_waveform_enb : std_logic; -- Enable for waveform RAM
signal ram_waveform_addrb : std_logic_vector(11 downto 0); -- Address for waveform RAM signal ram_waveform_addrb : std_logic_vector(11 downto 0); -- Address for waveform RAM
signal ram_waveform_doutb : std_logic_vector(15 downto 0); -- Data out from waveform RAM signal ram_waveform_doutb : std_logic_vector(15 downto 0); -- Data out from waveform RAM
@ -161,7 +159,6 @@ begin
ram_pulse_dina <= (others=>'0'); ram_pulse_dina <= (others=>'0');
ram_pulse_we <= (others=>'0'); ram_pulse_we <= (others=>'0');
ram_waveform_ena <= '0';
ram_waveform_wea <= (others=>'0'); ram_waveform_wea <= (others=>'0');
ram_waveform_addra <= (others=>'0'); ram_waveform_addra <= (others=>'0');
ram_waveform_dina <= (others=>'0'); ram_waveform_dina <= (others=>'0');
@ -175,7 +172,6 @@ begin
elsif rising_edge(clk) then elsif rising_edge(clk) then
ram_waveform_ena <= '0';
------------------------------------------------- -------------------------------------------------
-- CPU writing RAM -- CPU writing RAM
@ -190,7 +186,6 @@ begin
ram_pulse_we <= (others=>'0'); ram_pulse_we <= (others=>'0');
ram_waveform_wea(0) <= '1'; ram_waveform_wea(0) <= '1';
ram_waveform_ena <= '1';
ram_waveform_addra <= cpu_addr(10 downto 0); ram_waveform_addra <= cpu_addr(10 downto 0);
ram_waveform_dina <= cpu_wdata; ram_waveform_dina <= cpu_wdata;
@ -199,7 +194,6 @@ begin
ram_pulse_addra <= cpu_addr(9 downto 0); ram_pulse_addra <= cpu_addr(9 downto 0);
ram_pulse_dina <= cpu_wdata; ram_pulse_dina <= cpu_wdata;
ram_pulse_we <= std_logic_vector(to_unsigned(1, ram_pulse_we'length)); ram_pulse_we <= std_logic_vector(to_unsigned(1, ram_pulse_we'length));
ram_waveform_ena <= '0';
ram_waveform_wea <= (others=>'0'); ram_waveform_wea <= (others=>'0');
ram_waveform_addra <= (others=>'0'); ram_waveform_addra <= (others=>'0');
ram_waveform_dina <= (others=>'0'); ram_waveform_dina <= (others=>'0');
@ -218,7 +212,6 @@ begin
elsif (cpu_wr = '0') and (cpu_sel = '1') then elsif (cpu_wr = '0') and (cpu_sel = '1') then
if (cpu_addr(C_RAM_SELECT) = '1') then -- Waveform if (cpu_addr(C_RAM_SELECT) = '1') then -- Waveform
ram_waveform_ena <= '1';
ram_pulse_addra <= (others=>'0'); ram_pulse_addra <= (others=>'0');
ram_waveform_addra <= cpu_addr(10 downto 0); ram_waveform_addra <= cpu_addr(10 downto 0);
else -- Pulse else -- Pulse