Update qlaser_dacs_pulse_channel.vhdl
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@ -66,12 +66,10 @@ signal ram_pulse_addrb : std_logic_vector( 9 downto 0); -- Address for pul
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signal ram_pulse_doutb : std_logic_vector(31 downto 0); -- Data out from pulse RAM
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-- Signal declarations for waveform RAM
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signal ram_waveform_ena : std_logic; -- Enable for waveform RAM
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signal ram_waveform_wea : std_logic_vector( 0 downto 0); -- Write enable for waveform RAM
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signal ram_waveform_addra : std_logic_vector(10 downto 0); -- Address for waveform RAM
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signal ram_waveform_dina : std_logic_vector(31 downto 0); -- Data for waveform RAM
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signal ram_waveform_douta : std_logic_vector(31 downto 0); -- Data out from waveform RAM
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signal ram_waveform_enb : std_logic; -- Enable for waveform RAM
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signal ram_waveform_addrb : std_logic_vector(11 downto 0); -- Address for waveform RAM
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signal ram_waveform_doutb : std_logic_vector(15 downto 0); -- Data out from waveform RAM
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@ -161,7 +159,6 @@ begin
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ram_pulse_dina <= (others=>'0');
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ram_pulse_we <= (others=>'0');
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ram_waveform_ena <= '0';
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ram_waveform_wea <= (others=>'0');
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ram_waveform_addra <= (others=>'0');
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ram_waveform_dina <= (others=>'0');
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@ -175,7 +172,6 @@ begin
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elsif rising_edge(clk) then
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ram_waveform_ena <= '0';
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-------------------------------------------------
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-- CPU writing RAM
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@ -190,7 +186,6 @@ begin
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ram_pulse_we <= (others=>'0');
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ram_waveform_wea(0) <= '1';
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ram_waveform_ena <= '1';
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ram_waveform_addra <= cpu_addr(10 downto 0);
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ram_waveform_dina <= cpu_wdata;
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@ -199,7 +194,6 @@ begin
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ram_pulse_addra <= cpu_addr(9 downto 0);
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ram_pulse_dina <= cpu_wdata;
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ram_pulse_we <= std_logic_vector(to_unsigned(1, ram_pulse_we'length));
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ram_waveform_ena <= '0';
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ram_waveform_wea <= (others=>'0');
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ram_waveform_addra <= (others=>'0');
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ram_waveform_dina <= (others=>'0');
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@ -218,7 +212,6 @@ begin
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elsif (cpu_wr = '0') and (cpu_sel = '1') then
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if (cpu_addr(C_RAM_SELECT) = '1') then -- Waveform
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ram_waveform_ena <= '1';
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ram_pulse_addra <= (others=>'0');
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ram_waveform_addra <= cpu_addr(10 downto 0);
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else -- Pulse
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