2023-12-05 02:00:55 +00:00
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create_project zcu_pulse_channel ../../prj -force
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set_property board_part xilinx.com:zcu102:part0:3.4 [current_project]
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add_files {..\..\src\hdl\modules\qlaser_dacs_pulse_channel.vhdl}
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add_files -fileset sim_1 {..\..\src\hdl\tb\tb_cpubus_dacs_pulse_channel_pd.vhdl}
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add_files {..\..\src\hdl\pkg\qlaser_dac_dc_pkg.vhd}
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add_files {..\..\src\hdl\pkg\qlaser_pkg.vhd}
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add_files {..\..\src\hdl\pkg\iopakp.vhd}
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add_files {..\..\src\hdl\pkg\iopakb.vhd}
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2023-12-05 06:14:26 +00:00
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read_ip {..\xilinx-zcu\bram_pulseposition\bram_pulseposition.xci}
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read_ip {..\xilinx-zcu\bram_waveform\bram_waveform.xci}
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read_ip {..\xilinx-zcu\fifo_data_to_stream\fifo_data_to_stream.xci}
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2023-12-05 02:00:55 +00:00
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2023-12-05 06:14:26 +00:00
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# upgrade_ip [get_ips -filter {SCOPE !~ "*.bd"}]
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2023-12-05 02:00:55 +00:00
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generate_target all [get_ips -filter {SCOPE !~ "*.bd"}]
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2023-12-05 06:14:26 +00:00
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# Run the synthesis and generate the IP output products
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launch_runs synth_1
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# Wait for the synthesis to complete
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wait_on_run synth_1
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2023-12-05 02:00:55 +00:00
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exit
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