----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 10/14/2023 12:29:16 PM
-- Design Name: 
-- Module Name: blink_tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity blink_tb is
    -- Port ( CLK_125_N : in STD_LOGIC;
    --        GPIO_SW_C : in STD_LOGIC;
    --        GPIO_LED_7 : out STD_LOGIC);
end blink_tb;

architecture test of blink_tb is
        signal CLK_125_N : STD_LOGIC := '0';
        signal GPIO_SW_C : STD_LOGIC := '0';
        signal GPIO_LED_7 : STD_LOGIC := '0';
begin
    dut: entity work.blink
        port map(
            CLK_125_N => CLK_125_N,
            GPIO_SW_C => GPIO_SW_C,
            GPIO_LED_7 => GPIO_LED_7
        );
    CLK_125_N <= not CLK_125_N after 1 ps;
    

    -- Stimulus process
    process
    begin
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        
        GPIO_SW_C <= '1';
        wait for 10 ps;
        
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        wait until rising_edge(CLK_125_N);
        
        GPIO_SW_C <= '0';
        
        wait for 1 ns;
        
        wait;
    end process;
    -- process
    -- begin
    --     GPIO_SW_C <= '0';
    --     wait for 10 ns;
    --     GPIO_SW_C <= '1';
    --     wait for 10 ns;
    -- end process;

end test;