125 lines
4.4 KiB
VHDL
125 lines
4.4 KiB
VHDL
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--------------------------------------------------------------------------
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-- File : clkreset.vhd
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----------------------------------------------------------------------------
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-- Description : Wrapper for clock PLL and reset logic
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--
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-- External 'p_reset' input resets the PLL immediately and sets the 'reset'
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-- active high to the internal FPGA logic.
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-- When the reset goes inactive the PLL will try to generate the requested
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-- output freq clock 'clk_i' for the FPGA internal logic from the 'p_clk' input.
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-- Once the PLL output clock is stable the PLL sets the 'pll_locked' output high.
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-- A counter then increments to 255 and then the 'reset' output is set low
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-- to allow the FPGA logic to run.
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--
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-- *** Check p_reset_n polarity, design assumes active low ***
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--
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity clkreset is
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port(
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-- Reset and clock from pads
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p_reset : in std_logic; -- From RESET input pad
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p_clk_n : in std_logic; -- From CLOCK input pad, N
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p_clk_p : in std_logic; -- From CLOCK input pad, P
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-- Reset and clock outputs to all internal logic
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clk : out std_logic;
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lock : out std_logic;
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reset : out std_logic
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);
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end clkreset;
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------------------------------------------------------------------------
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-- Structural architecture instantiates a vendor IP block clock tile.
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------------------------------------------------------------------------
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architecture struct of clkreset is
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signal pll_locked : std_logic;
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signal pll_locked_d1 : std_logic := '0';
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signal clk_i : std_logic;
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signal cnt_reset : unsigned(7 downto 0) := X"00";
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signal reset_pll : std_logic;
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-- Clock generator IP. Use MMCM or PLL
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-- component clkpll
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-- port (
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-- refclk : in std_logic := '0'; -- refclk.clk
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-- reset : in std_logic := '0'; -- reset.reset
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-- outclk_0 : out std_logic; -- outclk0.clk
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-- locked : out std_logic -- locked.export
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-- );
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-- end component;
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component clk_wiz_0
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port (-- Clock in ports
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-- Clock out ports
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outclk_0 : out std_logic;
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-- Status and control signals
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reset : in std_logic;
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locked : out std_logic;
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clk_in1_p : in std_logic; -- refclk, P
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clk_in1_n : in std_logic -- refclk, N
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);
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end component;
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begin
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clk <= clk_i;
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lock <= pll_locked_d1;
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reset_pll <= p_reset;
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---------------------------------------------------------------------------------
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-- Clock generator. 100 MHz clock from XX MHz board clock input
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---------------------------------------------------------------------------------
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-- u_clkpll : clkpll
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-- port map(
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-- refclk => p_clk , -- in std_logic := '0'; -- refclk.clk
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-- reset => reset_pll , -- in std_logic := '0'; -- reset.reset
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-- outclk_0 => clk_i , -- out std_logic; -- outclk0.clk
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-- locked => pll_locked -- out std_logic -- locked.export
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-- );
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u_clkpll : clk_wiz_0
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port map (
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-- Clock out ports
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outclk_0 => clk_i, -- out
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-- Status and control signals
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reset => reset_pll, -- in
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locked => pll_locked, -- out
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-- Clock in ports
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clk_in1_p => p_clk_p, -- in
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clk_in1_n => p_clk_n -- in
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);
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-------------------------------------------------------------------------------
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-- Keep main logic reset until PLL locked for 255 clock cycles
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-------------------------------------------------------------------------------
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pr_reset : process (p_reset, pll_locked, clk_i)
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begin
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if (p_reset = '1' or pll_locked = '0') then
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reset <= '1';
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pll_locked_d1 <= '0';
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cnt_reset <= X"00";
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elsif rising_edge(clk_i) then
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pll_locked_d1 <= pll_locked;
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if (pll_locked_d1 = '1' and cnt_reset < X"FF") then
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cnt_reset <= cnt_reset + 1;
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end if;
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if (cnt_reset < X"FF") then
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reset <= '1';
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else
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reset <= '0';
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end if;
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end if;
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end process;
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end struct;
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