88 lines
3.9 KiB
Markdown
88 lines
3.9 KiB
Markdown
# CPU Regfiles
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The 31x64-bit register file with a read and write port used on the [Arm-compliant CPU](https://git.long-vega.ts.net/eyhc/Pipline_Arm_CPU).
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### Test Plan\
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#### Objective
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To verify the functionality of a 32x64-bit register file implemented in Verilog, ensuring it meets design specifications and performs correctly under various scenarios.
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#### Test Environment
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- Simulation Tool: Cadence Xcelium (ModelSim as fallback)
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- Design Language: Verilog
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- Testbench: `regstim.v`
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#### Test Cases
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1. **Register Write and Read Test**
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- **Objective**: Verify that data can be correctly written to and read from each register.
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- **Test Steps**:
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1. Initialize the register file.
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2. Write unique values to each register.
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3. Read back the values from each register.
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- **Assertions**:
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- Each read value should match the corresponding written value.
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- **Coverage**:
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- Ensure all 32 registers (0-31) are tested for write and read operations.
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2. **Register 31 Read-Only Test**
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- **Objective**: Ensure that register 31 always outputs zero regardless of any write attempts.
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- **Test Steps**:
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1. Attempt to write various values to register 31.
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2. Read the value from register 31.
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- **Assertions**:
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- The value read from register 31 should always be zero.
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- **Coverage**:
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- Multiple write attempts with different values to register 31.
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3. **Write Enable Test**
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- **Objective**: Verify that data is written to a register only when the write enable signal is active.
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- **Test Steps**:
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1. Attempt to write a value to a register with the write enable signal inactive.
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2. Activate the write enable signal and write a different value to the same register.
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3. Read the value from the register.
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- **Assertions**:
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- The register should hold the old value when write enable is inactive and update to the new value when write enable is active.
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- **Coverage**:
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- Test with multiple registers and different write enable signal timings.
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4. **Clock Edge Synchronization Test**
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- **Objective**: Ensure that registers update values only on the positive edge of the clock signal.
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- **Test Steps**:
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1. Write a value to a register.
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2. Change the value on the data bus without a clock edge.
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3. Read the register value.
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4. Trigger a clock edge and write a new value to the register.
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5. Read the register value again.
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- **Assertions**:
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- The register should not change its value until the positive edge of the clock signal.
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- **Coverage**:
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- Test with multiple registers and different data values.
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5. **Multiplexor Functionality Test**
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- **Objective**: Verify the correct functionality of the multiplexors in selecting the appropriate register values for reading.
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- **Test Steps**:
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1. Write distinct values to multiple registers.
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2. Use the multiplexors to select and read values from these registers.
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- **Assertions**:
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- The output should match the value of the selected register.
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- **Coverage**:
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- Test all 32 registers with various selection scenarios.
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#### Coverage Criteria
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- **Functional Coverage**:
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- All registers (0-31) must be tested for read and write operations.
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- Register 31 should be tested for its read-only property.
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- Write enable signal should be tested under various scenarios.
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- Clock edge synchronization must be verified.
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- Multiplexors should be tested to ensure correct value selection.
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- **Code Coverage**:
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- Ensure that every line of Verilog code is executed at least once during the tests.
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- Include edge cases and boundary conditions in testing.
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### Implementation
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The provided `regstim.v` testbench can be modified to include the above test cases. Ensure that each test case is clearly defined and assertions are added to validate the expected outcomes.
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By following this test plan, the functionality and robustness of the 32x64-bit ARM register file can be thoroughly verified.
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