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README.md

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 # CPU Regfiles
 
 The 31x64-bit register file with a read and write port used on the [Arm-compliant CPU](https://git.long-vega.ts.net/eyhc/Pipline_Arm_CPU). 
+### Test Plan\
+
+#### Objective
+To verify the functionality of a 32x64-bit register file implemented in Verilog, ensuring it meets design specifications and performs correctly under various scenarios.
+
+#### Test Environment
+- Simulation Tool: Cadence Xcelium (ModelSim as fallback)
+- Design Language: Verilog
+- Testbench: `regstim.v`
+
+#### Test Cases
+
+1. **Register Write and Read Test**
+   - **Objective**: Verify that data can be correctly written to and read from each register.
+   - **Test Steps**:
+     1. Initialize the register file.
+     2. Write unique values to each register.
+     3. Read back the values from each register.
+   - **Assertions**:
+     - Each read value should match the corresponding written value.
+   - **Coverage**:
+     - Ensure all 32 registers (0-31) are tested for write and read operations.
+
+2. **Register 31 Read-Only Test**
+   - **Objective**: Ensure that register 31 always outputs zero regardless of any write attempts.
+   - **Test Steps**:
+     1. Attempt to write various values to register 31.
+     2. Read the value from register 31.
+   - **Assertions**:
+     - The value read from register 31 should always be zero.
+   - **Coverage**:
+     - Multiple write attempts with different values to register 31.
+
+3. **Write Enable Test**
+   - **Objective**: Verify that data is written to a register only when the write enable signal is active.
+   - **Test Steps**:
+     1. Attempt to write a value to a register with the write enable signal inactive.
+     2. Activate the write enable signal and write a different value to the same register.
+     3. Read the value from the register.
+   - **Assertions**:
+     - The register should hold the old value when write enable is inactive and update to the new value when write enable is active.
+   - **Coverage**:
+     - Test with multiple registers and different write enable signal timings.
+
+4. **Clock Edge Synchronization Test**
+   - **Objective**: Ensure that registers update values only on the positive edge of the clock signal.
+   - **Test Steps**:
+     1. Write a value to a register.
+     2. Change the value on the data bus without a clock edge.
+     3. Read the register value.
+     4. Trigger a clock edge and write a new value to the register.
+     5. Read the register value again.
+   - **Assertions**:
+     - The register should not change its value until the positive edge of the clock signal.
+   - **Coverage**:
+     - Test with multiple registers and different data values.
+
+5. **Multiplexor Functionality Test**
+   - **Objective**: Verify the correct functionality of the multiplexors in selecting the appropriate register values for reading.
+   - **Test Steps**:
+     1. Write distinct values to multiple registers.
+     2. Use the multiplexors to select and read values from these registers.
+   - **Assertions**:
+     - The output should match the value of the selected register.
+   - **Coverage**:
+     - Test all 32 registers with various selection scenarios.
+
+#### Coverage Criteria
+- **Functional Coverage**:
+  - All registers (0-31) must be tested for read and write operations.
+  - Register 31 should be tested for its read-only property.
+  - Write enable signal should be tested under various scenarios.
+  - Clock edge synchronization must be verified.
+  - Multiplexors should be tested to ensure correct value selection.
+
+- **Code Coverage**:
+  - Ensure that every line of Verilog code is executed at least once during the tests.
+  - Include edge cases and boundary conditions in testing.
+
+### Implementation
+
+The provided `regstim.v` testbench can be modified to include the above test cases. Ensure that each test case is clearly defined and assertions are added to validate the expected outcomes.
+
+By following this test plan, the functionality and robustness of the 32x64-bit ARM register file can be thoroughly verified.