891 lines
37 KiB
Tcl
891 lines
37 KiB
Tcl
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################################################################
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# This is a generated script based on design: ps1
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2018.2
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source ps1_script.tcl
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xc7z020clg484-1
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set_property BOARD_PART digilentinc.com:eclypse-z7:part0:1.1 [current_project]
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name ps1
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:axi_bram_ctrl:4.*\
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xilinx.com:ip:blk_mem_gen:8.*\
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xilinx.com:ip:smartconnect:1.*\
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xilinx.com:ip:processing_system7:5.*\
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xilinx.com:ip:proc_sys_reset:5.*\
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"
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set list_ips_missing ""
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common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
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set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
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# Create ports
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set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ]
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set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ]
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set ext_reset_n [ create_bd_port -dir I -type rst ext_reset_n ]
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set_property -dict [ list \
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CONFIG.POLARITY {ACTIVE_LOW} \
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] $ext_reset_n
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# Create instance: axi_bram_ctrl, and set properties
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set axi_bram_ctrl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.* axi_bram_ctrl ]
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# Create instance: axi_bram_ctrl_bram, and set properties
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set axi_bram_ctrl_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.* axi_bram_ctrl_bram ]
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set_property -dict [ list \
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CONFIG.Memory_Type {True_Dual_Port_RAM} \
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] $axi_bram_ctrl_bram
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# Create instance: axi_smc, and set properties
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set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.* axi_smc ]
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set_property -dict [ list \
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CONFIG.NUM_SI {1} \
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] $axi_smc
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# Create instance: processing_system7_0, and set properties
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set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.* processing_system7_0 ]
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set_property -dict [ list \
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CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
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CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
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CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
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CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
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CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
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CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {20.000000} \
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CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
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CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
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CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
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CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
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CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
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CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \
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CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
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CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
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CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
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CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
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CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
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CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
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CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
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CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
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CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
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CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
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CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
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CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
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CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
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CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
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CONFIG.PCW_CLK0_FREQ {100000000} \
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CONFIG.PCW_CLK1_FREQ {10000000} \
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CONFIG.PCW_CLK2_FREQ {10000000} \
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CONFIG.PCW_CLK3_FREQ {10000000} \
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CONFIG.PCW_CORE0_FIQ_INTR {0} \
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CONFIG.PCW_CORE0_IRQ_INTR {0} \
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CONFIG.PCW_CORE1_FIQ_INTR {0} \
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CONFIG.PCW_CORE1_IRQ_INTR {0} \
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CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
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CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
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CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
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CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
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CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
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CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
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CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
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CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
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CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
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CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
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CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
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CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
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CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
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CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
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CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
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CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
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CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
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CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
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CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
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CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
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CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
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CONFIG.PCW_DDR_RAM_HIGHADDR {0x3FFFFFFF} \
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CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
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CONFIG.PCW_DM_WIDTH {4} \
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CONFIG.PCW_DQS_WIDTH {4} \
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CONFIG.PCW_DQ_WIDTH {32} \
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CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
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CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {0} \
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CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
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CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
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CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
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CONFIG.PCW_ENET0_RESET_ENABLE {0} \
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CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
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CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
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CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
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CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
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CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
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CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
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CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
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CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
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CONFIG.PCW_ENET1_RESET_ENABLE {0} \
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CONFIG.PCW_ENET_RESET_ENABLE {0} \
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CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
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CONFIG.PCW_EN_4K_TIMER {0} \
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CONFIG.PCW_EN_CAN0 {0} \
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CONFIG.PCW_EN_CAN1 {0} \
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CONFIG.PCW_EN_CLK0_PORT {1} \
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CONFIG.PCW_EN_CLK1_PORT {0} \
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CONFIG.PCW_EN_CLK2_PORT {0} \
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CONFIG.PCW_EN_CLK3_PORT {0} \
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CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
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CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
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CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
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CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
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CONFIG.PCW_EN_DDR {1} \
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CONFIG.PCW_EN_EMIO_CAN0 {0} \
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CONFIG.PCW_EN_EMIO_CAN1 {0} \
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CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
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CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
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CONFIG.PCW_EN_EMIO_ENET0 {0} \
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CONFIG.PCW_EN_EMIO_ENET1 {0} \
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CONFIG.PCW_EN_EMIO_GPIO {0} \
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CONFIG.PCW_EN_EMIO_I2C0 {0} \
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CONFIG.PCW_EN_EMIO_I2C1 {0} \
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CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
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CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
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CONFIG.PCW_EN_EMIO_PJTAG {0} \
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CONFIG.PCW_EN_EMIO_SDIO0 {0} \
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CONFIG.PCW_EN_EMIO_SDIO1 {0} \
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CONFIG.PCW_EN_EMIO_SPI0 {0} \
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CONFIG.PCW_EN_EMIO_SPI1 {0} \
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CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
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CONFIG.PCW_EN_EMIO_TRACE {0} \
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CONFIG.PCW_EN_EMIO_TTC0 {0} \
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CONFIG.PCW_EN_EMIO_TTC1 {0} \
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CONFIG.PCW_EN_EMIO_UART0 {0} \
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CONFIG.PCW_EN_EMIO_UART1 {0} \
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CONFIG.PCW_EN_EMIO_WDT {0} \
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CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
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CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
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CONFIG.PCW_EN_ENET0 {0} \
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CONFIG.PCW_EN_ENET1 {0} \
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CONFIG.PCW_EN_GPIO {0} \
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CONFIG.PCW_EN_I2C0 {0} \
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CONFIG.PCW_EN_I2C1 {0} \
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CONFIG.PCW_EN_MODEM_UART0 {0} \
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CONFIG.PCW_EN_MODEM_UART1 {0} \
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CONFIG.PCW_EN_PJTAG {0} \
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CONFIG.PCW_EN_PTP_ENET0 {0} \
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CONFIG.PCW_EN_PTP_ENET1 {0} \
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CONFIG.PCW_EN_QSPI {1} \
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CONFIG.PCW_EN_RST0_PORT {1} \
|
|
CONFIG.PCW_EN_RST1_PORT {0} \
|
|
CONFIG.PCW_EN_RST2_PORT {0} \
|
|
CONFIG.PCW_EN_RST3_PORT {0} \
|
|
CONFIG.PCW_EN_SDIO0 {1} \
|
|
CONFIG.PCW_EN_SDIO1 {0} \
|
|
CONFIG.PCW_EN_SMC {0} \
|
|
CONFIG.PCW_EN_SPI0 {0} \
|
|
CONFIG.PCW_EN_SPI1 {0} \
|
|
CONFIG.PCW_EN_TRACE {0} \
|
|
CONFIG.PCW_EN_TTC0 {0} \
|
|
CONFIG.PCW_EN_TTC1 {0} \
|
|
CONFIG.PCW_EN_UART0 {1} \
|
|
CONFIG.PCW_EN_UART1 {0} \
|
|
CONFIG.PCW_EN_USB0 {0} \
|
|
CONFIG.PCW_EN_USB1 {0} \
|
|
CONFIG.PCW_EN_WDT {0} \
|
|
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {4} \
|
|
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {3} \
|
|
CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
|
|
CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
|
|
CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
|
|
CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
|
|
CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
|
|
CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
|
|
CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
|
|
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
|
|
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \
|
|
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
|
|
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
|
|
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
|
|
CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
|
|
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
|
|
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
|
|
CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {1} \
|
|
CONFIG.PCW_GP0_NUM_READ_THREADS {4} \
|
|
CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \
|
|
CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {1} \
|
|
CONFIG.PCW_GP1_NUM_READ_THREADS {4} \
|
|
CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \
|
|
CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
|
|
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
|
|
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
|
|
CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
|
|
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {0} \
|
|
CONFIG.PCW_GPIO_MIO_GPIO_IO {<Select>} \
|
|
CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
|
|
CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
|
|
CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
|
|
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
|
|
CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
|
|
CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
|
|
CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
|
|
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
|
|
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
|
|
CONFIG.PCW_I2C_RESET_ENABLE {0} \
|
|
CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
|
|
CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
|
|
CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
|
|
CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
|
|
CONFIG.PCW_IOPLL_CTRL_FBDIV {36} \
|
|
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1200.000} \
|
|
CONFIG.PCW_IRQ_F2P_INTR {0} \
|
|
CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
|
|
CONFIG.PCW_MIO_14_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_14_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_14_SLEW {slow} \
|
|
CONFIG.PCW_MIO_15_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_15_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_15_SLEW {slow} \
|
|
CONFIG.PCW_MIO_1_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_1_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_1_SLEW {slow} \
|
|
CONFIG.PCW_MIO_2_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_2_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_2_SLEW {slow} \
|
|
CONFIG.PCW_MIO_3_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_3_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_3_SLEW {slow} \
|
|
CONFIG.PCW_MIO_40_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_40_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_40_SLEW {slow} \
|
|
CONFIG.PCW_MIO_41_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_41_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_41_SLEW {slow} \
|
|
CONFIG.PCW_MIO_42_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_42_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_42_SLEW {slow} \
|
|
CONFIG.PCW_MIO_43_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_43_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_43_SLEW {slow} \
|
|
CONFIG.PCW_MIO_44_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_44_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_44_SLEW {slow} \
|
|
CONFIG.PCW_MIO_45_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_45_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_45_SLEW {slow} \
|
|
CONFIG.PCW_MIO_47_DIRECTION {in} \
|
|
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_47_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_47_SLEW {slow} \
|
|
CONFIG.PCW_MIO_4_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_4_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_4_SLEW {slow} \
|
|
CONFIG.PCW_MIO_5_DIRECTION {inout} \
|
|
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_5_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_5_SLEW {slow} \
|
|
CONFIG.PCW_MIO_6_DIRECTION {out} \
|
|
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_6_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_6_SLEW {slow} \
|
|
CONFIG.PCW_MIO_PRIMITIVE {54} \
|
|
CONFIG.PCW_MIO_TREE_PERIPHERALS {unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 0#UART 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#unassigned#SD 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \
|
|
CONFIG.PCW_MIO_TREE_SIGNALS {unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#rx#tx#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#clk#cmd#data[0]#data[1]#data[2]#data[3]#unassigned#cd#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned} \
|
|
CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \
|
|
CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \
|
|
CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \
|
|
CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \
|
|
CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \
|
|
CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \
|
|
CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \
|
|
CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \
|
|
CONFIG.PCW_NAND_CYCLES_T_AR {1} \
|
|
CONFIG.PCW_NAND_CYCLES_T_CLR {1} \
|
|
CONFIG.PCW_NAND_CYCLES_T_RC {11} \
|
|
CONFIG.PCW_NAND_CYCLES_T_REA {1} \
|
|
CONFIG.PCW_NAND_CYCLES_T_RR {1} \
|
|
CONFIG.PCW_NAND_CYCLES_T_WC {11} \
|
|
CONFIG.PCW_NAND_CYCLES_T_WP {1} \
|
|
CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \
|
|
CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_NOR_CS0_T_CEOE {1} \
|
|
CONFIG.PCW_NOR_CS0_T_PC {1} \
|
|
CONFIG.PCW_NOR_CS0_T_RC {11} \
|
|
CONFIG.PCW_NOR_CS0_T_TR {1} \
|
|
CONFIG.PCW_NOR_CS0_T_WC {11} \
|
|
CONFIG.PCW_NOR_CS0_T_WP {1} \
|
|
CONFIG.PCW_NOR_CS0_WE_TIME {0} \
|
|
CONFIG.PCW_NOR_CS1_T_CEOE {1} \
|
|
CONFIG.PCW_NOR_CS1_T_PC {1} \
|
|
CONFIG.PCW_NOR_CS1_T_RC {11} \
|
|
CONFIG.PCW_NOR_CS1_T_TR {1} \
|
|
CONFIG.PCW_NOR_CS1_T_WC {11} \
|
|
CONFIG.PCW_NOR_CS1_T_WP {1} \
|
|
CONFIG.PCW_NOR_CS1_WE_TIME {0} \
|
|
CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \
|
|
CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \
|
|
CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \
|
|
CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \
|
|
CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \
|
|
CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \
|
|
CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \
|
|
CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \
|
|
CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \
|
|
CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \
|
|
CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \
|
|
CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \
|
|
CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \
|
|
CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \
|
|
CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \
|
|
CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \
|
|
CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \
|
|
CONFIG.PCW_P2F_CAN0_INTR {0} \
|
|
CONFIG.PCW_P2F_CAN1_INTR {0} \
|
|
CONFIG.PCW_P2F_CTI_INTR {0} \
|
|
CONFIG.PCW_P2F_DMAC0_INTR {0} \
|
|
CONFIG.PCW_P2F_DMAC1_INTR {0} \
|
|
CONFIG.PCW_P2F_DMAC2_INTR {0} \
|
|
CONFIG.PCW_P2F_DMAC3_INTR {0} \
|
|
CONFIG.PCW_P2F_DMAC4_INTR {0} \
|
|
CONFIG.PCW_P2F_DMAC5_INTR {0} \
|
|
CONFIG.PCW_P2F_DMAC6_INTR {0} \
|
|
CONFIG.PCW_P2F_DMAC7_INTR {0} \
|
|
CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \
|
|
CONFIG.PCW_P2F_ENET0_INTR {0} \
|
|
CONFIG.PCW_P2F_ENET1_INTR {0} \
|
|
CONFIG.PCW_P2F_GPIO_INTR {0} \
|
|
CONFIG.PCW_P2F_I2C0_INTR {0} \
|
|
CONFIG.PCW_P2F_I2C1_INTR {0} \
|
|
CONFIG.PCW_P2F_QSPI_INTR {0} \
|
|
CONFIG.PCW_P2F_SDIO0_INTR {0} \
|
|
CONFIG.PCW_P2F_SDIO1_INTR {0} \
|
|
CONFIG.PCW_P2F_SMC_INTR {0} \
|
|
CONFIG.PCW_P2F_SPI0_INTR {0} \
|
|
CONFIG.PCW_P2F_SPI1_INTR {0} \
|
|
CONFIG.PCW_P2F_UART0_INTR {0} \
|
|
CONFIG.PCW_P2F_UART1_INTR {0} \
|
|
CONFIG.PCW_P2F_USB0_INTR {0} \
|
|
CONFIG.PCW_P2F_USB1_INTR {0} \
|
|
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.063} \
|
|
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.062} \
|
|
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.065} \
|
|
CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.083} \
|
|
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.007} \
|
|
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.010} \
|
|
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.006} \
|
|
CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.048} \
|
|
CONFIG.PCW_PACKAGE_NAME {clg484} \
|
|
CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {6} \
|
|
CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \
|
|
CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \
|
|
CONFIG.PCW_PJTAG_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \
|
|
CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_PS7_SI_REV {PRODUCTION} \
|
|
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
|
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {6} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
|
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
|
CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
|
|
CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
|
|
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
|
|
CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \
|
|
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
|
|
CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \
|
|
CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \
|
|
CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \
|
|
CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \
|
|
CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \
|
|
CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \
|
|
CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {60} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {20} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
|
|
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
|
|
CONFIG.PCW_SMC_CYCLE_T0 {NA} \
|
|
CONFIG.PCW_SMC_CYCLE_T1 {NA} \
|
|
CONFIG.PCW_SMC_CYCLE_T2 {NA} \
|
|
CONFIG.PCW_SMC_CYCLE_T3 {NA} \
|
|
CONFIG.PCW_SMC_CYCLE_T4 {NA} \
|
|
CONFIG.PCW_SMC_CYCLE_T5 {NA} \
|
|
CONFIG.PCW_SMC_CYCLE_T6 {NA} \
|
|
CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \
|
|
CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \
|
|
CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \
|
|
CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \
|
|
CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \
|
|
CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \
|
|
CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \
|
|
CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \
|
|
CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \
|
|
CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \
|
|
CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \
|
|
CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \
|
|
CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \
|
|
CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \
|
|
CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \
|
|
CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \
|
|
CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \
|
|
CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \
|
|
CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \
|
|
CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \
|
|
CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \
|
|
CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \
|
|
CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \
|
|
CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \
|
|
CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \
|
|
CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \
|
|
CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \
|
|
CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \
|
|
CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \
|
|
CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \
|
|
CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \
|
|
CONFIG.PCW_TRACE_GRP_16BIT_ENABLE {0} \
|
|
CONFIG.PCW_TRACE_GRP_2BIT_ENABLE {0} \
|
|
CONFIG.PCW_TRACE_GRP_32BIT_ENABLE {0} \
|
|
CONFIG.PCW_TRACE_GRP_4BIT_ENABLE {0} \
|
|
CONFIG.PCW_TRACE_GRP_8BIT_ENABLE {0} \
|
|
CONFIG.PCW_TRACE_INTERNAL_WIDTH {2} \
|
|
CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \
|
|
CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \
|
|
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
|
|
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
|
|
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
|
|
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
|
|
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
|
|
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
|
|
CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \
|
|
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \
|
|
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \
|
|
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \
|
|
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \
|
|
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \
|
|
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \
|
|
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \
|
|
CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \
|
|
CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
|
|
CONFIG.PCW_UART0_BASEADDR {0xE0000000} \
|
|
CONFIG.PCW_UART0_BAUD_RATE {115200} \
|
|
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
|
|
CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \
|
|
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \
|
|
CONFIG.PCW_UART1_BASEADDR {0xE0001000} \
|
|
CONFIG.PCW_UART1_BAUD_RATE {115200} \
|
|
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
|
|
CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \
|
|
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \
|
|
CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {12} \
|
|
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
|
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
|
|
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
|
|
CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_AL {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \
|
|
CONFIG.PCW_UIPARAM_DDR_BL {8} \
|
|
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.25} \
|
|
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.25} \
|
|
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.25} \
|
|
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.25} \
|
|
CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit} \
|
|
CONFIG.PCW_UIPARAM_DDR_CL {7} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {61.0905} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {61.0905} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {61.0905} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {61.0905} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \
|
|
CONFIG.PCW_UIPARAM_DDR_CWL {6} \
|
|
CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {68.4725} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {71.086} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {66.794} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {108.7385} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {64.1705} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {63.686} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {68.46} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {105.4895} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \
|
|
CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \
|
|
CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \
|
|
CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \
|
|
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {533.333} \
|
|
CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \
|
|
CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3 (Low Voltage)} \
|
|
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \
|
|
CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \
|
|
CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \
|
|
CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {0} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \
|
|
CONFIG.PCW_UIPARAM_DDR_T_RP {7} \
|
|
CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \
|
|
CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \
|
|
CONFIG.PCW_USB0_BASEADDR {0xE0102000} \
|
|
CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \
|
|
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \
|
|
CONFIG.PCW_USB0_RESET_ENABLE {0} \
|
|
CONFIG.PCW_USB1_BASEADDR {0xE0103000} \
|
|
CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \
|
|
CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \
|
|
CONFIG.PCW_USB1_RESET_ENABLE {0} \
|
|
CONFIG.PCW_USB_RESET_ENABLE {0} \
|
|
CONFIG.PCW_USB_RESET_POLARITY {Active Low} \
|
|
CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \
|
|
CONFIG.PCW_USE_AXI_NONSECURE {0} \
|
|
CONFIG.PCW_USE_CORESIGHT {0} \
|
|
CONFIG.PCW_USE_CROSS_TRIGGER {0} \
|
|
CONFIG.PCW_USE_CR_FABRIC {1} \
|
|
CONFIG.PCW_USE_DDR_BYPASS {0} \
|
|
CONFIG.PCW_USE_DEBUG {0} \
|
|
CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \
|
|
CONFIG.PCW_USE_DMA0 {0} \
|
|
CONFIG.PCW_USE_DMA1 {0} \
|
|
CONFIG.PCW_USE_DMA2 {0} \
|
|
CONFIG.PCW_USE_DMA3 {0} \
|
|
CONFIG.PCW_USE_EXPANDED_IOP {0} \
|
|
CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \
|
|
CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
|
|
CONFIG.PCW_USE_HIGH_OCM {0} \
|
|
CONFIG.PCW_USE_M_AXI_GP0 {1} \
|
|
CONFIG.PCW_USE_M_AXI_GP1 {0} \
|
|
CONFIG.PCW_USE_PROC_EVENT_BUS {0} \
|
|
CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \
|
|
CONFIG.PCW_USE_S_AXI_ACP {0} \
|
|
CONFIG.PCW_USE_S_AXI_GP0 {0} \
|
|
CONFIG.PCW_USE_S_AXI_GP1 {0} \
|
|
CONFIG.PCW_USE_S_AXI_HP0 {0} \
|
|
CONFIG.PCW_USE_S_AXI_HP1 {0} \
|
|
CONFIG.PCW_USE_S_AXI_HP2 {0} \
|
|
CONFIG.PCW_USE_S_AXI_HP3 {0} \
|
|
CONFIG.PCW_USE_TRACE {0} \
|
|
CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \
|
|
CONFIG.PCW_VALUE_SILVERSION {3} \
|
|
CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \
|
|
CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \
|
|
CONFIG.PCW_WDT_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \
|
|
] $processing_system7_0
|
|
|
|
# Create instance: rst_ps7_0_100M, and set properties
|
|
set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.* rst_ps7_0_100M ]
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net axi_bram_ctrl_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl/BRAM_PORTA] [get_bd_intf_pins axi_bram_ctrl_bram/BRAM_PORTA]
|
|
connect_bd_intf_net -intf_net axi_bram_ctrl_BRAM_PORTB [get_bd_intf_pins axi_bram_ctrl/BRAM_PORTB] [get_bd_intf_pins axi_bram_ctrl_bram/BRAM_PORTB]
|
|
connect_bd_intf_net -intf_net axi_smc_M00_AXI [get_bd_intf_pins axi_bram_ctrl/S_AXI] [get_bd_intf_pins axi_smc/M00_AXI]
|
|
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
|
|
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
|
|
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins axi_smc/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net aux_reset_in_0_1 [get_bd_ports ext_reset_n] [get_bd_pins rst_ps7_0_100M/aux_reset_in]
|
|
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins axi_bram_ctrl/s_axi_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk]
|
|
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
|
|
connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins axi_bram_ctrl/s_axi_aresetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn]
|
|
|
|
# Create address segments
|
|
create_bd_addr_seg -range 0x00020000 -offset 0x40000000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_bram_ctrl/S_AXI/Mem0] SEG_axi_bram_ctrl_Mem0
|
|
|
|
|
|
# Restore current instance
|
|
current_bd_instance $oldCurInst
|
|
|
|
save_bd_design
|
|
}
|
|
# End of create_root_design()
|
|
|
|
|
|
##################################################################
|
|
# MAIN FLOW
|
|
##################################################################
|
|
|
|
create_root_design ""
|
|
|
|
|