xilinx.com xci unknown 1.0 bram_pulse_definition 4096 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 1 0 0 0 1 100000000 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0.0 AXI4LITE READ_WRITE 0 0 0 0 0 OTHER NONE 8192 32 1 OTHER NONE 8192 32 1 100000000 0 0 0.0 0 10 10 1 4 0 1 9 1 0 1 NONE 0 0 0 ./ 0 0 0 0 0 0 0 0 Estimated Power for IP : 4.465107 mW zynquplus 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bram_pulse_definition.mem no_coe_file_loaded 0 0 2 0 1 1024 1024 1 1 32 32 0 0 CE CE ALL 0 0 0 0 0 0 0 1 1 1024 1024 READ_FIRST READ_FIRST 32 32 zynquplus 4 Memory_Slave AXI4_Full false Minimum_Area true 9 NONE no_coe_file_loaded ALL bram_pulse_definition false false false false false false false false false Always_Enabled Always_Enabled Single_Bit_Error_Injection false Native false no_mem_loaded True_Dual_Port_RAM READ_FIRST READ_FIRST 0 0 BRAM 0 100 100 50 100 100 50 8kx2 false false 1 1 32 32 false false false false 0 false false CE CE SYNC false false false false false false false 1024 32 32 No_ECC false false false Stand_Alone zynquplus xilinx.com:zcu102:part0:3.4 xczu9eg ffvb1156 VERILOG MIXED -2 E TRUE TRUE IP_Flow 5 TRUE ../../../prj/zcu_pulse_channel.gen/sources_1/ip/bram_pulse_definition . 2022.1.2 OUT_OF_CONTEXT