create_project zcu_pulse_channel ../../prj -force

set_property board_part xilinx.com:zcu102:part0:3.4 [current_project]

add_files {..\..\src\hdl\modules\qlaser_dacs_pulse_channel.vhdl}
add_files -fileset sim_1 {..\..\src\hdl\tb\tb_cpubus_dacs_pulse_channel.vhdl}
add_files {..\..\src\hdl\pkg\qlaser_dac_dc_pkg.vhd}
add_files {..\..\src\hdl\pkg\qlaser_pkg.vhd}
add_files {..\..\src\hdl\pkg\iopakp.vhd}
add_files {..\..\src\hdl\pkg\iopakb.vhd}
read_ip {..\xilinx-zcu\bram_pulseposition\bram_pulseposition.xci}
read_ip {..\xilinx-zcu\bram_waveform\bram_waveform.xci}
read_ip {..\xilinx-zcu\fifo_data_to_stream\fifo_data_to_stream.xci}
read_ip {..\xilinx-zcu\bram_pulse_definition\bram_pulse_definition.xci}

# upgrade_ip [get_ips -filter {SCOPE !~ "*.bd"}]
generate_target all [get_ips -filter {SCOPE !~ "*.bd"}]

# Run the synthesis and generate the IP output products
launch_runs synth_1

# Wait for the synthesis to complete
wait_on_run synth_1

# Generate the simulation models
proc recursive_glob {dir} {
    set files [glob -nocomplain -type f -directory $dir *_sim_netlist.vhdl]
    foreach subdir [glob -nocomplain -type d -directory $dir *] {
        lappend files {*}[recursive_glob $subdir]
    }
    return $files
}

set src_dir ../../prj/zcu_pulse_channel.gen/sources_1/ip/
set files [recursive_glob $src_dir]

foreach file $files {
    file copy -force $file ../../src/hdl/ip_gen
}

exit