xilinx.com BlockDiagram ps1 1.00.a isTop true FIXED_IO CAN_DEBUG false DDR CAN_DEBUG false TIMEPERIOD_PS 1250 MEMORY_TYPE COMPONENTS DATA_WIDTH 8 CS_ENABLED true DATA_MASK_ENABLED true SLOT Single MEM_ADDR_MAP ROW_COLUMN_BANK BURST_LENGTH 8 AXI_ARBITRATION_SCHEME TDM CAS_LATENCY 11 CAS_WRITE_LATENCY 11 CLK.FCLK_CLK0 Clk Clock CLK FCLK_CLK0 FREQ_HZ 100000000 PHASE 0.000 CLK_DOMAIN ps1_processing_system7_0_0_FCLK_CLK0 RST.FCLK_RESET0_N Reset Reset RST FCLK_RESET0_N POLARITY ACTIVE_LOW RST.EXT_RESET_N Reset Reset RST ext_reset_n POLARITY ACTIVE_LOW BlockDiagram :vivado.xilinx.com: FCLK_CLK0 out FCLK_RESET0_N out ext_reset_n in xilinx.com BlockDiagram ps1_imp 1.00.a axi_bram_ctrl ps1_axi_bram_ctrl_0_0 axi_bram_ctrl_bram ps1_axi_bram_ctrl_bram_0 True_Dual_Port_RAM axi_smc ps1_axi_smc_0 1 processing_system7_0 ps1_processing_system7_0_0 0x00100000 0x3FFFFFFF 0xE0000000 0xE0000FFF 0xE0100000 0xE0100FFF TRUE 533.333 0 0.0 0.0 0.0 0.0 0.25 0.25 0.25 0.25 0 0 0 0 0 0 0 0 0 0 0 0 68.4725 71.086 66.794 108.7385 64.1705 63.686 68.46 105.4895 61.0905 61.0905 61.0905 61.0905 160 160 160 160 160 160 160 160 160 160 160 160 -0.007 -0.010 -0.006 -0.048 0.063 0.062 0.065 0.083 667 33.333333 666.666666 10.159 200 20 100 200 100 50 50 50 666.666687 533.333374 10.158730 200.000000 10.000000 10.000000 10.000000 60 60 20.000000 100.000000 10.000000 10.000000 23.8095 23.8095 50 111.111115 50 200.000000 200.000000 100.000000 10.000000 10.000000 10.000000 111.111115 111.111115 111.111115 111.111115 111.111115 111.111115 100000000 10000000 10000000 10000000 0 1 1 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 4 4 4 4 115200 0 12 0 0 12 0 64 64 64 64 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 32 4 4 54 1 0 0 0 1 0 0 0 0 0 0 0 DIRECT 3 1 1 None part0 LVCMOS 3.3V LVCMOS 1.8V 1 0 DDR 3 (Low Voltage) 32 Bit 8 Normal (0-85) MT41J256M16 RE-125 0 0 0 0 0 1 MIO 1 .. 6 1 MIO 1 .. 6 0 x4 0 0 0xFCFFFFFF 0 0 1 MIO 40 .. 45 1 MIO 47 0 0 0 1 MIO 14 .. 15 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 6:2:1 ARM PLL DDR PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL IO PLL External External External CPU_1X CPU_1X CPU_1X CPU_1X CPU_1X CPU_1X CPU_1X DDR PLL IO PLL Active Low Active Low Active Low enabled LVCMOS 3.3V slow LVCMOS 3.3V slow LVCMOS 3.3V slow LVCMOS 3.3V slow LVCMOS 3.3V slow LVCMOS 3.3V slow enabled LVCMOS 3.3V slow enabled LVCMOS 3.3V slow enabled LVCMOS 1.8V slow enabled LVCMOS 1.8V slow enabled LVCMOS 1.8V slow enabled LVCMOS 1.8V slow enabled LVCMOS 1.8V slow enabled LVCMOS 1.8V slow enabled LVCMOS 1.8V slow NA unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#UART 0#UART 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#unassigned#SD 0#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#rx#tx#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#clk#cmd#data[0]#data[1]#data[2]#data[3]#unassigned#cd#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned PRODUCTION 1 1 1 1 1 11 11 0 1 1 1 1 11 11 0 1 1 1 1 11 11 0 1 1 1 1 11 11 0 1 1 1 1 1 11 11 NA NA NA NA NA NA NA clg484 0 rst_ps7_0_100M ps1_rst_ps7_0_100M_0 axi_bram_ctrl_BRAM_PORTA axi_bram_ctrl_BRAM_PORTB processing_system7_0_M_AXI_GP0 axi_smc_M00_AXI processing_system7_0_FCLK_CLK0 processing_system7_0_FCLK_RESET0_N rst_ps7_0_100M_peripheral_aresetn aux_reset_in_0_1 xilinx.com Addressing/processing_system7_0 processing_system7 5.5 M_AXI_GP0 0x40000000 master_id 0 Data 4G 32 SEG_axi_bram_ctrl_Mem0 /axi_bram_ctrl/S_AXI/Mem0 0x40000000 128K