modified src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
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@ -329,7 +329,7 @@ begin
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sm_wavedata <= (others=>'0');
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sm_wavedata_dv <= '0';
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-- Actively read pulse definition RAM and update the variables
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------------------------------------------------------------------------
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-- Main state machine
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@ -367,41 +367,54 @@ begin
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-- Load four addresses from pulse definition RAM into four 32 bits regesters
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------------------------------------------------------------------------
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when S_LOAD =>
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-- TODO: Eric: does is needed here? or should be inside the if-else loops
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-- Load the pulse channel RAM addresses and start the waveform output
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sm_busy <= '1'; -- TODO: Eric: does is needed here? or should be inside the if-else loops
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sm_busy <= '1';
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-- Pipline the pulse definition address
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-- TODO: is it better to make a counter to count the quarter or just mod 4?
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-- TODO: maybe C-slow around the pulse ram to get it down to 1 cycle??
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if (unsigned(ram_pulse_addrb) mod 4 = 0) then
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ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
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sm_state <= S_HOLD; -- stay in the load state to load the next address
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reg_pulse_time <= ram_pulse_doutb;
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pc <= std_logic_vector(unsigned(pc) + C_PC_INCR);
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ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 1);
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sm_state <= S_LOAD;
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-- reg_pulse_time <= ram_pulse_doutb;
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elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then
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ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
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sm_state <= S_HOLD; -- stay in the load state to load the next address
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reg_pulse_sizes <= ram_pulse_doutb;
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ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 2);
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sm_state <= S_LOAD;
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-- reg_pulse_sizes <= ram_pulse_doutb;
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reg_pulse_time <= ram_pulse_doutb;
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elsif (unsigned(ram_pulse_addrb) mod 4 = 2) then
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ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
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sm_state <= S_HOLD; -- stay in the load state to load the next address
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reg_pulse_factors <= ram_pulse_doutb;
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ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 3);
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sm_state <= S_LOAD;
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-- reg_pulse_factors <= ram_pulse_doutb;
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reg_pulse_sizes <= ram_pulse_doutb;
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elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then
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ram_pulse_addrb <= pc;
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sm_state <= S_WAIT; -- go to the wait state to wait for the cnt_time to match the pulse time
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reg_pulse_flattop <= ram_pulse_doutb;
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-- ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 4);
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sm_state <= S_WAIT; -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state
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-- reg_pulse_flattop <= ram_pulse_doutb;
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pc <= std_logic_vector(unsigned(pc) + C_PC_INCR);
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reg_pulse_factors <= ram_pulse_doutb;
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end if;
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------------------------------------------------------------------------
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-- Hold the last pulse definition address and output its data for one more clock cycle
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------------------------------------------------------------------------
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when S_HOLD =>
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sm_state <= S_LOAD;
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-- ------------------------------------------------------------------------
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-- -- Hold the last pulse definition address and output its data for one more clock cycle
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-- ------------------------------------------------------------------------
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-- when S_HOLD =>
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-- sm_state <= S_LOAD;
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------------------------------------------------------------------------
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-- Wait for cnt_time, external input, to match pulse position RAM output
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-- Return to idle state if max time is reached. Output waveform value zero.
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------------------------------------------------------------------------
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when S_WAIT =>
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reg_pulse_flattop <= ram_pulse_doutb;
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-- Start to output wave and increment pulse position RAM address
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if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then
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sm_state <= S_WAVE_UP;
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@ -463,12 +476,13 @@ begin
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-- If the end of the pulse table is reached then go to idle, increment pulse address for the next waveform otherwise
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if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_LEN_PULSE-1, C_BITS_ADDR_PULSE))) then
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ram_pulse_addrb <= (others=>'0');
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pc <= (others=>'0');
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sm_state <= S_IDLE;
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else -- increment pulse address for the next waveform
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-- ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
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ram_pulse_addrb <= pc;
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-- the above line will now happen in the load state
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-- pc <= std_logic_vector(unsigned(pc) + C_PC_INCR);
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sm_state <= S_LOAD;
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end if;
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@ -489,4 +503,5 @@ begin
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end case;
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end if;
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end process;
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end channel;
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@ -1,7 +1,7 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time
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add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr
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@ -13,17 +13,17 @@ add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {279215135747 fs} 0}
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WaveRestoreCursors {{Cursor 1} {277726970613 fs} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 99
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@ -39,4 +39,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits fs
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update
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WaveRestoreZoom {278568705752 fs} {279501294248 fs}
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WaveRestoreZoom {277686713216 fs} {277803286784 fs}
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