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modified src/hdl/modules/qlaser_dacs_pulse_channel.vhdl

This commit is contained in:
Eric Yu 2024-01-04 15:41:32 -08:00
parent 6af4ea22d3
commit e9d3eec1c1
2 changed files with 44 additions and 29 deletions
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61
src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
View File

@ -329,7 +329,7 @@ begin
sm_wavedata <= (others=>'0'); sm_wavedata <= (others=>'0');
sm_wavedata_dv <= '0'; sm_wavedata_dv <= '0';
-- Actively read pulse definition RAM and update the variables
------------------------------------------------------------------------ ------------------------------------------------------------------------
-- Main state machine -- Main state machine
@ -367,41 +367,54 @@ begin
-- Load four addresses from pulse definition RAM into four 32 bits regesters -- Load four addresses from pulse definition RAM into four 32 bits regesters
------------------------------------------------------------------------ ------------------------------------------------------------------------
when S_LOAD => when S_LOAD =>
-- TODO: Eric: does is needed here? or should be inside the if-else loops
-- Load the pulse channel RAM addresses and start the waveform output -- Load the pulse channel RAM addresses and start the waveform output
sm_busy <= '1'; -- TODO: Eric: does is needed here? or should be inside the if-else loops sm_busy <= '1';
-- Pipline the pulse definition address
-- TODO: is it better to make a counter to count the quarter or just mod 4? -- TODO: is it better to make a counter to count the quarter or just mod 4?
-- TODO: maybe C-slow around the pulse ram to get it down to 1 cycle??
if (unsigned(ram_pulse_addrb) mod 4 = 0) then if (unsigned(ram_pulse_addrb) mod 4 = 0) then
ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1); ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 1);
sm_state <= S_HOLD; -- stay in the load state to load the next address sm_state <= S_LOAD;
reg_pulse_time <= ram_pulse_doutb; -- reg_pulse_time <= ram_pulse_doutb;
pc <= std_logic_vector(unsigned(pc) + C_PC_INCR);
elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then
ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1); ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 2);
sm_state <= S_HOLD; -- stay in the load state to load the next address sm_state <= S_LOAD;
reg_pulse_sizes <= ram_pulse_doutb; -- reg_pulse_sizes <= ram_pulse_doutb;
reg_pulse_time <= ram_pulse_doutb;
elsif (unsigned(ram_pulse_addrb) mod 4 = 2) then elsif (unsigned(ram_pulse_addrb) mod 4 = 2) then
ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1); ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 3);
sm_state <= S_HOLD; -- stay in the load state to load the next address sm_state <= S_LOAD;
reg_pulse_factors <= ram_pulse_doutb; -- reg_pulse_factors <= ram_pulse_doutb;
reg_pulse_sizes <= ram_pulse_doutb;
elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then
ram_pulse_addrb <= pc; -- ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 4);
sm_state <= S_WAIT; -- go to the wait state to wait for the cnt_time to match the pulse time sm_state <= S_WAIT; -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state
reg_pulse_flattop <= ram_pulse_doutb; -- reg_pulse_flattop <= ram_pulse_doutb;
pc <= std_logic_vector(unsigned(pc) + C_PC_INCR);
reg_pulse_factors <= ram_pulse_doutb;
end if; end if;
------------------------------------------------------------------------ -- ------------------------------------------------------------------------
-- Hold the last pulse definition address and output its data for one more clock cycle -- -- Hold the last pulse definition address and output its data for one more clock cycle
------------------------------------------------------------------------ -- ------------------------------------------------------------------------
when S_HOLD => -- when S_HOLD =>
sm_state <= S_LOAD; -- sm_state <= S_LOAD;
------------------------------------------------------------------------ ------------------------------------------------------------------------
-- Wait for cnt_time, external input, to match pulse position RAM output -- Wait for cnt_time, external input, to match pulse position RAM output
-- Return to idle state if max time is reached. Output waveform value zero. -- Return to idle state if max time is reached. Output waveform value zero.
------------------------------------------------------------------------ ------------------------------------------------------------------------
when S_WAIT => when S_WAIT =>
reg_pulse_flattop <= ram_pulse_doutb;
-- Start to output wave and increment pulse position RAM address -- Start to output wave and increment pulse position RAM address
if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then
sm_state <= S_WAVE_UP; sm_state <= S_WAVE_UP;
@ -463,12 +476,13 @@ begin
-- If the end of the pulse table is reached then go to idle, increment pulse address for the next waveform otherwise -- If the end of the pulse table is reached then go to idle, increment pulse address for the next waveform otherwise
if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_LEN_PULSE-1, C_BITS_ADDR_PULSE))) then if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_LEN_PULSE-1, C_BITS_ADDR_PULSE))) then
ram_pulse_addrb <= (others=>'0'); ram_pulse_addrb <= (others=>'0');
pc <= (others=>'0');
sm_state <= S_IDLE; sm_state <= S_IDLE;
else -- increment pulse address for the next waveform else -- increment pulse address for the next waveform
-- ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1); ram_pulse_addrb <= pc;
-- the above line will now happen in the load state -- the above line will now happen in the load state
-- pc <= std_logic_vector(unsigned(pc) + C_PC_INCR);
sm_state <= S_LOAD; sm_state <= S_LOAD;
end if; end if;
@ -489,4 +503,5 @@ begin
end case; end case;
end if; end if;
end process; end process;
end channel; end channel;

12
tools/sim/waves_do/pp_sm.do
View File

@ -1,7 +1,7 @@
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time
add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr
@ -13,17 +13,17 @@ add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {279215135747 fs} 0} WaveRestoreCursors {{Cursor 1} {277726970613 fs} 0}
quietly wave cursor active 1 quietly wave cursor active 1
configure wave -namecolwidth 150 configure wave -namecolwidth 150
configure wave -valuecolwidth 99 configure wave -valuecolwidth 99
@ -39,4 +39,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits fs configure wave -timelineunits fs
update update
WaveRestoreZoom {278568705752 fs} {279501294248 fs} WaveRestoreZoom {277686713216 fs} {277803286784 fs}