diff --git a/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl b/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl index c0e27f0..df5fd97 100644 --- a/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl +++ b/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl @@ -279,7 +279,11 @@ begin -- or until the maximum counter time has been reached. ---------------------------------------------------------------- pr_sm : process (reset, clk) + variable v_amp_factor : std_logic_vector(C_BITS_GAIN_FACTOR - 1 downto 0); + variable v_time_factor : std_logic_vector(C_BITS_TIME_FACTOR - 1 downto 0); + -- Temp variables for waveform output + variable v_ram_waveform_doutb_multiplied : std_logic_vector(C_BITS_GAIN_FACTOR + 15 downto 0); begin if (reset = '1') then @@ -420,6 +424,9 @@ begin ------------------------------------------------------------------------ when S_WAVE_UP => -- Check if is end of rise of the waveform, and hold the address + -- first, parse the scale factors from reg_pulse_factors register + v_time_factor := reg_pulse_factors(C_BITS_TIME_FACTOR - 1 downto 0); + v_amp_factor := reg_pulse_factors(C_BITS_GAIN_FACTOR + C_BITS_TIME_FACTOR - 1 downto C_BITS_TIME_FACTOR); -- TODO: convert the numbers below to constaint. right now just make sure I'm not confused if (cnt_wave_len = reg_pulse_sizes(25 downto 16)) then sm_state <= S_WAVE_FLAT; @@ -431,8 +438,9 @@ begin cnt_wave_len <= std_logic_vector(unsigned(cnt_wave_len) + 1); ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1); end if; - - sm_wavedata <= ram_waveform_doutb; + + v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * unsigned(v_amp_factor)); + sm_wavedata <= v_ram_waveform_doutb_multiplied(31 downto 16); sm_wavedata_dv <= '1'; ------------------------------------------------------------------------ @@ -448,7 +456,8 @@ begin else cnt_wave_top <= std_logic_vector(unsigned(cnt_wave_top) + 1); end if; - sm_wavedata <= ram_waveform_doutb; + v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * unsigned(v_amp_factor)); + sm_wavedata <= v_ram_waveform_doutb_multiplied(31 downto 16); sm_wavedata_dv <= '1'; ------------------------------------------------------------------------ @@ -479,7 +488,8 @@ begin cnt_wave_len <= std_logic_vector(unsigned(cnt_wave_len) + 1); ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - 1); end if; - sm_wavedata <= ram_waveform_doutb; + v_ram_waveform_doutb_multiplied := std_logic_vector(unsigned(ram_waveform_doutb) * unsigned(v_amp_factor)); + sm_wavedata <= v_ram_waveform_doutb_multiplied(31 downto 16); sm_wavedata_dv <= '1'; ------------------------------------------------------------------------ diff --git a/src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd b/src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd index 4069325..a31b9ba 100644 --- a/src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd +++ b/src/hdl/pkg/qlaser_dacs_pulse_channel_pkg.vhd @@ -27,5 +27,8 @@ constant C_BITS_ADDR_WAVE : integer := 16; constant C_BITS_ADDR_PULSE : integer := 10; -- Number of bits in address for pulse definition RAM constant C_LEN_PULSE : integer := 2**C_BITS_ADDR_PULSE; -- Numbers of address for pulse definition RAM constant C_PC_INCR : integer := 4; - -- Width of pulse counter increment + -- Width of pulse counter increment + + +constant BIT_FRAC : integer := 4; -- Define the number of fractional bits end package qlaser_dacs_pulse_channel_pkg; \ No newline at end of file diff --git a/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl b/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl index d538235..5fb51a2 100644 --- a/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl +++ b/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl @@ -132,7 +132,6 @@ variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit numb -- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg -- Define the number of fractional bits -constant BIT_FRAC : integer := 4; -- TODO: this should be defined in qlaser_pkg begin -- Convert each field into its std_logic_vector equivalent @@ -148,7 +147,7 @@ begin -- 4 writes. (Address is an integer) cpu_write(clk, ADR_RAM_PULSE+num_entry , x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); cpu_write(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); - cpu_write(clk, ADR_RAM_PULSE+(num_entry+2) , slv_timefactor & slv_gainfactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); + cpu_write(clk, ADR_RAM_PULSE+(num_entry+2) , slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); cpu_write(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata); end; @@ -225,7 +224,6 @@ variable slv_wavetopwidth : std_logic_vector(16 downto 0); -- For 17-bit numb -- constant ADR_PULSE_DEF : integer := to_integer(unsigned(X"?????")); -- Use address of pulse definition RAM from qlaser_pkg -- Define the number of fractional bits -constant BIT_FRAC : integer := 4; -- TODO: this should be defined in qlaser_pkg begin -- Convert each field into its std_logic_vector equivalent @@ -241,7 +239,7 @@ begin -- 4 writes. (Address is an integer) cpu_read(clk, ADR_RAM_PULSE+num_entry, x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); cpu_read(clk, ADR_RAM_PULSE+(num_entry+1), "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); - cpu_read(clk, ADR_RAM_PULSE+(num_entry+2), slv_timefactor & slv_gainfactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); + cpu_read(clk, ADR_RAM_PULSE+(num_entry+2), slv_gainfactor & slv_timefactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); cpu_read(clk, ADR_RAM_PULSE+(num_entry+3), "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv); end; @@ -369,7 +367,7 @@ begin -- TODO: In the real setting should we have the python script to check those parameters to make sure they are valid and non-overlapping? v_pulsetime := v_ndata32 + (NADDR*(1024+32)); v_timefactor := 1.0; - v_gainfactor := 1.0; + v_gainfactor := 2.0; v_wavestartaddr := 0; v_wavesteps := (NADDR+1)*32; v_wavetopwidth := 0; -- TODO: EricToGeoff/Sara: in the real settings do we have a case of no flat top? diff --git a/tools/sim/waves_do/pp_sm_wavetables.do b/tools/sim/waves_do/pp_sm_wavetables.do index 3d25fef..4d54df4 100644 --- a/tools/sim/waves_do/pp_sm_wavetables.do +++ b/tools/sim/waves_do/pp_sm_wavetables.do @@ -1,4 +1,10 @@ onerror {resume} +quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time(31 downto 16)} reg_pulse_time_31_16 +quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time(15 downto 0)} reg_pulse_time_15_0 +quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(31 downto 16)} reg_pulse_factors_31_16 +quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(15 downto 0)} ewg_pulse_factors_15_0 +quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(11 downto 0)} wave_start_addr +quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(25 downto 16)} wave_length quietly WaveActivateNextPane {} 0 add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset @@ -18,10 +24,12 @@ add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb -add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time -add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes -add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors -add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time +add wave -noupdate -radix unsigned -childformat {{/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(15) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(14) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(13) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(12) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(11) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(10) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(9) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(8) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(7) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(6) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(5) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(4) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(3) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(2) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(1) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16(0) -radix unsigned}} -subitemconfig {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(31) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(30) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(29) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(28) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(27) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(26) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(25) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(24) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(23) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(22) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(21) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(20) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(19) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(18) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(17) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(16) {-radix unsigned}} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors_31_16 +add wave -noupdate -label reg_pulse_factors_15_0 -radix unsigned -childformat {{/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(15) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(14) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(13) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(12) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(11) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(10) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(9) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(8) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(7) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(6) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(5) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(4) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(3) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(2) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(1) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0(0) -radix unsigned}} -subitemconfig {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(15) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(14) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(13) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(12) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(11) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(10) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(9) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(8) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(7) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(6) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(5) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(4) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(3) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(2) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(1) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(0) {-radix unsigned}} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ewg_pulse_factors_15_0 +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_start_addr +add wave -noupdate -radix unsigned -childformat {{/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(9) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(8) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(7) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(6) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(5) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(4) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(3) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(2) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(1) -radix unsigned} {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length(0) -radix unsigned}} -subitemconfig {/tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(25) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(24) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(23) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(22) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(21) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(20) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(19) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(18) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(17) {-radix unsigned} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(16) {-radix unsigned}} /tb_cpubus_dacs_pulse_channel/u_dac_pulse/wave_length +add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_wea add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_addra add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_dina @@ -35,7 +43,7 @@ add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tvalid add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tlast add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tready TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {468198791399 fs} 0} +WaveRestoreCursors {{Cursor 1} {739708211940 fs} 0} quietly wave cursor active 1 configure wave -namecolwidth 163 configure wave -valuecolwidth 99 @@ -51,4 +59,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits fs update -WaveRestoreZoom {468135557347 fs} {468308654877 fs} +WaveRestoreZoom {739618451235 fs} {739791548765 fs}