modify tb
This commit is contained in:
parent
1a2db012fe
commit
74d552a323
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@ -7,6 +7,7 @@ use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.qlaser_pkg.all;
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use work.qlaser_dacs_pulse_channel_pkg.all;
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entity qlaser_dacs_pulse_channel is
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port (
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@ -39,26 +40,6 @@ end entity;
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-- Single channel pulse generator with two RAMs
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---------------------------------------------------------------------------
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architecture channel of qlaser_dacs_pulse_channel is
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-- Constants declearations
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constant C_RAM_SELECT : integer := 11; -- Select bit for which RAM for CPU read/write
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-- constant C_NUM_PULSE : integer := 16; -- Number of output data values from pulse RAM (16x24-bit)
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constant C_START_TIME : integer := 24; -- Start time for pulse generation
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constant C_BITS_ADDR_START : integer := 12; -- Number of bits for starting address
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constant C_BITS_ADDR_LENGTH : integer := 10; -- Number of bits for length address used by an edge of a pulse
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constant C_BITS_GAIN_FACTOR : integer := 16; -- Number of bits in gain table
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constant C_BITS_TIME_FACTOR : integer := 16; -- Number of bits in time table
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constant C_BITS_TIME_INT : integer := 14; -- Starting bit for time integer part of the time factor, counting from MSB
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constant C_BITS_TIME_FRAC : integer := 5; -- Starting bit for time fractional part of the time factor, counting from MSB
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constant C_BITS_ADDR_TOP : integer := 17; -- Number of bits for the "flat top", the top of the pulse
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constant C_LENGTH_WAVEFORM : integer := 4096; -- Number of output data values from waveform RAM (4kx16-bit)
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constant C_BITS_ADDR_WAVE : integer := 16; -- Number of bits in address for waveform RAM
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constant C_BITS_ADDR_PULSE : integer := 10; -- Number of bits in address for pulse definition RAM
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constant C_LEN_PULSE : integer := 2**C_BITS_ADDR_PULSE; -- Numbers of address for pulse definition RAM
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constant C_PC_INCR : integer := 4; -- Width of pulse counter increment
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-- Signal declarations for pulse RAM
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signal ram_pulse_we : std_logic_vector( 0 downto 0); -- Write enable for pulse RAM
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signal ram_pulse_addra : std_logic_vector( 9 downto 0); -- Address for pulse RAM
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@ -445,6 +426,7 @@ begin
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-- reset counters for transitions
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cnt_wave_len <= (others=>'0');
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cnt_wave_top <= (others=>'0');
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-- TODO: toSara: do we need to consider the even of no flat top?
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else
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cnt_wave_len <= std_logic_vector(unsigned(cnt_wave_len) + 1);
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ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1);
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@ -510,4 +492,14 @@ begin
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end if;
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end process;
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-- AXI-Stream output.
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-- TBD: This should come from a FIFO
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-- TODO: the bits are not correct, should be top bits (C_BITS_GAIN_FACTOR + 16 downto C_BITS_GAIN_FACTOR), but for now just make it this way so modelsim can simulate
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-- TODO: apply scaling factor to the output
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axis_tdata <= sm_wavedata; -- axi stream output data, this output should be multiplied by the gain factor, then take the top 16 bits
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axis_tvalid <= sm_wavedata_dv; -- axi_stream output data valid
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-- TBD : Generate in state machine?
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axis_tlast <= '0'; -- axi_stream output last
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end channel;
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@ -0,0 +1,31 @@
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----------------------------------------------------------------------------------------
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-- Project : qlaser FPGA
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-- File : qlaser_dacs_pulse_channel.vhd
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-- Description : Pulse Channel package file specifying constants
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-- Author : eyhc
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----------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package qlaser_dacs_pulse_channel_pkg is
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-- Constants declearations
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constant C_RAM_SELECT : integer := 11; -- Select bit for which RAM for CPU read/write
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-- constant C_NUM_PULSE : integer := 16; -- Number of output data values from pulse RAM (16x24-bit)
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constant C_START_TIME : integer := 24; -- Start time for pulse generation
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constant C_BITS_ADDR_START : integer := 12; -- Number of bits for starting address
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constant C_BITS_ADDR_LENGTH : integer := 10; -- Number of bits for length address used by an edge of a pulse
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constant C_BITS_GAIN_FACTOR : integer := 16; -- Number of bits in gain table
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constant C_BITS_TIME_FACTOR : integer := 16; -- Number of bits in time table
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constant C_BITS_TIME_INT : integer := 14; -- Starting bit for time integer part of the time factor, counting from MSB
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constant C_BITS_TIME_FRAC : integer := 5; -- Starting bit for time fractional part of the time factor, counting from MSB
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constant C_BITS_ADDR_TOP : integer := 17; -- Number of bits for the "flat top", the top of the pulse
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constant C_LENGTH_WAVEFORM : integer := 4096; -- Number of output data values from waveform RAM (4kx16-bit)
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constant C_BITS_ADDR_WAVE : integer := 16; -- Number of bits in address for waveform RAM
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constant C_BITS_ADDR_PULSE : integer := 10; -- Number of bits in address for pulse definition RAM
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constant C_LEN_PULSE : integer := 2**C_BITS_ADDR_PULSE; -- Numbers of address for pulse definition RAM
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constant C_PC_INCR : integer := 4;
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-- Width of pulse counter increment
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end package qlaser_dacs_pulse_channel_pkg;
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@ -14,6 +14,7 @@ use ieee.std_logic_1164.all;
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use std.textio.all;
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use work.std_iopak.all;
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use work.qlaser_dacs_pulse_channel_pkg.all;
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entity tb_cpubus_dacs_pulse_channel is
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@ -325,8 +326,17 @@ begin
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-- Reset and drive CPU bus
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-------------------------------------------------------------
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pr_main : process
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variable v_ndata32 : integer := 0;
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variable v_ndata16 : integer := 0;
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variable v_ndata32 : integer := 0;
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variable v_ndata16 : integer := 0;
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-- "global" variables for base definitions of each pulses, all pulses are based on these but scaled/offset a bit
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variable v_pulsetime : integer := 0; -- For 24-bit pulse time
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variable v_timefactor : real := 0.0; -- For 16-bit fixed point timestep
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variable v_gainfactor : real := 0.0; -- For 16-bit fixed point gain
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variable v_wavestartaddr : integer := 0; -- For 12-bit address i.e. 1024 point waveform RAM
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variable v_wavesteps : integer := 0; -- For 10-bit number of steps i.e. 0 = 1 step, X"3FF" = 1024 points
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variable v_wavetopwidth : integer := 0; -- For 17-bit number of clock cycles in top of waveform
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begin
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-- Reset
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reset <= '1';
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@ -356,7 +366,15 @@ begin
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v_ndata32 := 128; -- Time for first pulse
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cpu_print_msg("Load pulse RAM");
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for NADDR in 0 to 255 loop
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cpu_write_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
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-- TODO: In the real setting should we have the python script to check those parameters to make sure they are valid and non-overlapping?
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v_pulsetime := v_ndata32 + (NADDR*(1024+32));
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v_timefactor := 1.0;
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v_gainfactor := 1.0;
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v_wavestartaddr := 0;
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v_wavesteps := (NADDR+1)*32;
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v_wavetopwidth := 0; -- TODO: EricToGeoff/Sara: in the real settings do we have a case of no flat top?
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-- cpu_write_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
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cpu_write_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
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end loop;
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cpu_print_msg("Pulse RAM loaded");
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clk_delay(20);
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@ -368,36 +386,42 @@ begin
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cpu_print_msg("Load waveform RAM");
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v_ndata16 := 1; -- first waveform value
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for NADDR in 0 to 2047 loop
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v_ndata32 := (((v_ndata16+1) * 65536) + v_ndata16);
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v_ndata32 := (((v_ndata16) * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1)); -- Write two 16-bit values with each write
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cpu_write(clk, (ADR_RAM_WAVE + NADDR) , v_ndata32, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
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v_ndata16 := v_ndata16 + 2;
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end loop;
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cpu_print_msg("Waveform RAM loaded");
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clk_delay(20);
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-- ----------------------------------------------------------------
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-- -- Read back Pulse RAM.
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-- -- Comment out if not needed to check CPU R/W
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-- ----------------------------------------------------------------
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-- v_ndata32 := 128; -- Time for first pulse
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-- for NADDR in 0 to 255 loop
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-- v_pulsetime := v_ndata32 + (NADDR*(1024+32));
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-- v_timefactor := 1.0;
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-- v_gainfactor := 1.0;
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-- v_wavestartaddr := 0;
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-- v_wavesteps := NADDR*32;
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-- v_wavetopwidth := 0;
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-- cpu_read_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
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-- end loop;
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-- clk_delay(20);
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----------------------------------------------------------------
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-- Read back Pulse RAM.
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----------------------------------------------------------------
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v_ndata32 := 128; -- Time for first pulse
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for NADDR in 0 to 255 loop
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cpu_read_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
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end loop;
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clk_delay(20);
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-- ----------------------------------------------------------------
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-- -- Read back Waveform RAM
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-- ----------------------------------------------------------------
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-- v_ndata16 := 1; -- first waveform value
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-- for NADDR in 0 to 2047 loop
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-- v_ndata32 := (((v_ndata16) * 2**C_BITS_ADDR_WAVE) + (v_ndata16 - 1));
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-- cpu_read (clk, ADR_RAM_WAVE + NADDR , std_logic_vector(to_unsigned(v_ndata32, 32)) , cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
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-- v_ndata16 := v_ndata16 + 2;
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-- end loop;
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----------------------------------------------------------------
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-- Read back Waveform RAM
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----------------------------------------------------------------
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v_ndata16 := 1; -- first waveform value
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for NADDR in 0 to 2047 loop
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v_ndata32 := (((v_ndata16+1) * 65536) + v_ndata16);
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cpu_read (clk, ADR_RAM_WAVE + NADDR , std_logic_vector(to_unsigned(v_ndata32, 32)) , cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
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v_ndata16 := v_ndata16 + 2;
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end loop;
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-- Done reg write/read check
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cpu_print_msg("RAM readback completed");
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clk_delay(20);
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-- -- Done reg write/read check
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-- cpu_print_msg("RAM readback completed");
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-- clk_delay(20);
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----------------------------------------------------------------
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@ -409,7 +433,7 @@ begin
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start <= '0';
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-- Wait for cnt_time to reach last pulse start time + waveform size
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for NCNT in 1 to (128 + 16*(1024+32)+ 1024) loop
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for NCNT in 1 to (128 + 256*(1024+32)+ 4096) loop -- TODO: EricToGeoff/Sara: in the real settings do we have a constant amount of time or the total time also vary? if so, how much?
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cnt_time <= std_logic_vector(unsigned(cnt_time) + 1);
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clk_delay(0);
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end loop;
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@ -2,7 +2,7 @@ do compile.do
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vsim -voptargs="+acc" -lib work tb_cpubus_dacs_pulse_channel
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do waves_do/pp_sm.do
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do waves_do/pp_sm_wavetables.do
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view wave
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view structure
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@ -0,0 +1,12 @@
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# Current time Mon Jan 15 15:15:21 2024
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# ModelSim - Intel FPGA Edition Stack Trace
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# Program = vsim
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# Id = "10.5b"
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# Version = "2016.10"
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# Date = "Oct 5 2016"
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# Platform = win32pe
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# Signature = a4da31216fa3031746f0a74423efc007
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# 0 0x004d3b4a: '<unknown (@0x4d3b4a)>'
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# End of Stack Trace
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@ -0,0 +1,54 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time
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add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wdata
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wr
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_sel
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_wea
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_addra
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_dina
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_douta
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_addrb
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_doutb
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_wavedata
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_wavedata_dv
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tdata
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tvalid
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tlast
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tready
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {468198791399 fs} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 163
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configure wave -valuecolwidth 99
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits fs
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update
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WaveRestoreZoom {468135557347 fs} {468308654877 fs}
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