add state machine
This commit is contained in:
parent
c1daca2a0f
commit
6af4ea22d3
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@ -2,6 +2,7 @@
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*.jou
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*.ini
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*.wlf
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wlft*
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work
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transcript
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prj
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@ -35,13 +35,13 @@ port (
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);
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end entity;
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----------------------------------------------------------------
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---------------------------------------------------------------------------
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-- Single channel pulse generator with two RAMs
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----------------------------------------------------------------
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---------------------------------------------------------------------------
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architecture channel of qlaser_dacs_pulse_channel is
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-- Constants declearations
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constant C_RAM_SELECT : integer := 11; -- Select bit for which RAM for CPU read/write
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constant C_NUM_PULSE : integer := 16; -- Number of output data values from pulse RAM (16x24-bit)
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-- constant C_NUM_PULSE : integer := 16; -- Number of output data values from pulse RAM (16x24-bit)
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constant C_START_TIME : integer := 24; -- Start time for pulse generation
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constant C_BITS_ADDR_START : integer := 12; -- Number of bits for starting address
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@ -52,9 +52,11 @@ constant C_BITS_TIME_INT : integer := 14; -- Starting bit fo
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constant C_BITS_TIME_FRAC : integer := 5; -- Starting bit for time fractional part of the time factor, counting from MSB
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constant C_BITS_ADDR_TOP : integer := 17; -- Number of bits for the "flat top", the top of the pulse
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constant C_LENGTH_WAVEFORM : integer := 1024; -- Number of output data values from waveform RAM (1024x16-bit)
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constant C_BITS_ADDR_WAVE : integer := 10; -- Number of bits in address for waveform RAM
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constant C_LENGTH_WAVEFORM : integer := 4096; -- Number of output data values from waveform RAM (4kx16-bit)
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constant C_BITS_ADDR_WAVE : integer := 16; -- Number of bits in address for waveform RAM
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constant C_BITS_ADDR_PULSE : integer := 10; -- Number of bits in address for pulse definition RAM
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constant C_LEN_PULSE : integer := 2**C_BITS_ADDR_PULSE; -- Numbers of address for pulse definition RAM
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constant C_PC_INCR : integer := 4; -- Width of pulse counter increment
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-- Signal declarations for pulse RAM
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@ -74,10 +76,13 @@ signal ram_waveform_addrb : std_logic_vector(11 downto 0); -- Address for wav
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signal ram_waveform_doutb : std_logic_vector(15 downto 0); -- Data out from waveform RAM
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-- State variable type declaration for main state machine
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-- TODO: add a fetch state to get four address from pd ram?
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type t_sm_state is (
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S_RESET, -- Wait for 'enable'. Stay here until JESD interface is up and running,
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S_IDLE, -- Wait for 'start'
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S_WAIT, -- Wait for cnt_time, external input, to match pulse position RAM output
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S_LOAD, -- Load the pulse channel RAM addresses and start the waveform output
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S_HOLD, -- Hold the last pulse definition address and output its data
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S_WAVE_UP, -- Output the rising edge of a waveform
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S_WAVE_FLAT,-- Output the flat top part of a waveform
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S_WAVE_DOWN -- Output the falling edge of a waveform
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@ -86,6 +91,8 @@ signal sm_state : t_sm_state;
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signal sm_wavedata : std_logic_vector(15 downto 0); -- Waveform RAM data
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signal sm_wavedata_dv : std_logic; -- Signal to indicate that waveform RAM data is valid
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signal sm_busy : std_logic; -- Signal to indicate that s.m. is not idle
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signal cnt_wave_len : std_logic_vector(C_BITS_ADDR_LENGTH - 1 downto 0); -- Counter used for incremnet/decrement wave table addresses
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signal cnt_wave_top : std_logic_vector(C_BITS_ADDR_TOP - 1 downto 0); -- Counter for the flat top of the waveform
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-- Misc signals
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signal cpu_rdata_dv_e1 : std_logic;
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@ -93,6 +100,21 @@ signal cpu_rdata_dv_e2 : std_logic;
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signal cpu_rdata_ramsel_d1 : std_logic;
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signal cpu_rdata_ramsel_d2 : std_logic;
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signal pc : std_logic_vector(C_BITS_ADDR_PULSE - 1 downto 0); -- pulse counter, used to count the number of pulses generated
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----------------------------------------------------------------
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-- Assign values from the pulse definition ram to regfiles (?) with the following:
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-- 1. Start time 24 bits. [23:0]
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-- 2. Wave start addr 12 bit at [11:0]
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-- Wave length 10-bit at [25:16]
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-- 3. Scale factors 16, 16. [31:16] [15:0]
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-- 4. Flat-top 17-bit. [16:0]
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----------------------------------------------------------------
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signal reg_pulse_time : std_logic_vector(31 downto 0); -- first register which stores the pulse's start time
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signal reg_pulse_sizes : std_logic_vector(31 downto 0); -- second register which stores the pulse's length, the bit width should increase with the amount of addresses the wavetable has, and its start address
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signal reg_pulse_factors : std_logic_vector(31 downto 0); -- third register which stores the pulse's amplitude and time scale factors
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signal reg_pulse_flattop : std_logic_vector(31 downto 0); -- fourth register which stores the pulse's flat top value
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-- Pipeline delays
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signal start_d1 : std_logic;
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signal enable_d1 : std_logic;
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@ -264,4 +286,207 @@ begin
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end if;
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end process;
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----------------------------------------------------------------
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-- State machine:
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-- Compares cnt_time input against current output from pulse position RAM.
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-- When values match iti incremnts the pulse postion RAM address to
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-- retrieve the next pulse position and also starts reading the
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-- entire waveform table, one value every clock cycle, until it reaches the end.
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-- Once the pulse is complete it waits for the next cnt_time match.
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-- Repeat until all pulse position RAM times have triggered a pulse output
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-- or until the maximum counter time has been reached.
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----------------------------------------------------------------
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pr_sm : process (reset, clk)
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begin
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if (reset = '1') then
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sm_state <= S_IDLE; -- TODO: Eric: Should this be S_RESET since we reset the JEDS interface as well?
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ram_pulse_addrb <= (others=>'0');
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ram_waveform_addrb <= (others=>'0');
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sm_wavedata <= (others=>'0');
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sm_wavedata_dv <= '0';
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sm_busy <= '0';
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reg_pulse_time <= (others=>'0');
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reg_pulse_sizes <= (others=>'0');
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reg_pulse_factors <= (others=>'0');
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reg_pulse_flattop <= (others=>'0');
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pc <= (others=>'0');
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cnt_wave_len <= (others=>'0');
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cnt_wave_top <= (others=>'0');
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elsif rising_edge(clk) then
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-- Pipeline delays to use for rising edge detection
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enable_d1 <= enable;
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start_d1 <= start;
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-- Default
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sm_wavedata <= (others=>'0');
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sm_wavedata_dv <= '0';
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-- Actively read pulse definition RAM and update the variables
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------------------------------------------------------------------------
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-- Main state machine
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------------------------------------------------------------------------
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case sm_state is
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------------------------------------------------------------------------
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-- Wait for rising edge of enable
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-- This is set when the JESD interface is aligned and functional.
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-- Send a zero value to initialize the DAC then go to idle.
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------------------------------------------------------------------------
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when S_RESET =>
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if (enable = '1') and (enable_d1 = '0') then
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sm_wavedata <= (others=>'0');
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sm_wavedata_dv <= '1';
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sm_state <= S_IDLE;
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end if;
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sm_busy <= '0';
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------------------------------------------------------------------------
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-- Wait for rising edge of 'start'.
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-- No data output.
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------------------------------------------------------------------------
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when S_IDLE =>
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if (start = '1') and (start_d1 = '0') then
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sm_state <= S_LOAD;
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sm_busy <= '1';
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else
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sm_busy <= '0';
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end if;
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------------------------------------------------------------------------
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-- Load four addresses from pulse definition RAM into four 32 bits regesters
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------------------------------------------------------------------------
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when S_LOAD =>
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-- Load the pulse channel RAM addresses and start the waveform output
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sm_busy <= '1'; -- TODO: Eric: does is needed here? or should be inside the if-else loops
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-- TODO: is it better to make a counter to count the quarter or just mod 4?
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if (unsigned(ram_pulse_addrb) mod 4 = 0) then
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ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
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sm_state <= S_HOLD; -- stay in the load state to load the next address
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reg_pulse_time <= ram_pulse_doutb;
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pc <= std_logic_vector(unsigned(pc) + C_PC_INCR);
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elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then
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ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
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sm_state <= S_HOLD; -- stay in the load state to load the next address
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reg_pulse_sizes <= ram_pulse_doutb;
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elsif (unsigned(ram_pulse_addrb) mod 4 = 2) then
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ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
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sm_state <= S_HOLD; -- stay in the load state to load the next address
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reg_pulse_factors <= ram_pulse_doutb;
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elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then
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ram_pulse_addrb <= pc;
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sm_state <= S_WAIT; -- go to the wait state to wait for the cnt_time to match the pulse time
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reg_pulse_flattop <= ram_pulse_doutb;
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end if;
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------------------------------------------------------------------------
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-- Hold the last pulse definition address and output its data for one more clock cycle
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------------------------------------------------------------------------
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when S_HOLD =>
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sm_state <= S_LOAD;
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------------------------------------------------------------------------
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-- Wait for cnt_time, external input, to match pulse position RAM output
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-- Return to idle state if max time is reached. Output waveform value zero.
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------------------------------------------------------------------------
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when S_WAIT =>
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-- Start to output wave and increment pulse position RAM address
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if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then
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sm_state <= S_WAVE_UP;
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-- set the wavetable's address to the starting address defined from the pulse ram
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ram_waveform_addrb <= reg_pulse_sizes(C_BITS_ADDR_START - 1 downto 0);
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-- reset the wave lenth counter
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cnt_wave_len <= (others=>'0');
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elsif (cnt_time = X"FFFFFF") then
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sm_state <= S_IDLE;
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end if;
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------------------------------------------------------------------------
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-- Output the raising edge of a waveform
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-- Hold the last address when complete
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------------------------------------------------------------------------
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when S_WAVE_UP =>
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-- Check if is end of rise of the waveform, and hold the address
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-- TODO: convert the numbers below to constaint. right now just make sure I'm not confused
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if (cnt_wave_len = reg_pulse_sizes(25 downto 16)) then
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sm_state <= S_WAVE_FLAT;
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-- reset counters for transitions
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cnt_wave_len <= (others=>'0');
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cnt_wave_top <= (others=>'0');
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else
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cnt_wave_len <= std_logic_vector(unsigned(cnt_wave_len) + 1);
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ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) + 1);
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end if;
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sm_wavedata <= ram_waveform_doutb;
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sm_wavedata_dv <= '1';
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------------------------------------------------------------------------
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-- Hold the last address and output its data
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-- decrement from this address when finished waiting
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------------------------------------------------------------------------
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when S_WAVE_FLAT =>
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-- count the 17-bit flat top, if the counter reaches the flat top value, then go to the next state
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if (cnt_wave_top = reg_pulse_flattop(C_BITS_ADDR_TOP - 1 downto 0)) then
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sm_state <= S_WAVE_DOWN;
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-- reset the counter for the next transition
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cnt_wave_top <= (others=>'0');
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else
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cnt_wave_top <= std_logic_vector(unsigned(cnt_wave_top) + 1);
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end if;
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sm_wavedata <= ram_waveform_doutb;
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sm_wavedata_dv <= '1';
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------------------------------------------------------------------------
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-- Output the falling edge of a waveform
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-- Hold the start address when complete
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------------------------------------------------------------------------
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when S_WAVE_DOWN =>
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-- End of waveform?
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-- TODO: convert the numbers below to constaint. right now just make sure I'm not confused
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if (cnt_wave_len = reg_pulse_sizes(25 downto 16)) then
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-- If the end of the pulse table is reached then go to idle, increment pulse address for the next waveform otherwise
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if (ram_pulse_addrb = std_logic_vector(to_unsigned(C_LEN_PULSE-1, C_BITS_ADDR_PULSE))) then
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ram_pulse_addrb <= (others=>'0');
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sm_state <= S_IDLE;
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else -- increment pulse address for the next waveform
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-- ram_pulse_addrb <= std_logic_vector(unsigned(ram_pulse_addrb) + 1);
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-- the above line will now happen in the load state
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sm_state <= S_LOAD;
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end if;
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-- Output waveform from RAM with decremented address
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else
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cnt_wave_len <= std_logic_vector(unsigned(cnt_wave_len) + 1);
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ram_waveform_addrb <= std_logic_vector(unsigned(ram_waveform_addrb) - 1);
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end if;
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sm_wavedata <= ram_waveform_doutb;
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sm_wavedata_dv <= '1';
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------------------------------------------------------------------------
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-- Default
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------------------------------------------------------------------------
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when others =>
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sm_state <= S_IDLE;
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end case;
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end if;
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end process;
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end channel;
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@ -361,19 +361,19 @@ begin
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cpu_print_msg("Pulse RAM loaded");
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clk_delay(20);
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-- ----------------------------------------------------------------
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-- -- Load waveform RAM with a simple ramp
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-- -- Write two 16-bit values with each write
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-- ----------------------------------------------------------------
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-- cpu_print_msg("Load waveform RAM");
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-- v_ndata16 := 1; -- first waveform value
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-- for NADDR in 0 to 511 loop
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-- v_ndata32 := (((v_ndata16+1) * 65536) + v_ndata16);
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-- cpu_write(clk, (ADR_RAM_WAVE + NADDR) , v_ndata32, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
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-- v_ndata16 := v_ndata16 + 2;
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-- end loop;
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-- cpu_print_msg("Waveform RAM loaded");
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-- clk_delay(20);
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----------------------------------------------------------------
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-- Load waveform RAM with a simple ramp
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-- Write two 16-bit values with each write
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----------------------------------------------------------------
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cpu_print_msg("Load waveform RAM");
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v_ndata16 := 1; -- first waveform value
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for NADDR in 0 to 2047 loop
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v_ndata32 := (((v_ndata16+1) * 65536) + v_ndata16);
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cpu_write(clk, (ADR_RAM_WAVE + NADDR) , v_ndata32, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
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v_ndata16 := v_ndata16 + 2;
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end loop;
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cpu_print_msg("Waveform RAM loaded");
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clk_delay(20);
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----------------------------------------------------------------
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@ -385,34 +385,34 @@ begin
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end loop;
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clk_delay(20);
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-- ----------------------------------------------------------------
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-- -- Read back Waveform RAM
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-- ----------------------------------------------------------------
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-- v_ndata16 := 1; -- first waveform value
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-- for NADDR in 0 to 511 loop
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-- v_ndata32 := (((v_ndata16+1) * 65536) + v_ndata16);
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-- cpu_read (clk, ADR_RAM_WAVE + NADDR , std_logic_vector(to_unsigned(v_ndata32, 32)) , cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
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-- v_ndata16 := v_ndata16 + 2;
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-- end loop;
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----------------------------------------------------------------
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-- Read back Waveform RAM
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----------------------------------------------------------------
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v_ndata16 := 1; -- first waveform value
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for NADDR in 0 to 2047 loop
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v_ndata32 := (((v_ndata16+1) * 65536) + v_ndata16);
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cpu_read (clk, ADR_RAM_WAVE + NADDR , std_logic_vector(to_unsigned(v_ndata32, 32)) , cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
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v_ndata16 := v_ndata16 + 2;
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end loop;
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-- -- Done reg write/read check
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-- cpu_print_msg("RAM readback completed");
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-- clk_delay(20);
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-- Done reg write/read check
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cpu_print_msg("RAM readback completed");
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clk_delay(20);
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-- ----------------------------------------------------------------
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-- -- Start the pulse outputs
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-- ----------------------------------------------------------------
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-- clk_delay(5);
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-- start <= '1';
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-- clk_delay(5);
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-- start <= '0';
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----------------------------------------------------------------
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-- Start the pulse outputs
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----------------------------------------------------------------
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clk_delay(5);
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start <= '1';
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clk_delay(5);
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start <= '0';
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-- -- Wait for cnt_time to reach last pulse start time + waveform size
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-- for NCNT in 1 to (128 + 16*(1024+32)+ 1024) loop
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-- cnt_time <= std_logic_vector(unsigned(cnt_time) + 1);
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-- clk_delay(0);
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-- end loop;
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-- Wait for cnt_time to reach last pulse start time + waveform size
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for NCNT in 1 to (128 + 16*(1024+32)+ 1024) loop
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cnt_time <= std_logic_vector(unsigned(cnt_time) + 1);
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clk_delay(0);
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end loop;
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wait for 10 us;
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@ -2,7 +2,7 @@ do compile.do
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vsim -voptargs="+acc" -lib work tb_cpubus_dacs_pulse_channel
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do waves_do/pp_rw_cpu.do
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do waves_do/pp_sm.do
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view wave
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view structure
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@ -0,0 +1,42 @@
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/busy
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cnt_time
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add wave -noupdate -radix binary /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_addr
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wdata
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_wr
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_sel
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add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata
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add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/cpu_rdata_dv
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add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addra
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||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_dina
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_douta
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_addrb
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_state
|
||||
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_we
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_pulse_doutb
|
||||
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/pc
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors
|
||||
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_flattop
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 1} {279215135747 fs} 0}
|
||||
quietly wave cursor active 1
|
||||
configure wave -namecolwidth 150
|
||||
configure wave -valuecolwidth 99
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits fs
|
||||
update
|
||||
WaveRestoreZoom {278568705752 fs} {279501294248 fs}
|
||||
Loading…
Reference in New Issue