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PulseChannelUnVerified
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modified tb

This commit is contained in:
Eric Yu 2024-01-23 21:12:52 -08:00
parent a0c05457c9
commit 5ecd4eaf5a
5 changed files with 8 additions and 14 deletions
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1
.gitignore vendored
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@ -2,6 +2,7 @@
*.jou
*.ini
*.wlf
*.vstf
wlft*
work
transcript

3
.vscode/settings.json vendored
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@ -1,3 +0,0 @@
{
"digital-ide.dont-show-again.propose.issue": true
}

6
src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl
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@ -367,10 +367,10 @@ begin
-- TODO: In the real setting should we have the python script to check those parameters to make sure they are valid and non-overlapping?
v_pulsetime := v_ndata32 + (NADDR*(1024+32));
v_timefactor := 1.0;
v_gainfactor := 0.5;
v_gainfactor := 1.0/real(NADDR + 1);
v_wavestartaddr := 0; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right?
v_wavesteps := NADDR + 1;
v_wavetopwidth := 1;
v_wavesteps := NADDR*32;
v_wavetopwidth := NADDR;
-- cpu_write_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
cpu_write_pulsedef(clk, NADDR*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
end loop;

2
tools/sim/compile.bat
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@ -1,2 +1,2 @@
echo off
vsim -c -quiet -do compile.do
modelsim -c -quiet -do compile.do

10
tools/sim/waves_do/pp_sm_wavetables.do
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@ -1,10 +1,6 @@
onerror {resume}
quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time(31 downto 16)} reg_pulse_time_31_16
quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_time(15 downto 0)} reg_pulse_time_15_0
quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(31 downto 16)} reg_pulse_factors_31_16
quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_factors(15 downto 0)} ewg_pulse_factors_15_0
quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(11 downto 0)} wave_start_addr
quietly virtual signal -install /tb_cpubus_dacs_pulse_channel/u_dac_pulse { /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reg_pulse_sizes(25 downto 16)} wave_length
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/clk
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/reset
@ -38,12 +34,12 @@ add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/ram_waveform_doutb
add wave -noupdate -radix hexadecimal /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_wavedata
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/sm_wavedata_dv
add wave -noupdate -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tdata
add wave -noupdate -format Analog-Step -height 74 -max 204.0 -radix unsigned /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tdata
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tvalid
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tlast
add wave -noupdate /tb_cpubus_dacs_pulse_channel/u_dac_pulse/axis_tready
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {104895000000 fs} 0}
WaveRestoreCursors {{Cursor 1} {2789695000000 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 163
configure wave -valuecolwidth 99
@ -59,4 +55,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits fs
update
WaveRestoreZoom {104768451235 fs} {104941548765 fs}
WaveRestoreZoom {2786977182418 fs} {2792819201950 fs}