diff --git a/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl b/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
index e57c63d..74c7772 100644
--- a/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
+++ b/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
@@ -88,7 +88,6 @@ signal sm_wavedata_dv : std_logic; -- Signal to indic
signal sm_busy : std_logic; -- Signal to indicate that s.m. is not idle
-- Misc signals
-signal ram_pulse_douta_d1 : std_logic_vector(31 downto 0); -- Delay distrib RAM output to match pipeline of Block RAM
signal cpu_rdata_dv_e1 : std_logic;
signal cpu_rdata_dv_e2 : std_logic;
signal cpu_rdata_ramsel_d1 : std_logic;
@@ -193,7 +192,7 @@ begin
ram_pulse_addra <= cpu_addr(9 downto 0);
ram_pulse_dina <= cpu_wdata;
- ram_pulse_we <= std_logic_vector(to_unsigned(1, ram_pulse_we'length));
+ ram_pulse_we(0) <= '1';
ram_waveform_wea <= (others=>'0');
ram_waveform_addra <= (others=>'0');
ram_waveform_dina <= (others=>'0');
@@ -214,18 +213,17 @@ begin
if (cpu_addr(C_RAM_SELECT) = '1') then -- Waveform
ram_pulse_addra <= (others=>'0');
ram_waveform_addra <= cpu_addr(10 downto 0);
- else -- Pulse
+ else -- Pulse
ram_pulse_addra <= cpu_addr(9 downto 0);
- ram_pulse_douta_d1 <= ram_pulse_douta; -- Delay distrib RAM output to match pipeline of Block RAM
ram_waveform_addra <= (others=>'0');
end if;
ram_pulse_we <= (others=>'0');
ram_waveform_wea(0) <= '0';
- cpu_rdata_dv_e2 <= '1'; -- DV for cycle, when RAM output occurs
- cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
- cpu_rdata_ramsel_d1 <= cpu_addr(9); -- Save the select bit one cycle later
+ cpu_rdata_dv_e2 <= '1'; -- DV for cycle, when RAM output occurs
+ cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
+ cpu_rdata_ramsel_d1 <= cpu_addr(C_RAM_SELECT); -- Save the select bit one cycle later
cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1;
else
@@ -235,7 +233,7 @@ begin
ram_waveform_wea(0) <= '0';
cpu_rdata_dv_e2 <= '0';
- cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
+ cpu_rdata_dv_e1 <= cpu_rdata_dv_e2; -- DV for next cycle
cpu_rdata_ramsel_d1 <= '0';
cpu_rdata_ramsel_d2 <= cpu_rdata_ramsel_d1;
@@ -255,7 +253,7 @@ begin
cpu_rdata <= ram_waveform_douta;
elsif (cpu_rdata_ramsel_d2 = '0') then
- cpu_rdata <= ram_pulse_douta_d1;
+ cpu_rdata <= ram_pulse_douta;
end if;
else
diff --git a/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl b/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl
index 8e3df89..94df9ef 100644
--- a/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl
+++ b/src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl
@@ -107,7 +107,7 @@ procedure cpu_write_pulsedef(
constant num_entry : in integer;
- -- TODO: Partial ? list of parameters
+ -- TODO: Partial ? list of parameters, there could be more if need more features
constant pulsetime : in integer; -- Pulse time in clock cycles
constant timefactor : in real; -- Fixed point time scale factor
constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000"
@@ -200,7 +200,7 @@ procedure cpu_read_pulsedef(
constant num_entry : in integer;
- -- TODO: Partial ? list of parameters
+ -- TODO: Partial ? list of parameters, there could be more if need more features
constant pulsetime : in integer; -- Pulse time in clock cycles
constant timefactor : in real; -- Fixed point time scale factor
constant gainfactor : in real; -- Fixed point gain value. Max value 1.0 is hex X"8000". Gain 0.5 is therefore X"4000"
@@ -238,10 +238,10 @@ begin
--etc, etc.
-- 4 writes. (Address is an integer)
- -- cpu_read(clk, ADR_RAM_PULSE+num_entry, x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
- -- cpu_read(clk, ADR_RAM_PULSE+(num_entry+1) , "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
- -- cpu_read(clk, ADR_RAM_PULSE+(num_entry+2) , slv_timefactor & slv_gainfactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
- -- cpu_read(clk, ADR_RAM_PULSE+(num_entry+3) , "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
+ cpu_read(clk, ADR_RAM_PULSE+num_entry, x"00" & slv_pulsetime, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
+ cpu_read(clk, ADR_RAM_PULSE+(num_entry+1), "00" & x"00" & slv_wavesteps & slv_wavestartaddr, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
+ cpu_read(clk, ADR_RAM_PULSE+(num_entry+2), slv_timefactor & slv_gainfactor, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
+ cpu_read(clk, ADR_RAM_PULSE+(num_entry+3), "0000000" & x"00" & slv_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata, cpu_rdata, cpu_rdata_dv);
end;
@@ -356,7 +356,7 @@ begin
v_ndata32 := 128; -- Time for first pulse
cpu_print_msg("Load pulse RAM");
for NADDR in 0 to 255 loop
- cpu_write_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 512, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
+ cpu_write_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
end loop;
cpu_print_msg("Pulse RAM loaded");
clk_delay(20);
@@ -381,7 +381,7 @@ begin
----------------------------------------------------------------
v_ndata32 := 128; -- Time for first pulse
for NADDR in 0 to 255 loop
- cpu_read_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 512, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
+ cpu_read_pulsedef(clk, NADDR*4, v_ndata32 + (NADDR*(1024+32)), 1.0, 1.0, 0, NADDR*32, 128, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
end loop;
clk_delay(20);
@@ -395,24 +395,24 @@ begin
-- v_ndata16 := v_ndata16 + 2;
-- end loop;
- -- Done reg write/read check
- cpu_print_msg("RAM readback completed");
- clk_delay(20);
+ -- -- Done reg write/read check
+ -- cpu_print_msg("RAM readback completed");
+ -- clk_delay(20);
- ----------------------------------------------------------------
- -- Start the pulse outputs
- ----------------------------------------------------------------
- clk_delay(5);
- start <= '1';
- clk_delay(5);
- start <= '0';
+ -- ----------------------------------------------------------------
+ -- -- Start the pulse outputs
+ -- ----------------------------------------------------------------
+ -- clk_delay(5);
+ -- start <= '1';
+ -- clk_delay(5);
+ -- start <= '0';
- -- Wait for cnt_time to reach last pulse start time + waveform size
- for NCNT in 1 to (128 + 16*(1024+32)+ 1024) loop
- cnt_time <= std_logic_vector(unsigned(cnt_time) + 1);
- clk_delay(0);
- end loop;
+ -- -- Wait for cnt_time to reach last pulse start time + waveform size
+ -- for NCNT in 1 to (128 + 16*(1024+32)+ 1024) loop
+ -- cnt_time <= std_logic_vector(unsigned(cnt_time) + 1);
+ -- clk_delay(0);
+ -- end loop;
wait for 10 us;
diff --git a/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci b/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci
index 3ce1f9d..ae18318 100644
--- a/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci
+++ b/tools/xilinx-zcu/bram_pulse_definition/bram_pulse_definition.xci
@@ -257,7 +257,7 @@
../../../prj/zcu_pulse_channel.gen/sources_1/ip/bram_pulse_definition
.
- 2022.1
+ 2022.1.2
OUT_OF_CONTEXT
diff --git a/tools/xilinx-zcu/bram_pulseposition/bram_pulseposition.xci b/tools/xilinx-zcu/bram_pulseposition/bram_pulseposition.xci
index 0a7f774..e0fd654 100644
--- a/tools/xilinx-zcu/bram_pulseposition/bram_pulseposition.xci
+++ b/tools/xilinx-zcu/bram_pulseposition/bram_pulseposition.xci
@@ -86,7 +86,7 @@
../../../prj/zcu_pulse_channel.gen/sources_1/ip/bram_pulseposition
.
- 2022.1
+ 2022.1.2
OUT_OF_CONTEXT
diff --git a/tools/xilinx-zcu/bram_waveform/bram_waveform.xci b/tools/xilinx-zcu/bram_waveform/bram_waveform.xci
index 96cfc54..86b9ffa 100644
--- a/tools/xilinx-zcu/bram_waveform/bram_waveform.xci
+++ b/tools/xilinx-zcu/bram_waveform/bram_waveform.xci
@@ -257,7 +257,7 @@
../../../prj/zcu_pulse_channel.gen/sources_1/ip/bram_waveform
.
- 2022.1
+ 2022.1.2
OUT_OF_CONTEXT
diff --git a/tools/xilinx-zcu/fifo_data_to_stream/fifo_data_to_stream.xci b/tools/xilinx-zcu/fifo_data_to_stream/fifo_data_to_stream.xci
index 28c743e..19bf8f7 100644
--- a/tools/xilinx-zcu/fifo_data_to_stream/fifo_data_to_stream.xci
+++ b/tools/xilinx-zcu/fifo_data_to_stream/fifo_data_to_stream.xci
@@ -524,7 +524,7 @@
../../../prj/zcu_pulse_channel.gen/sources_1/ip/fifo_data_to_stream
.
- 2022.1
+ 2022.1.2
OUT_OF_CONTEXT