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PulseChannelUnVerified
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modify tb

This commit is contained in:
Eric Yu 2024-01-29 17:08:07 -08:00
parent e41460c843
commit 334aa10655
1 changed files with 4 additions and 4 deletions
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8
src/hdl/tb/tb_cpubus_dacs_pulse_channel.vhdl
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@ -367,7 +367,7 @@ begin
cpu_print_msg("Load pulse RAM");
-- for NADDR in 0 to 255 loop
-- -- TODO: In the real setting should we have the python script to check those parameters to make sure they are valid and non-overlapping?
-- v_pulsetime := v_ndata32 + (NADDR*(1024+32)); -- todo: what is this math doing?
-- v_pulsetime := v_ndata32 + (NADDR*(4096+32)); -- todo: what is this math doing?
-- v_timefactor := 1.0;
-- v_gainfactor := 1.0/real(NADDR + 1);
-- v_wavestartaddr := 0; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right?
@ -380,7 +380,7 @@ begin
----------------------------------------------------------------
-- Load pulse RAM with a series of pulse start times MANUALLY
---------------------------------------------------------------
v_pulseaddr := 1;
v_pulseaddr := 0;
v_pulsetime := 7;
v_timefactor := 1.0;
v_gainfactor := 1.0;
@ -390,8 +390,8 @@ begin
cpu_write_pulsedef(clk, v_pulseaddr*4, v_pulsetime, v_timefactor, v_gainfactor, v_wavestartaddr, v_wavesteps, v_wavetopwidth, cpu_sel, cpu_wr, cpu_addr, cpu_wdata);
v_pulseaddr := 32;
v_pulsetime := 21;
v_pulseaddr := 1;
v_pulsetime := 69;
v_timefactor := 1.0;
v_gainfactor := 1.0;
v_wavestartaddr := 4; -- TODO: EricToGeoff/Sara: I assume we want starting address of each wave to be different and non-overlapping, right?