modified src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
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@ -377,12 +377,14 @@ begin
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if (unsigned(ram_pulse_addrb) mod 4 = 0) then
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ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 1);
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sm_state <= S_LOAD;
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-- first quarter of the pulse definition, no register is loaded
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-- reg_pulse_time <= ram_pulse_doutb;
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elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then
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ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 2);
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sm_state <= S_LOAD;
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-- reg_pulse_sizes <= ram_pulse_doutb;
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-- second quarter of the pulse definition, the start time is loaded
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reg_pulse_time <= ram_pulse_doutb;
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@ -390,14 +392,17 @@ begin
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ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 3);
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sm_state <= S_LOAD;
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-- reg_pulse_factors <= ram_pulse_doutb;
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-- third quarter of the pulse definition, the length and start address of the wavetable are loaded
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reg_pulse_sizes <= ram_pulse_doutb;
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elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then
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-- ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 4);
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sm_state <= S_WAIT; -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state
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-- hold the last pulse definition address as it will be used in the next state
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-- reg_pulse_flattop <= ram_pulse_doutb;
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pc <= std_logic_vector(unsigned(pc) + C_PC_INCR);
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pc <= std_logic_vector(unsigned(pc) + C_PC_INCR); -- incremnet the pulse counter and start waiting to output the wave
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-- forth quarter of the pulse definition, the scale factors are loaded
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reg_pulse_factors <= ram_pulse_doutb;
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@ -414,6 +419,7 @@ begin
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-- Return to idle state if max time is reached. Output waveform value zero.
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------------------------------------------------------------------------
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when S_WAIT =>
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-- read the last word of the pulse definition, the flat top value
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reg_pulse_flattop <= ram_pulse_doutb;
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-- Start to output wave and increment pulse position RAM address
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if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then
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