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modified src/hdl/modules/qlaser_dacs_pulse_channel.vhdl

This commit is contained in:
Eric Yu 2024-01-06 00:11:26 -08:00
parent e9d3eec1c1
commit 1a2db012fe
1 changed files with 7 additions and 1 deletions
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8
src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
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@ -377,12 +377,14 @@ begin
if (unsigned(ram_pulse_addrb) mod 4 = 0) then if (unsigned(ram_pulse_addrb) mod 4 = 0) then
ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 1); ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 1);
sm_state <= S_LOAD; sm_state <= S_LOAD;
-- first quarter of the pulse definition, no register is loaded
-- reg_pulse_time <= ram_pulse_doutb; -- reg_pulse_time <= ram_pulse_doutb;
elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then
ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 2); ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 2);
sm_state <= S_LOAD; sm_state <= S_LOAD;
-- reg_pulse_sizes <= ram_pulse_doutb; -- reg_pulse_sizes <= ram_pulse_doutb;
-- second quarter of the pulse definition, the start time is loaded
reg_pulse_time <= ram_pulse_doutb; reg_pulse_time <= ram_pulse_doutb;
@ -390,14 +392,17 @@ begin
ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 3); ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 3);
sm_state <= S_LOAD; sm_state <= S_LOAD;
-- reg_pulse_factors <= ram_pulse_doutb; -- reg_pulse_factors <= ram_pulse_doutb;
-- third quarter of the pulse definition, the length and start address of the wavetable are loaded
reg_pulse_sizes <= ram_pulse_doutb; reg_pulse_sizes <= ram_pulse_doutb;
elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then
-- ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 4); -- ram_pulse_addrb <= std_logic_vector(unsigned(pc) + 4);
sm_state <= S_WAIT; -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state sm_state <= S_WAIT; -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state
-- hold the last pulse definition address as it will be used in the next state
-- reg_pulse_flattop <= ram_pulse_doutb; -- reg_pulse_flattop <= ram_pulse_doutb;
pc <= std_logic_vector(unsigned(pc) + C_PC_INCR); pc <= std_logic_vector(unsigned(pc) + C_PC_INCR); -- incremnet the pulse counter and start waiting to output the wave
-- forth quarter of the pulse definition, the scale factors are loaded
reg_pulse_factors <= ram_pulse_doutb; reg_pulse_factors <= ram_pulse_doutb;
@ -414,6 +419,7 @@ begin
-- Return to idle state if max time is reached. Output waveform value zero. -- Return to idle state if max time is reached. Output waveform value zero.
------------------------------------------------------------------------ ------------------------------------------------------------------------
when S_WAIT => when S_WAIT =>
-- read the last word of the pulse definition, the flat top value
reg_pulse_flattop <= ram_pulse_doutb; reg_pulse_flattop <= ram_pulse_doutb;
-- Start to output wave and increment pulse position RAM address -- Start to output wave and increment pulse position RAM address
if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then