diff --git a/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl b/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
index ca30ede..a76aa60 100644
--- a/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
+++ b/src/hdl/modules/qlaser_dacs_pulse_channel.vhdl
@@ -377,12 +377,14 @@ begin
                     if (unsigned(ram_pulse_addrb) mod 4 = 0) then
                         ram_pulse_addrb  <= std_logic_vector(unsigned(pc) + 1);
                         sm_state            <= S_LOAD;
+                        -- first quarter of the pulse definition, no register is loaded
                         -- reg_pulse_time      <= ram_pulse_doutb;
                         
                     elsif (unsigned(ram_pulse_addrb) mod 4 = 1) then
                         ram_pulse_addrb  <= std_logic_vector(unsigned(pc) + 2);
                         sm_state            <= S_LOAD;
                         -- reg_pulse_sizes     <= ram_pulse_doutb;
+                        -- second quarter of the pulse definition, the start time is loaded
                         reg_pulse_time      <= ram_pulse_doutb;
                         
                         
@@ -390,14 +392,17 @@ begin
                         ram_pulse_addrb  <= std_logic_vector(unsigned(pc) + 3);
                         sm_state            <= S_LOAD;
                         -- reg_pulse_factors   <= ram_pulse_doutb;
+                        -- third quarter of the pulse definition, the length and start address of the wavetable are loaded
                         reg_pulse_sizes     <= ram_pulse_doutb;
                         
 
                     elsif (unsigned(ram_pulse_addrb) mod 4 = 3) then
                         -- ram_pulse_addrb  <= std_logic_vector(unsigned(pc) + 4);
                         sm_state            <= S_WAIT;  -- address is on the forth word of the entry, the loading process is complete. Moving onto the next state
+                        -- hold the last pulse definition address as it will be used in the next state
                         -- reg_pulse_flattop   <= ram_pulse_doutb;
-                        pc                  <= std_logic_vector(unsigned(pc) + C_PC_INCR);
+                        pc                  <= std_logic_vector(unsigned(pc) + C_PC_INCR);  -- incremnet the pulse counter and start waiting to output the wave
+                        -- forth quarter of the pulse definition, the scale factors are loaded
                         reg_pulse_factors   <= ram_pulse_doutb;
                         
 
@@ -414,6 +419,7 @@ begin
                 -- Return to idle state if max time is reached. Output waveform value zero. 
                 ------------------------------------------------------------------------
                 when  S_WAIT    =>
+                    -- read the last word of the pulse definition, the flat top value
                     reg_pulse_flattop   <= ram_pulse_doutb;
                     -- Start to output wave and increment pulse position RAM address
                     if (reg_pulse_time(C_START_TIME - 1 downto 0) = cnt_time) then