42 lines
1.4 KiB
Tcl
42 lines
1.4 KiB
Tcl
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create_project zcu_pulse_channel ../../prj -force
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set_property board_part xilinx.com:zcu102:part0:3.4 [current_project]
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add_files {..\..\src\hdl\modules\qlaser_dacs_pulse_channel.vhdl}
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add_files -fileset sim_1 {..\..\src\hdl\tb\tb_cpubus_dacs_pulse_channel.vhdl}
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add_files {..\..\src\hdl\pkg\qlaser_dac_dc_pkg.vhd}
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add_files {..\..\src\hdl\pkg\qlaser_pkg.vhd}
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add_files {..\..\src\hdl\pkg\iopakp.vhd}
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add_files {..\..\src\hdl\pkg\iopakb.vhd}
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read_ip {..\xilinx-zcu\bram_pulseposition\bram_pulseposition.xci}
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read_ip {..\xilinx-zcu\bram_waveform\bram_waveform.xci}
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read_ip {..\xilinx-zcu\fifo_data_to_stream\fifo_data_to_stream.xci}
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read_ip {..\xilinx-zcu\bram_pulse_definition\bram_pulse_definition.xci}
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# upgrade_ip [get_ips -filter {SCOPE !~ "*.bd"}]
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generate_target all [get_ips -filter {SCOPE !~ "*.bd"}]
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# Run the synthesis and generate the IP output products
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launch_runs synth_1
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# Wait for the synthesis to complete
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wait_on_run synth_1
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# Generate the simulation models
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proc recursive_glob {dir} {
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set files [glob -nocomplain -type f -directory $dir *_sim_netlist.vhdl]
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foreach subdir [glob -nocomplain -type d -directory $dir *] {
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lappend files {*}[recursive_glob $subdir]
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}
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return $files
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}
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set src_dir ../../prj/zcu_pulse_channel.gen/sources_1/ip/
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set files [recursive_glob $src_dir]
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foreach file $files {
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file copy -force $file ../../src/hdl/ip_gen
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}
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exit
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