50 lines
1.9 KiB
Plaintext
50 lines
1.9 KiB
Plaintext
// Test of SUB instruction.
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// Requires:
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// ADDS, SUBS, ADDI & B instructions
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// Expected results:
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// X0 = 1
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// X1 = -1
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// X2 = 2
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// X3 = -3
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// X4 = -2
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// X5 = -5
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// X6 = 0
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// X7 = -6
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// Flags: negative = 1, carry-out = 1, overflow = 0, zero = 0
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//ADDI: I-type, Reg[Rd] = Reg[Rn] + {'0, Imm12}
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//OP Imm12 Rn Rd
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//3322222222 221111111111 00000 00000
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//1098765432 109876543210 98765 43210
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//1001000100 Unsigned 0..31 0..31
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//B: B-type, PC = PC + SignExtend({Imm26, 2'b00})
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//OP Imm26
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//332222 22222211111111110000000000
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//109876 54321098765432109876543210
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//000101 2's Comp Imm26
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//SUBS: R-type, Reg[Rd] = Reg[Rn] - Reg[Rm]
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//OP Rm Shamt Rn Rd
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//33222222222 21111 111111 00000 00000
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//10987654321 09876 543210 98765 43210
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//11101011000 0..31 000000 0..31 0..31
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//ADDS: R-type, Reg[Rd] = Reg[Rn] + Reg[Rm]
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//OP Rm Shamt Rn Rd
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//33222222222 21111 111111 00000 00000
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//10987654321 09876 543210 98765 43210
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//10101011000 0..31 000000 0..31 0..31
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// MAIN:
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1001000100_000000000001_11111_00000 // ADDI X0, X31, #1 // X0 = 1
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11101011000_00000_000000_11111_00001 // SUBS X1, X31, X0 // X1 = -1
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11101011000_00001_000000_00000_00010 // SUBS X2, X0, X1 // X2 = 2
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11101011000_00010_000000_00001_00011 // SUBS X3, X1, X2 // X3 = -3
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11101011000_00001_000000_00011_00100 // SUBS X4, X3, X1 // X4 = -2
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10101011000_00100_000000_00011_00101 // ADDS X5, X3, X4 // X5 = -5
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10101011000_00001_000000_00000_00110 // ADDS X6, X0, X1 // X6 = 0
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10101011000_00101_000000_00001_00111 // ADDS X7, X1, X5 // X7 = -6. Flags: negative, carry-out
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1001000100_000000000000_11111_11111 // ADDI X31, X31, #0 // NOOP - should NOT write the flags.
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000101_00000000000000000000000000 // HALT:B HALT // (HALT = 0)
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1001000100_000000000000_11111_11111 // ADDI X31, X31, #0 // Bogus instruction - pipelined CPU may need it.
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