32 lines
1.1 KiB
Plaintext
32 lines
1.1 KiB
Plaintext
// Test of ADDI instruction, with a final B(ranch) instruction to stay in one place.
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// Requires:
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// ADDI & B instructions
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// Expected results:
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// X0 = 0
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// X1 = 1
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// X2 = 2
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// X3 = 3
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// X4 = 4
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//ADDI: I-type, Reg[Rd] = Reg[Rn] + {'0, Imm12}
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//OP Imm12 Rn Rd
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//3322222222 221111111111 00000 00000
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//1098765432 109876543210 98765 43210
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//1001000100 Unsigned 0..31 0..31
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//B: B-type, PC = PC + SignExtend({Imm26, 2'b00})
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//OP Imm26
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//332222 22222211111111110000000000
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//109876 54321098765432109876543210
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//000101 2's Comp Imm26
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//Note: X31 is always 0.
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// MAIN:
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1001000100_000000000000_11111_00000 // ADDI X0, X31, #0 // X0 = 0
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1001000100_000000000001_00000_00001 // ADDI X1, X0, #1 // X1 = 1
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1001000100_000000000001_00001_00010 // ADDI X2, X1, #1 // X2 = 2
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1001000100_000000000010_00001_00011 // ADDI X3, X1, #2 // X3 = 3
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1001000100_000000000100_00000_00100 // ADDI X4, X0, #4 // X4 = 4
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000101_00000000000000000000000000 // HALT:B HALT // HALT = 0
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1001000100_000000000000_11111_11111 // ADDI X31, X31, #0 // Bogus instruction - pipelined CPU may need it.
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