// Test of LDUR and STUR instructions
// Requires:
// B, ADDI, LDUR, & STUR instructions
// Expected results:
// X0 = 1
// X1 = 2
// X2 = 3
// X3 = 8
// X4 = 11
// X5 = 1
// X6 = 2
// X7 = 3
// Mem[0] = 1

// Mem[8] = 2
// Mem[16] = 3

//ADDI: I-type, Reg[Rd] = Reg[Rn] + {'0, Imm12}
//OP         Imm12        Rn    Rd
//3322222222 221111111111 00000 00000
//1098765432 109876543210 98765 43210
//1001000100 Unsigned     0..31 0..31

//B: B-type, PC = PC + SignExtend({Imm26, 2'b00})
//OP     Imm26
//332222 22222211111111110000000000
//109876 54321098765432109876543210
//000101 2's Comp Imm26

//LDUR: D-type, Reg[Rt] = Mem[Reg[Rn] + SignExtend(Imm9)]
//OP          Imm9      00 Rn    Rt
//33222222222 211111111 11 00000 00000
//10987654321 098765432 10 98765 43210
//11111000010 2's Comp  00 0..31 0..31

//STUR: D-type, Mem[Reg[Rn] + SignExtend(Imm9)] = Reg[Rt]
//OP          Imm9      00 Rn    Rt
//33222222222 211111111 11 00000 00000
//10987654321 098765432 10 98765 43210
//11111000000 2's Comp  00 0..31 0..31

               // MAIN:
1001000100_000000000001_11111_00000    // ADDI X0, X31, #1     // X0 = 1
1001000100_000000000010_11111_00001    // ADDI X1, X31, #2     // X1 = 2
1001000100_000000000011_11111_00010    // ADDI X2, X31, #3     // X2 = 3
1001000100_000000001000_11111_00011    // ADDI X3, X31, #8     // X3 = 8
1001000100_000000001011_11111_00100    // ADDI X4, X31, #11    // X4 = 11
11111000000_000000000_00_11111_00000   // STUR X0, [X31, #0]   // Mem[0] = 1
11111000000_111111101_00_00100_00001   // STUR X1, [X4,  #-3]  // Mem[8] = 2
11111000000_000001000_00_00011_00010   // STUR X2, [X3, #8]    // Mem[16] = 3
11111000010_000000101_00_00100_00111   // LDUR X7, [X4, #5]    // X7 = Mem[16] = 3
11111000010_111111000_00_00011_00101   // LDUR X5, [X3, #-8]   // X5 = Mem[0] = 1
11111000010_000000101_00_00010_00110   // LDUR X6, [X2, #5]    // X6 = Mem[8] = 2
000101_00000000000000000000000000      // HALT:B HALT          // HALT = 0
1001000100_000000000000_11111_11111    // ADDI X31, X31, #0    // Bogus instruction � pipelined CPU may need it