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Pipline_Arm_CPU
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reg results should be signed

This commit is contained in:
Eric Yu 2024-10-05 01:03:20 -07:00
parent 1175313fbd
commit 7b911f354a
2 changed files with 5 additions and 3 deletions
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6
src/hdl/CPU_pipelined.sv
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@ -262,11 +262,13 @@ module CPU_pipelined_testbench();
end end
for (i = 0; i < 32; i = i + 1) begin for (i = 0; i < 32; i = i + 1) begin
$display("X%0d = %0d", i, dut.u_regfile.dataBus[i]); $display("X%0d = %0d", i, $signed(dut.u_regfile.dataBus[i]));
end end
// Addtional signals to display // Addtional signals to display
// $display("Mem[0] = %0d", dut.dmem.mem[0]);
// $display("Mem[8] = %0d", dut.dmem.mem[8]);
// $display("Mem[16] = %0d", dut.dmem.mem[16]);
// //
$display("PC = %0d", dut.pcIF / 4); $display("PC = %0d", dut.pcIF / 4);

2
tools/sim/runs/sim.do
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@ -1,5 +1,5 @@
# Change to path to the benchmark to simulate # Change to path to the benchmark to simulate
set bench_path ../Benchmarks/test04_LdurStur.arm set bench_path ../Benchmarks/test12_Fibonacci.arm
vlib work vlib work