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Pipline_Arm_CPU
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Update README.md

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Eric Yu 2024-02-14 08:23:27 +00:00
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@ -11,15 +11,10 @@ A simple 64-bit ARM CPU with Pipelining. The pipelined CPU will have 1 delay slo
ADDI Rd, Rn, Imm12: Reg[Rd] = Reg[Rn] + ZeroExtend(Imm12).
ADDS Rd, Rn, Rm: Reg[Rd] = Reg[Rn] + Reg[Rm]. Set flags.
B Imm26: PC = PC + SignExtend(Imm26 << 2).
For lab #4 (only) this instr. has a delay slot.
B.LT Imm19: If (flags.negative != flags.overflow) PC = PC + SignExtend(Imm19<<2).
For lab #4 (only) this instr. has a delay slot.
BL Imm26: X30 = PC + 4 (instruction after this one), PC = PC + SignExtend(Imm26<<2).
For lab #4 (only) this instr. has a delay slot.
BR Rd: PC = Reg[Rd].
For lab #4 (only) this instr. has a delay slot.
CBZ Rd, Imm19: If (Reg[Rd] == 0) PC = PC + SignExtend(Imm19<<2).
For lab #4 (only) this instr. has a delay slot.
LDUR Rd, [Rn, #Imm9]: Reg[Rd] = Mem[Reg[Rn] + SignExtend(Imm9)].
For lab #4 (only) the value in rd cannot be used in the next cycle.
STUR Rd, [Rn, #Imm9]: Mem[Reg[Rn] + SignExtend(Imm9)] = Reg[Rd].