more generalized sim.do

README.md

@@ -19,4 +19,15 @@ LDUR Rd, [Rn, #Imm9]: Reg[Rd] = Mem[Reg[Rn] + SignExtend(Imm9)].
 For lab #4 (only) the value in rd cannot be used in the next cycle. 
 STUR Rd, [Rn, #Imm9]: Mem[Reg[Rn] + SignExtend(Imm9)] = Reg[Rd]. 
 SUBS Rd, Rn, Rm: Reg[Rd] = Reg[Rn] - Reg[Rm].  Set flags.
-```
+```
+
+## How to simulate
+1. Navigate to the `tools\sim\runs` directory.
+2. Edit `bench_path` in `sim.do` to point to the desired benchmark (vector) file.
+3. Run the simulation by executing `vsim -c -do sim.do -l vsim.log` in the terminal.
+
+To debug in waveform, run command 
+```
+modelsim -view vsim.wlf -do <path\to\optional\wave.do>
+```
+ where `<path\to\optional\wave.do>` is the path to the .do file containing the waveform settings. There are some in the `tools\sim\waves` directory.

src/hdl/CPU_pipelined.sv

@@ -222,7 +222,8 @@ module CPU_pipelined #(parameter DELAY_NS=0.05) (reset, clk);
 
 endmodule
 
-
+// maximum number of cycles to run the simulation for. Exceeding this limit means something gets stuck in a loop.
+`define MAX_CYCLES 1000000
 module CPU_pipelined_testbench();
 	parameter ClockDelay = 5000;
 
@@ -243,8 +244,32 @@ module CPU_pipelined_testbench();
 
 		reset <= 1; @(posedge clk);
 		reset <= 0; @(posedge clk);  // toggle reset
-        $display("%t begin benchmark", $time);
-        repeat(777) @(posedge clk);  // repeat *many* times to give enough cycyles to calculate everything (~800 for sort)
+        $display("%t begin benchmark %s", $time, `BENCHMARK);
+
+        i = 0;
+        // Continue until the halt instruction is reached or the simulation times out
+        while (dut.u_instructmem.instruction != 32'b00010100000000000000000000000000 && i < `MAX_CYCLES) begin
+            @(posedge clk);
+            i = i + 1;
+        end
+        repeat(5) @(posedge clk);
+        
+        if (i == `MAX_CYCLES) begin
+            $display("Simulation timed out");
+        end
+        else begin
+            $display("Simulation completed in %0d cycles", i+1);
+        end
+
+        for (i = 0; i < 32; i = i + 1) begin
+            $display("X%0d = %0d", i, dut.u_regfile.dataBus[i]);
+        end
+
+        // Addtional signals to display
+
+        // 
+
+        $display("PC = %0d", dut.pcIF / 4);
 		$stop;
 	end
 

tools/sim/runs/run1.do

@@ -1,15 +0,0 @@
-vlib work
-
-vlog ../../../src/hdl/*.sv
-
-vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
-
-do ../waves/test1.do
-
-view wave
-view structure
-view signals
-
-run -all
-
-# End

tools/sim/runs/run10.do

@@ -1,15 +0,0 @@
-vlib work
-
-vlog ../../../src/hdl/*.sv
-
-vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
-
-do ../waves/test10.do
-
-view wave
-view structure
-view signals
-
-run -all
-
-# End

tools/sim/runs/run11.do

@@ -1,15 +0,0 @@
-vlib work
-
-vlog ../../../src/hdl/*.sv
-
-vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
-
-do ../waves/test11.do
-
-view wave
-view structure
-view signals
-
-run -all
-
-# End

tools/sim/runs/run12.do

@@ -1,15 +0,0 @@
-vlib work
-
-vlog ../../../src/hdl/*.sv
-
-vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
-
-do ../waves/test12.do
-
-view wave
-view structure
-view signals
-
-run -all
-
-# End

tools/sim/runs/run2.do

@@ -1,15 +0,0 @@
-vlib work
-
-vlog ../../../src/hdl/*.sv
-
-vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
-
-do ../waves/test2.do
-
-view wave
-view structure
-view signals
-
-run -all
-
-# End

tools/sim/runs/run3.do

@@ -1,15 +0,0 @@
-vlib work
-
-vlog ../../../src/hdl/*.sv
-
-vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
-
-do ../waves/test3.do
-
-view wave
-view structure
-view signals
-
-run -all
-
-# End

tools/sim/runs/run4.do

@@ -1,15 +0,0 @@
-vlib work
-
-vlog ../../../src/hdl/*.sv
-
-vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
-
-do ../waves/test4.do
-
-view wave
-view structure
-view signals
-
-run -all
-
-# End

tools/sim/runs/run5.do

@@ -1,15 +0,0 @@
-vlib work
-
-vlog ../../../src/hdl/*.sv
-
-vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
-
-do ../waves/test5.do
-
-view wave
-view structure
-view signals
-
-run -all
-
-# End

tools/sim/runs/run6.do

@@ -1,15 +0,0 @@
-vlib work
-
-vlog ../../../src/hdl/*.sv
-
-vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
-
-do ../waves/test6.do
-
-view wave
-view structure
-view signals
-
-run -all
-
-# End

tools/sim/runs/sim.do

@@ -0,0 +1,16 @@
+# Change to path to the benchmark to simulate
+set bench_path ../Benchmarks/test04_LdurStur.arm
+
+vlib work
+
+onerror {exit}
+
+vlog ../../../src/hdl/*.sv +define+BENCHMARK="${bench_path}"
+
+vsim -voptargs="+acc" -t 1ns -lib work CPU_pipelined_testbench
+
+log -r /*
+
+run -all
+
+quit -f